A framework where a deep Q-Learning Reinforcement Learning agent tries to choose the correct traffic light phase at an intersection to maximize traffic efficiency.

This repository contains source code for past labs and projects involving FPGA and Verilog based designs

🚥 An Artificial Neural Network based Traffic Light Controller for intersections. Computational Intelligence class final project.

Deep Reinforcement Learning Agent to control traffic light providing emergency facilitation using real-time traffic data.

Reliable Mechanism or circuit made using Arduino Microcontrollers and Radio Frequency Transceiver for Faster Emergency Vehicle Exit In traffic Jams

Discover the world of Racket programming! This repository showcases four projects, including a Trafficlights simulation with Arduino, a Virtual Turing Machine emulator, a regex matcher using FSM, and a Raspberry Pi-controlled network server for MIRTO. Unleash your coding skills with Racket! 🚀🎓🔧

Detect traffic lights and classify the state of them, then give the commands "go" or "stop".

Intelligent Traffic Light Controller

Our open-source academic research files, codes, data, and so on.

A TensorFlow implementation of TrafficLightNeuralNetwork (ANN-based Traffic Light Controller).

simulated the traffic light controller system for simple two-way intersection and for a two-way intersection with traffic sensors, using the Arduino UNO R3 controller in TinkerCAD.

Traffic light controller in VHDL

Microprocessor project: traffic light system (Intel MCS-51/8051 in assembly language)

Primer proyecto del curso Diseño de Sistemas Digitales. La idea es generar un código en ensamblador capaz de resolver un problema de intersección utilizando el lenguaje de programación ARM.

a VHDL code for a traffic light controller on FPGA is presented.

GLD /w model based RL : MDP

An automatic traffic light system built with 8051 and C.

Deep reinforcement learning for traffic light control in transportation networks

In this Project, a sophisticated traffic light controller was developed using Verilog and was implemented on an FPGA (Field-Programmable Gate Array) platform. The primary aim was to simulate a realistic traffic management system, employing a Moore state machine design paradigm.