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chore(h5): update to latest STM32CubeH5 v1.4.0 #2586

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chore(h5): update to latest STM32CubeH5 v1.4.0 #2586

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8ef8b6a
system(H5) update STM32H5xx HAL Drivers to v1.4.0
fpistm Dec 2, 2024
68462f5
system(H5): update STM32H5xx CMSIS Drivers to v1.3.1
fpistm Dec 2, 2024
62168c0
chore(h5): update variants against CubeMX DB release 6.0.130
fpistm Dec 3, 2024
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4 changes: 2 additions & 2 deletions system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h
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Expand Up @@ -186,7 +186,7 @@ typedef enum
/** @} */ /* End of group Configuration_of_CMSIS */


#include <core_cm33.h> /*!< ARM Cortex-M33 processor and core peripherals */
#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */
#include "system_stm32h5xx.h" /*!< STM32H5xx System */


Expand Down Expand Up @@ -13300,7 +13300,7 @@ typedef struct
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI3_NS))

#define IS_SPI_LIMITED_INSTANCE(INSTANCE) ((INSTANCE) == NULL)
#define IS_SPI_LIMITED_INSTANCE(INSTANCE) ((INSTANCE) == ((SPI_TypeDef *) 0xDEADDEADUL))

#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI3_NS))

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2 changes: 1 addition & 1 deletion system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h523xx.h
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Expand Up @@ -215,7 +215,7 @@ typedef enum
/** @} */ /* End of group Configuration_of_CMSIS */


#include <core_cm33.h> /*!< ARM Cortex-M33 processor and core peripherals */
#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */
#include "system_stm32h5xx.h" /*!< STM32H5xx System */


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2 changes: 1 addition & 1 deletion system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h
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Expand Up @@ -218,7 +218,7 @@ typedef enum
/** @} */ /* End of group Configuration_of_CMSIS */


#include <core_cm33.h> /*!< ARM Cortex-M33 processor and core peripherals */
#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */
#include "system_stm32h5xx.h" /*!< STM32H5xx System */


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2 changes: 1 addition & 1 deletion system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h
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Expand Up @@ -234,7 +234,7 @@ typedef enum
/** @} */ /* End of group Configuration_of_CMSIS */


#include <core_cm33.h> /*!< ARM Cortex-M33 processor and core peripherals */
#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */
#include "system_stm32h5xx.h" /*!< STM32H5xx System */


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2 changes: 1 addition & 1 deletion system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h
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Expand Up @@ -239,7 +239,7 @@ typedef enum
/** @} */ /* End of group Configuration_of_CMSIS */


#include <core_cm33.h> /*!< ARM Cortex-M33 processor and core peripherals */
#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */
#include "system_stm32h5xx.h" /*!< STM32H5xx System */


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2 changes: 1 addition & 1 deletion system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h
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Expand Up @@ -242,7 +242,7 @@ typedef enum
/** @} */ /* End of group Configuration_of_CMSIS */


#include <core_cm33.h> /*!< ARM Cortex-M33 processor and core peripherals */
#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */
#include "system_stm32h5xx.h" /*!< STM32H5xx System */


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12 changes: 6 additions & 6 deletions system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h
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Expand Up @@ -57,7 +57,7 @@
application
*/

#if !defined (STM32H573xx) && !defined (STM32H563xx) \
#if !defined (STM32H573xx) && !defined (STM32H563xx) \
&& !defined (STM32H562xx) && !defined (STM32H503xx) \
&& !defined (STM32H533xx) && !defined (STM32H523xx)
/* #define STM32H573xx */ /*!< STM32H573xx Devices */
Expand All @@ -81,12 +81,12 @@
#endif /* USE_HAL_DRIVER */

/**
* @brief CMSIS Device version number 1.3.0
* @brief CMSIS Device version number 1.3.1
*/
#define __STM32H5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32H5_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
#define __STM32H5_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32H5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32H5_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32H5_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32H5_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32H5_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32H5_CMSIS_VERSION ((__STM32H5_CMSIS_VERSION_MAIN << 24U)\
|(__STM32H5_CMSIS_VERSION_SUB1 << 16U)\
|(__STM32H5_CMSIS_VERSION_SUB2 << 8U )\
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19 changes: 15 additions & 4 deletions system/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.html
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Expand Up @@ -30,11 +30,22 @@ <h1 id="release-notes-for-stm32h5xx-cmsis">Release Notes for <mark> STM32H5xx C
<div class="col-sm-12 col-lg-8">
<h1 id="update-history"><strong>Update History</strong></h1>
<div class="collapse">
<input type="checkbox" id="collapse-section4" Checked aria-hidden="true"> <label for="collapse-section4" checked aria-hidden="true"><strong>V1.3.0 / 05-June-2024</strong></label>
<input type="checkbox" id="collapse-section5" Checked aria-hidden="true"> <label for="collapse-section5" checked aria-hidden="true"><strong>V1.3.1 / 30-October-2024</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
<p>CMSIS Device Maintenance Release version of bits and registers definition aligned with <strong>RM0481</strong> (STM32H5 reference manual)</p>
<ul>
<li>Update to use #include "core_cm33.h" instead of #include &lt;core_cm33.h&gt; to force the first searches for the core_cm33.h file in the same directory as the file that contains the #include directive (Drivers\CMSIS\Core\Include)</li>
<li>Update IS_SPI_LIMITED macro to return an essential boolean</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" checked aria-hidden="true"><strong>V1.3.0 / 05-June-2024</strong></label>
<div>
<h2 id="main-changes-1">Main Changes</h2>
<p>CMSIS Device Maintenance Release version of bits and registers definition aligned with <strong>RM0481</strong> (STM32H5 reference manual)</p>
<ul>
<li>Add RNG_CR_NIST_VALUE, RNG_NSCR_NIST_VALUE and RNG_HTCR_NIST_VALUE defines</li>
<li>Add Bits definition for RNG_NSCR register : Add RNG_NSCR_EN_OSC1, RNG_NSCR_EN_OSC2, RNG_NSCR_EN_OSC3, RNG_NSCR_EN_OSC4, RNG_NSCR_EN_OSC5 and RNG_NSCR_EN_OSC6 defines</li>
<li>Add USART_DMAREQUESTS_SW_WA define</li>
Expand All @@ -50,7 +61,7 @@ <h2 id="main-changes">Main Changes</h2>
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" checked aria-hidden="true"><strong>V1.2.0 / 09-February-2024</strong></label>
<div>
<h2 id="main-changes-1">Main Changes</h2>
<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>First official release of STM32H5xx CMSIS drivers to support <strong>STM32H533xx and STM32H523xx</strong> devices</li>
<li>Add bit definition for I3C_BCR register</li>
Expand All @@ -69,7 +80,7 @@ <h2 id="main-changes-1">Main Changes</h2>
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" checked aria-hidden="true"><strong>V1.1.0 / 07-June-2023</strong></label>
<div>
<h2 id="main-changes-2">Main Changes</h2>
<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>Add DUA addresses constants definitions for STM32H573xx devices only</li>
<li>Fix wrong definition of IS_TIM_CLOCKSOURCE_TIX_INSTANCE &amp; IS_TIM_TISEL_INSTANCE macros</li>
Expand All @@ -80,7 +91,7 @@ <h2 id="main-changes-2">Main Changes</h2>
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" checked aria-hidden="true"><strong>V1.0.0 / 10-February-2023</strong></label>
<div>
<h2 id="main-changes-3">Main Changes</h2>
<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>First official release version of bits and registers definition aligned with RM0481 and RM0492 (STM32H5 reference manuals)</li>
</ul>
Expand Down
2 changes: 1 addition & 1 deletion system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
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Expand Up @@ -9,7 +9,7 @@
* STM32F7: 1.2.9
* STM32G0: 1.4.4
* STM32G4: 1.2.5
* STM32H5: 1.3.0
* STM32H5: 1.3.1
* STM32H7: 1.10.4
* STM32L0: 1.9.3
* STM32L1: 2.3.3
Expand Down
77 changes: 67 additions & 10 deletions system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
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Expand Up @@ -472,7 +472,9 @@ extern "C" {
#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5)
#define PAGESIZE FLASH_PAGE_SIZE
#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */
#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
Expand Down Expand Up @@ -601,6 +603,15 @@ extern "C" {
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */

#if defined(STM32U5)

#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster
#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection
#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection

#endif /* STM32U5 */

#if defined(STM32H5)
#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
Expand Down Expand Up @@ -806,6 +817,21 @@ extern "C" {
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
#endif /* STM32U5 */

#if defined(STM32WBA)
#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF
#define GPIO_AF11_RF_IO1 GPIO_AF11_RF
#define GPIO_AF11_RF_IO2 GPIO_AF11_RF
#define GPIO_AF11_RF_IO3 GPIO_AF11_RF
#define GPIO_AF11_RF_IO4 GPIO_AF11_RF
#define GPIO_AF11_RF_IO5 GPIO_AF11_RF
#define GPIO_AF11_RF_IO6 GPIO_AF11_RF
#define GPIO_AF11_RF_IO7 GPIO_AF11_RF
#define GPIO_AF11_RF_IO8 GPIO_AF11_RF
#define GPIO_AF11_RF_IO9 GPIO_AF11_RF
#endif /* STM32WBA */
/**
* @}
*/
Expand Down Expand Up @@ -860,6 +886,10 @@ extern "C" {
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE

#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7)
#define HRTIMInterruptResquests HRTIMInterruptRequests
#endif /* STM32F3 || STM32G4 || STM32H7 */

#if defined(STM32G4)
#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
Expand Down Expand Up @@ -997,8 +1027,8 @@ extern "C" {
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)

#endif /* STM32F3 */

/**
* @}
*/
Expand Down Expand Up @@ -1249,10 +1279,10 @@ extern "C" {
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1

#if defined(STM32H5) || defined(STM32H7RS)
#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
#endif /* STM32H5 || STM32H7RS */
#endif /* STM32H5 || STM32H7RS || STM32N6 */

#if defined(STM32WBA)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
Expand All @@ -1264,10 +1294,10 @@ extern "C" {
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
#endif /* STM32WBA */

#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
#endif /* STM32H5 || STM32WBA || STM32H7RS */
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */

#if defined(STM32F7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
Expand Down Expand Up @@ -1999,12 +2029,12 @@ extern "C" {
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
* @{
*/
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
#endif /* STM32H5 || STM32WBA || STM32H7RS */
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */

/**
* @}
Expand Down Expand Up @@ -3665,7 +3695,7 @@ extern "C" {
#endif

#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
Expand Down Expand Up @@ -3916,8 +3946,8 @@ extern "C" {
*/
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
defined (STM32WBA) || defined (STM32H5) || \
defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \
defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
Expand Down Expand Up @@ -4211,6 +4241,33 @@ extern "C" {

#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
#if defined(STM32U5)
#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD
#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK
#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC
#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST
#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF
#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM
#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM
#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK
#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ
#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT
#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0
#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1
#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM
#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG
#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM
#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM
#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT
#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM
#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM
#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID
#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0
#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1
#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK
#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK
#endif
/**
* @}
*/
Expand Down
4 changes: 2 additions & 2 deletions system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h
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Expand Up @@ -320,10 +320,10 @@ extern HAL_TickFreqTypeDef uwTickFreq;
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */

#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */
#endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */

#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
Expand Down
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