fel: Add support for allwinner T7

Allwinner T7 share the same CCM/UART base address with H6. Add support for it in uart0-helloworld-sdboot. Signed-off-by: qianfan Zhao <[email protected]>
linux-sunxi · Jan 2, 2024 · abe1937 · abe1937
1 parent 6a2f6b5
commit abe1937
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Showing 2 changed files with 39 additions and 2 deletions.
diff --git a/soc_info.c b/soc_info.c
@@ -112,6 +112,23 @@ sram_swap_buffers h6_sram_swap_buffers[] = {
 	{ .size = 0 }  /* End of the table */
 };
 
+/*
+ * T7 SRAM layout:
+ *
+ * SRAM A1: 0x0002_0000 - 0x0002_7fff,  32K contains stacks
+ * SRAM  C: 0x0002_8000 - 0x0004_ffff, 160K full access
+ * SRAM A2: 0x0010_0000 - 0x0010_3fff,  16K unknown part, the data was changed
+ *                                          when read back
+ *          0x0010_4000 - 0x0011_ffff, 112K full access
+ */
+sram_swap_buffers t7_sram_swap_buffers[] = {
+	/* 0x21C00-0x21FFF (IRQ stack) */
+	{ .buf1 = 0x21C00, .buf2 = 0x4d800, .size = 0x0400 },
+	/* 0x25C00-0x27FFF (Stack) */
+	{ .buf1 = 0x25C00, .buf2 = 0x4dc00, .size = 0x2400 },
+	{ .size = 0 }  /* End of the table */
+};
+
 /*
  * V831 has 96KiB SRAM A1 at 0x20000 where the SPL has to be loaded to.
  * SRAM C is continuous with SRAM A1, and both SRAMs are tried to be used
@@ -394,6 +411,18 @@ soc_info_t soc_info_table[] = {
 		.sid_base     = 0x01C23800,
 		.sid_sections = generic_2k_sid_maps,
 		.watchdog     = &wd_h3_compat,
+	},{
+		.soc_id       = 0x1708, /* Allwinner T7 */
+		.name         = "T7",
+		.spl_addr     = 0x20000,
+		.scratch_addr = 0x21000,
+		.thunk_addr   = 0x4d200, .thunk_size = 0x200,
+		.swap_buffers = t7_sram_swap_buffers,
+		.sram_size    = 180 * 1024,
+		.sid_base     = 0x03006000,
+		.sid_offset   = 0x200,
+		.sid_sections = generic_2k_sid_maps,
+		.watchdog     = &wd_h6_compat,
 	},{
 		.soc_id       = 0x1718, /* Allwinner H5 */
 		.name         = "H5",

diff --git a/uart0-helloworld-sdboot.c b/uart0-helloworld-sdboot.c
@@ -145,6 +145,7 @@ enum sunxi_gpio_number {
 #define SUN6I_GPH_UART0         (2)
 #define SUN8I_H3_GPA_UART0      (2)
 #define SUN8I_R528_GPE_UART0	(6)
+#define SUN8I_T7_GPB_UART0	(4)
 #define SUN8I_V3S_GPB_UART0	(3)
 #define SUN8I_V5_GPB_UART0	(2)
 #define SUN8I_V831_GPH_UART0	(5)
@@ -313,6 +314,7 @@ void soc_detection_init(void)
 #define soc_is_h616()	(soc_id == 0x1823)
 #define soc_is_r329()	(soc_id == 0x1851)
 #define soc_is_r40()	(soc_id == 0x1701)
+#define soc_is_t7()	(soc_id == 0x1708)
 #define soc_is_v3s()	(soc_id == 0x1681)
 #define soc_is_v831()	(soc_id == 0x1817)
 #define soc_is_v853()	(soc_id == 0x1886)
@@ -419,7 +421,7 @@ void clock_init_uart_r329(void)
 void clock_init_uart(void)
 {
 	if (soc_is_h6() || soc_is_v831() || soc_is_h616() || soc_is_v5() ||
-	    soc_is_a63())
+	    soc_is_a63() || soc_is_t7())
 		clock_init_uart_h6();
 	else if (soc_is_r329() || soc_is_v853() || soc_is_r528())
 		clock_init_uart_r329();
@@ -513,6 +515,10 @@ void gpio_init(void)
 		sunxi_gpio_set_cfgpin(SUNXI_GPE(2), SUN8I_R528_GPE_UART0);
 		sunxi_gpio_set_cfgpin(SUNXI_GPE(3), SUN8I_R528_GPE_UART0);
 		sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP);
+	} else if (soc_is_t7()) {
+		sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_T7_GPB_UART0);
+		sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_T7_GPB_UART0);
+		sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
 	} else if (soc_is_v5()) {
 		sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V5_GPB_UART0);
 		sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_V5_GPB_UART0);
@@ -624,7 +630,7 @@ int get_boot_device(void)
 void bases_init(void)
 {
 	if (soc_is_h6() || soc_is_v831() || soc_is_h616() || soc_is_v5() ||
-	    soc_is_a63()) {
+	    soc_is_a63() || soc_is_t7()) {
 		pio_base = H6_PIO_BASE;
 		uart0_base = H6_UART0_BASE;
 	} else if (soc_is_r329()) {
@@ -686,6 +692,8 @@ int main(void)
 		uart0_puts("Allwinner V853!\n");
 	else if (soc_is_r528())
 		uart0_puts("Allwinner R528/T113!\n");
+	else if (soc_is_t7())
+		uart0_puts("Allwinner T7!\n");
 	else if (soc_is_v5())
 		uart0_puts("Allwinner V5!\n");
 	else if (soc_is_suniv())