GitHub - ilyajob05/verilog_modules: verilog modules

The library is designed to work on the Nexys 4 Artix-7 FPGA Trainer Board from Digilent

Example of the program on NEXUS 4 https://youtu.be/khbDWAvb528

Name		Name	Last commit message	Last commit date
Latest commit History 15 Commits
LICENSE		LICENSE
README.md		README.md
buttonBlock.v		buttonBlock.v
buttonCleaner.v		buttonCleaner.v
buttonTest.v		buttonTest.v
devider.v		devider.v
drawSVGA.v		drawSVGA.v
pwm2digit.v		pwm2digit.v
pwm_generator.v		pwm_generator.v
rmii_rx.v		rmii_rx.v
rmii_rx_byte.v		rmii_rx_byte.v
rmii_send_pack.v		rmii_send_pack.v
rmii_tx.v		rmii_tx.v
syncLatch.v		syncLatch.v
timer.v		timer.v
timer32.v		timer32.v
uart_rx.v		uart_rx.v
uart_tx.v		uart_tx.v
udp_rx.v		udp_rx.v
udp_tx.v		udp_tx.v