arm64: fix compile failed 'tpidr_el1' undeclared

time/lib_localtime.c: In function 'tz_lock': time/lib_localtime.c:396:7: error: 'tpidr_el1' undeclared (first use in this function) 396 | if (up_interrupt_context() || (sched_idletask() && OSINIT_IDLELOOP())) | ^~~~~~~~~~~~~~~~~~~~ Signed-off-by: ligd <[email protected]>
apache · Nov 17, 2024 · a88652f · a88652f
1 parent dfa24a0
commit a88652f
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Showing 2 changed files with 38 additions and 36 deletions.
diff --git a/arch/arm64/include/arch.h b/arch/arm64/include/arch.h
@@ -34,9 +34,10 @@
 #ifndef __ASSEMBLY__
 #  include <stdint.h>
 #  include <stddef.h>
-#  include <nuttx/macro.h>
 #endif
 
+#include <nuttx/irq.h>
+
 /****************************************************************************
  * Pre-processor Prototypes
  ****************************************************************************/
@@ -53,41 +54,6 @@
 
 #endif /* CONFIG_ARCH_ADDRENV */
 
-/****************************************************************************
- * Name:
- *   read_/write_/zero_/modify_ sysreg
- *
- * Description:
- *
- *   ARMv8 Architecture Registers access method
- *   All the macros need a memory clobber
- *
- ****************************************************************************/
-
-#define read_sysreg(reg)                            \
-  ({                                                \
-    uint64_t __val;                                 \
-    __asm__ volatile ("mrs %0, " STRINGIFY(reg)     \
-                    : "=r" (__val) :: "memory");    \
-    __val;                                          \
-  })
-
-#define write_sysreg(__val, reg)                    \
-  ({                                                \
-    __asm__ volatile ("msr " STRINGIFY(reg) ", %0"  \
-                      : : "r" (__val) : "memory");  \
-  })
-
-#define zero_sysreg(reg)                            \
-  ({                                                \
-    __asm__ volatile ("msr " STRINGIFY(reg) ", xzr" \
-                      ::: "memory");                \
-  })
-
-#define modify_sysreg(v,m,a)                        \
-  write_sysreg((read_sysreg(a) & ~(m)) |            \
-               ((uintptr_t)(v) & (m)), a)
-
 /****************************************************************************
  * Inline functions
  ****************************************************************************/

diff --git a/arch/arm64/include/irq.h b/arch/arm64/include/irq.h
@@ -35,6 +35,7 @@
 #ifndef __ASSEMBLY__
 #  include <stdint.h>
 #  include <arch/syscall.h>
+#  include <nuttx/macro.h>
 #endif
 
 /* Include NuttX-specific IRQ definitions */
@@ -394,6 +395,41 @@ static inline void up_irq_restore(irqstate_t flags)
 #  define up_cpu_index() ((int)MPID_TO_CORE(GET_MPIDR()))
 #endif /* CONFIG_ARCH_HAVE_MULTICPU */
 
+/****************************************************************************
+ * Name:
+ *   read_/write_/zero_/modify_ sysreg
+ *
+ * Description:
+ *
+ *   ARMv8 Architecture Registers access method
+ *   All the macros need a memory clobber
+ *
+ ****************************************************************************/
+
+#define read_sysreg(reg)                            \
+  ({                                                \
+    uint64_t __val;                                 \
+    __asm__ volatile ("mrs %0, " STRINGIFY(reg)     \
+                    : "=r" (__val) :: "memory");    \
+    __val;                                          \
+  })
+
+#define write_sysreg(__val, reg)                    \
+  ({                                                \
+    __asm__ volatile ("msr " STRINGIFY(reg) ", %0"  \
+                      : : "r" (__val) : "memory");  \
+  })
+
+#define zero_sysreg(reg)                            \
+  ({                                                \
+    __asm__ volatile ("msr " STRINGIFY(reg) ", xzr" \
+                      ::: "memory");                \
+  })
+
+#define modify_sysreg(v,m,a)                        \
+  write_sysreg((read_sysreg(a) & ~(m)) |            \
+               ((uintptr_t)(v) & (m)), a)
+
 /****************************************************************************
  * Schedule acceleration macros
  *