Critical bugfix

ChangeLog.md

@@ -4,16 +4,18 @@ This page documents (nearly) all bugfixes and enhancements that produce visible
 ## Changes not yet in release
 Changes listed here are checked in to GitHub ("master" branch unless specifically noted; this is only done when a change involves a large amount of work and breaks the core in the interim, or where the change is considered very high risk, and needs testing by others prior to merging the changes with master). These changes are not yet in any "release" nor can they be installed through board manager, only downloading latest code from github will work. These changes will be included in the listed version, though planned version numbers may change without notice - critical fixes may be inserted before a planned release and the planned release bumped up a version, or versions may go from patch to minor version depending on the scale of changes.
 
-## Planned 2.5.1
-* Added support for serial buffer sizes of 256.
-* Added test for defined(USE_ASM_TXC), USE_ASM_RXC, and USE_ASM_DRE in UART.h so that variants and board definitions can now turn this off.
-* Attempting to use illegal options, like buffer sizes that aren't powers of 2, now errors out.
 
 ### Ongoing
 * Port enhanced documentation from DxCore.
 
 ## Released Versions
 
+## 2.5.1
+* Added support for serial buffer sizes of 256.
+* Added test for defined(USE_ASM_TXC), USE_ASM_RXC, and USE_ASM_DRE in UART.h so that variants and board definitions can now turn this off.
+* Attempting to use illegal options, like buffer sizes that aren't powers of 2, now errors out.
+* **CRITICAL BUGFIX** which could COMPLETELY BREAK SERIAL if the sketch used >8192b of flash, with obtuse and uninformative error messages
+
 ### 2.5.0
 * **New I2C/TWI implementation** (I2C and TWI refer to the same interface, the one provided by Wire.h; don't get me started about how these and the library are named).
   * Support for acting as both master and slave (on the same pins); this configuration, sometimes known as "multi-master", includes not only the simple case of multiple masters and slaves on an I2C bus, each of which is always exclusively either a master or a slave, but also the more complicated case, which has been a frequent request: For the AVR device to act as both master AND slave. It can both initiate transactions with slaves, or respond to transactions initiated by other masters.

megaavr/cores/megatinycore/UART.cpp

@@ -294,7 +294,11 @@ ISR(USART0_DRE_vect, ISR_NAKED) {
       "pop         r29"               "\n\t"  // pop Y
       "pop         r28"               "\n\t"  // finish popping Y
       "brts        .+2"               "\n\t"  // hop over the next insn if T bit set, means entered through do_dre, rather than poll_dre
-      "rjmp _poll_dre_done"           "\n\t"  // we skip this jump.
+#if PROGMEM_SIZE > 0x8192
+      "jmp _poll_dre_done"            "\n\t"  // >8k parts must us jmp, otherwise it will give PCREL error.
+#else
+      "rjmp _poll_dre_done"           "\n\t"  // 8k parts can use RJMP
+#endif
       "pop         r27"               "\n\t"  // and continue with popping registers.
       "pop         r26"               "\n\t"
       "pop         r25"               "\n\t"
@@ -385,7 +389,11 @@ void UartClass::_poll_tx_data_empty(void) {
         #endif
         __asm__ __volatile__(
                 "clt"              "\n\t" // CLear the T flag to signal to the ISR that we got there from here.
-                "rjmp _poll_dre"   "\n\t"
+#if PROGMEM_SIZE > 0x8192
+                "jmp _poll_dre"    "\n\t"
+#else
+                "rjmp _poll_dre"    "\n\t"
+#endif
                 "_poll_dre_done:"    "\n"
 #ifdef USART1
                 ::"z"((uint16_t)thisSerial)

megaavr/platform.txt

@@ -7,7 +7,7 @@
 name=megaTinyCore
 versionnum.major=2
 versionnum.minor=5
-versionnum.patch=0
+versionnum.patch=1
 versionnum.postfix=
 versionnum.released=1