Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Fixes for Xilinx Zynq #499

Open
wants to merge 7 commits into
base: master
Choose a base branch
from
Open

Conversation

dgarske
Copy link
Contributor

@dgarske dgarske commented Aug 27, 2024

Fixes to support wolfBoot native make and gcc-arm cross compiler for Xilinx UltraScale+ MPSoC. ZD 18159
Adjust wolfBoot linker script to not use 0 base
Add documentation about exception level.
Fixes for QSPI bare-metal driver for multi-sector and read return code.
Fixed issue with Xilinx XMSS IMAGE_HEADER_SIZE in documentation. It should be 5000 bytes.
Added support for SHA3 with ARMASM.

@dgarske dgarske self-assigned this Aug 27, 2024
@dgarske dgarske force-pushed the zynqmp_makegcc branch 3 times, most recently from 2cd183c to 23c5076 Compare September 3, 2024 20:27
@dgarske dgarske force-pushed the zynqmp_makegcc branch 8 times, most recently from d7d084b to 39aeed9 Compare November 1, 2024 16:45
…Xilinx UltraScale+ MPSoC. ZD 18159

Adjust wolfBoot linker script to not use 0 base
Add documentation about exception level.
Fixes for QSPI bare-metal driver for multi-sector and read return code.
Fixed issue with Xilinx XMSS IMAGE_HEADER_SIZE in documentation. It should be 5000 bytes.
Added support for SHA3 with ARMASM.
@dgarske dgarske marked this pull request as ready for review November 26, 2024 17:34
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant