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Wrong PLL Factors #1

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LnnrtS opened this issue Nov 14, 2016 · 2 comments
Open

Wrong PLL Factors #1

LnnrtS opened this issue Nov 14, 2016 · 2 comments
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@LnnrtS
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LnnrtS commented Nov 14, 2016

You adapted HSE_VALUE to match the development board's crystal. In hardware/system_stm32f4xx.c the PLL factors are set but they are hardcoded and not calculated from HSE_VALUE. The resulting system clock is around factor 3 lower than indented.
The easiest hack would be to change PLL_M to 8 but it's certainly not the cleanest solution.

@wangyeee wangyeee self-assigned this Nov 14, 2016
@wangyeee
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Good catch!
I think I've blindly used latest version of system_stm32f4xx.c in ST's STM32F4xx_StdPeriph_Driver_v1.6.1. Will find a better solution than hardcoding.

@LnnrtS
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LnnrtS commented Nov 15, 2016

setting PLL_M to HSE_VALUE/1000000u also is an easy fix. But whole file seems not to be designed for variable crystal values anyways..
Thanks for your reply!

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