Project Combine

An FPGA reverse engineering project.

Generated documentation

See https://prjunnamed.github.io/prjcombine/

IRC and Matrix channel

#prjcombine on libera.chat
#prjcombine:catircservices.org on matrix (bridged with IRC)
channel logs

Roadmap

phase 1: geometry database extraction
phase 2: bitstream reverse engineering
phase 3: timing database extraction
phase 4: in-hardware test, documentation writing, final database export

Status

Xilinx XC9500/XC9500XL/XC9500XV CPLDs: phase 4 complete
Xilinx/Philips Coolrunner XPLA3 CPLDs: phase 4 complete
Xilinx Coolrunner 2 CPLDs: phase 4 in progress
Xilinx FPGAs:
- XC2000, XC2000L: phase 2 complete
- XC3000, XC3100: phase 2 complete
- XC3000A, XC3100A, XC3000L, XC3100L: phase 2 complete
- XC4000, XC4000D: phase 2 complete
- XC4000A: phase 2 complete
- XC4000H: phase 2 complete
- XC4000E, XC4000L, Spartan: phase 2 complete
- XC4000EX, XC4000XL: phase 2 complete
- XC4000XLA: phase 2 complete
- XC4000XV: phase 2 complete
- Spartan XL: phase 2 complete
- Virtex, Virtex E, Spartan 2, Spartan 2E: phase 2 complete
- Virtex 2, Virtex 2 Pro: phase 2 complete
- Spartan 3, Spartan 3E, Spartan 3A, Spartan 3AN, Spartan 3A DSP: phase 2 complete
- FPGAcore: phase 2 complete
- Spartan 6: phase 2 complete
- Virtex 4: phase 2 complete
- Virtex 5: phase 2 complete
- Virtex 6: phase 2 complete
- Virtex 7, Kintex 7, Artix 7, Spartan 7, Zynq 7000: phase 2 complete
- Ultrascale: phase 1 complete
- Ultrascale+: phase 1 complete
- Versal: phase 1 in progress