From 881faa65584ccd379a843303d91fb6e3f886cde3 Mon Sep 17 00:00:00 2001 From: Maximilian Gerhardt Date: Wed, 10 Feb 2021 20:05:43 +0100 Subject: [PATCH 01/11] Add SVD files for ATMega chips Output of the https://github.com/Rahix/avr-device tool (all `*.svd.patched` files renamd to `*.svd`). Created as descripted in [community post](https://community.platformio.org/t/avr-simulator-as-aid-tool-for-debugging-code/13444/44?u=maxgerhardt) The SVD files are not yet referenced in the board JSON files because the parser in VSCode throws an error and in CLion it can parse the file but cannot read out the registers (possible `avr-gdb` issue). Other issues will be opened for this. --- misc/svd/atmega1280.svd | 6463 +++++++++++++ misc/svd/atmega168.svd | 3030 ++++++ misc/svd/atmega2560.svd | 6318 +++++++++++++ misc/svd/atmega328p.svd | 3040 ++++++ misc/svd/atmega328pb.svd | 4127 +++++++++ misc/svd/atmega32u4.svd | 4649 ++++++++++ misc/svd/atmega4809.svd | 18369 +++++++++++++++++++++++++++++++++++++ misc/svd/atmega48p.svd | 2944 ++++++ misc/svd/atmega64.svd | 4326 +++++++++ misc/svd/atmega644.svd | 3479 +++++++ misc/svd/atmega8.svd | 2775 ++++++ misc/svd/attiny84.svd | 1627 ++++ misc/svd/attiny841.svd | 3309 +++++++ misc/svd/attiny85.svd | 1792 ++++ misc/svd/attiny861.svd | 2354 +++++ misc/svd/attiny88.svd | 2237 +++++ 16 files changed, 70839 insertions(+) create mode 100644 misc/svd/atmega1280.svd create mode 100644 misc/svd/atmega168.svd create mode 100644 misc/svd/atmega2560.svd create mode 100644 misc/svd/atmega328p.svd create mode 100644 misc/svd/atmega328pb.svd create mode 100644 misc/svd/atmega32u4.svd create mode 100644 misc/svd/atmega4809.svd create mode 100644 misc/svd/atmega48p.svd create mode 100644 misc/svd/atmega64.svd create mode 100644 misc/svd/atmega644.svd create mode 100644 misc/svd/atmega8.svd create mode 100644 misc/svd/attiny84.svd create mode 100644 misc/svd/attiny841.svd create mode 100644 misc/svd/attiny85.svd create mode 100644 misc/svd/attiny861.svd create mode 100644 misc/svd/attiny88.svd diff --git a/misc/svd/atmega1280.svd b/misc/svd/atmega1280.svd new file mode 100644 index 0000000..1ba49c2 --- /dev/null +++ b/misc/svd/atmega1280.svd @@ -0,0 +1,6463 @@ + + Atmel + ATmega1280 + 8 + 8 + read-write + 0 + 0xff + + + AC + Analog Comparator + 0x50 + + + ACSR + Analog Comparator Control And Status Register + 0x0 + read-write + + + ACIS + Analog Comparator Interrupt Mode Select + [1:0] + + true + + ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 + + + ACIC + Analog Comparator Input Capture Enable + [2:2] + + + ACIE + Analog Comparator Interrupt Enable + [3:3] + + + ACI + Analog Comparator Interrupt Flag + [4:4] + + + ACO + Analog Compare Output + [5:5] + read-only + + ACBG + Analog Comparator Bandgap Select + [6:6] + + + ACD + Analog Comparator Disable + [7:7] + + + + + ADCSRB + ADC Control and Status Register B + 0x2B + + + ACME + Analog Comparator Multiplexer Enable + [6:6] + + + + + DIDR1 + Digital Input Disable Register 1 + 0x2F + + + AIN0D + AIN0 Digital Input Disable + [0:0] + + + AIN1D + AIN1 Digital Input Disable + [1:1] + + + + + + + ADC + Analog-to-Digital Converter + 0x78 + + + ADC + ADC Data Register Bytes + 0x0 + 16 + + + 0 + 65535 + + + + + ADCSRA + The ADC Control and Status register A + 0x2 + read-write + + + ADPS + ADC Prescaler Select Bits + [2:0] + + true + + ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 + + + ADIE + ADC Interrupt Enable + [3:3] + + + ADIF + ADC Interrupt Flag + [4:4] + + + ADATE + ADC Auto Trigger Enable + [5:5] + + + ADSC + ADC Start Conversion + [6:6] + + + ADEN + ADC Enable + [7:7] + + + + + ADCSRB + The ADC Control and Status register B + 0x3 + + + ADTS + ADC Auto Trigger Source bits + [2:0] + + true + + + + VAL_0x00 + Free Running mode + 0 + + + VAL_0x01 + Analog Comparator + 1 + + + VAL_0x02 + External Interrupt Request 0 + 2 + + + VAL_0x03 + Timer/Counter0 Compare Match A + 3 + + + VAL_0x04 + Timer/Counter0 Overflow + 4 + + + VAL_0x05 + Timer/Counter1 Compare Match B + 5 + + + VAL_0x06 + Timer/Counter1 Overflow + 6 + + + VAL_0x07 + Timer/Counter1 Capture Event + 7 + + + + + MUX5 + Analog Channel and Gain Selection Bits + [3:3] + + + ACME + <TBD> + [6:6] + + + + + ADMUX + The ADC multiplexer Selection Register + 0x4 + + + MUX + Analog Channel and Gain Selection Bits + [4:0] + + + 0 + 31 + + + + + ADLAR + Left Adjust Result + [5:5] + + + REFS + Reference Selection Bits + [7:6] + + true + + REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 + + + + + DIDR0 + Digital Input Disable Register + 0x6 + + + ADC0D + <TBD> + [0:0] + + + ADC1D + <TBD> + [1:1] + + + ADC2D + <TBD> + [2:2] + + + ADC3D + <TBD> + [3:3] + + + ADC4D + <TBD> + [4:4] + + + ADC5D + <TBD> + [5:5] + + + ADC6D + <TBD> + [6:6] + + + ADC7D + <TBD> + [7:7] + + + + + DIDR2 + Digital Input Disable Register + 0x5 + + + ADC8D + <TBD> + [0:0] + + + ADC9D + <TBD> + [1:1] + + + ADC10D + <TBD> + [2:2] + + + ADC11D + <TBD> + [3:3] + + + ADC12D + <TBD> + [4:4] + + + ADC13D + <TBD> + [5:5] + + + ADC14D + <TBD> + [6:6] + + + ADC15D + <TBD> + [7:7] + + + + + + + BOOT_LOAD + Bootloader + 0x57 + + + SPMCSR + Store Program Memory Control Register + 0x0 + + + SPMEN + Store Program Memory Enable + [0:0] + + + PGERS + Page Erase + [1:1] + + + PGWRT + Page Write + [2:2] + + + BLBSET + Boot Lock Bit Set + [3:3] + + + RWWSRE + Read While Write section read enable + [4:4] + + + SIGRD + Signature Row Read + [5:5] + + + RWWSB + Read While Write Section Busy + [6:6] + + + SPMIE + SPM Interrupt Enable + [7:7] + + + + + + + CPU + CPU Registers + 0x3E + + RESET + External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + 0 + + + INT0 + External Interrupt Request 0 + 1 + + + INT1 + External Interrupt Request 1 + 2 + + + INT2 + External Interrupt Request 2 + 3 + + + INT3 + External Interrupt Request 3 + 4 + + + INT4 + External Interrupt Request 4 + 5 + + + INT5 + External Interrupt Request 5 + 6 + + + INT6 + External Interrupt Request 6 + 7 + + + INT7 + External Interrupt Request 7 + 8 + + + PCINT0 + Pin Change Interrupt Request 0 + 9 + + + PCINT1 + Pin Change Interrupt Request 1 + 10 + + + PCINT2 + Pin Change Interrupt Request 2 + 11 + + + WDT + Watchdog Time-out Interrupt + 12 + + + TIMER2_COMPA + Timer/Counter2 Compare Match A + 13 + + + TIMER2_COMPB + Timer/Counter2 Compare Match B + 14 + + + TIMER2_OVF + Timer/Counter2 Overflow + 15 + + + TIMER1_CAPT + Timer/Counter1 Capture Event + 16 + + + TIMER1_COMPA + Timer/Counter1 Compare Match A + 17 + + + TIMER1_COMPB + Timer/Counter1 Compare Match B + 18 + + + TIMER1_COMPC + Timer/Counter1 Compare Match C + 19 + + + TIMER1_OVF + Timer/Counter1 Overflow + 20 + + + TIMER0_COMPA + Timer/Counter0 Compare Match A + 21 + + + TIMER0_COMPB + Timer/Counter0 Compare Match B + 22 + + + TIMER0_OVF + Timer/Counter0 Overflow + 23 + + + SPI_STC + SPI Serial Transfer Complete + 24 + + + USART0_RX + USART0, Rx Complete + 25 + + + USART0_UDRE + USART0 Data register Empty + 26 + + + USART0_TX + USART0, Tx Complete + 27 + + + ANALOG_COMP + Analog Comparator + 28 + + + ADC + ADC Conversion Complete + 29 + + + EE_READY + EEPROM Ready + 30 + + + TIMER3_CAPT + Timer/Counter3 Capture Event + 31 + + + TIMER3_COMPA + Timer/Counter3 Compare Match A + 32 + + + TIMER3_COMPB + Timer/Counter3 Compare Match B + 33 + + + TIMER3_COMPC + Timer/Counter3 Compare Match C + 34 + + + TIMER3_OVF + Timer/Counter3 Overflow + 35 + + + USART1_RX + USART1, Rx Complete + 36 + + + USART1_UDRE + USART1 Data register Empty + 37 + + + USART1_TX + USART1, Tx Complete + 38 + + + TWI + 2-wire Serial Interface + 39 + + + SPM_READY + Store Program Memory Read + 40 + + + TIMER4_CAPT + Timer/Counter4 Capture Event + 41 + + + TIMER4_COMPA + Timer/Counter4 Compare Match A + 42 + + + TIMER4_COMPB + Timer/Counter4 Compare Match B + 43 + + + TIMER4_COMPC + Timer/Counter4 Compare Match C + 44 + + + TIMER4_OVF + Timer/Counter4 Overflow + 45 + + + TIMER5_CAPT + Timer/Counter5 Capture Event + 46 + + + TIMER5_COMPA + Timer/Counter5 Compare Match A + 47 + + + TIMER5_COMPB + Timer/Counter5 Compare Match B + 48 + + + TIMER5_COMPC + Timer/Counter5 Compare Match C + 49 + + + TIMER5_OVF + Timer/Counter5 Overflow + 50 + + + USART2_RX + USART2, Rx Complete + 51 + + + USART2_UDRE + USART2 Data register Empty + 52 + + + USART2_TX + USART2, Tx Complete + 53 + + + USART3_RX + USART3, Rx Complete + 54 + + + USART3_UDRE + USART3 Data register Empty + 55 + + + USART3_TX + USART3, Tx Complete + 56 + + + + CLKPR + <TBD> + 0x23 + + + CLKPS + <TBD> + [3:0] + + true + + + + VAL_0x00 + 1 + 0 + + + VAL_0x01 + 2 + 1 + + + VAL_0x02 + 4 + 2 + + + VAL_0x03 + 8 + 3 + + + VAL_0x04 + 16 + 4 + + + VAL_0x05 + 32 + 5 + + + VAL_0x06 + 64 + 6 + + + VAL_0x07 + 128 + 7 + + + VAL_0x08 + 256 + 8 + + + + + CLKPCE + <TBD> + [7:7] + + + + + EIND + Extended Indirect Register + 0x1E + + + 0 + 255 + + + + + GPIOR0 + General Purpose IO Register 0 + 0x0 + + + GPIOR00 + General Purpose IO Register 0 bit 0 + [0:0] + + + GPIOR01 + General Purpose IO Register 0 bit 1 + [1:1] + + + GPIOR02 + General Purpose IO Register 0 bit 2 + [2:2] + + + GPIOR03 + General Purpose IO Register 0 bit 3 + [3:3] + + + GPIOR04 + General Purpose IO Register 0 bit 4 + [4:4] + + + GPIOR05 + General Purpose IO Register 0 bit 5 + [5:5] + + + GPIOR06 + General Purpose IO Register 0 bit 6 + [6:6] + + + GPIOR07 + General Purpose IO Register 0 bit 7 + [7:7] + + + + + GPIOR1 + General Purpose IO Register 1 + 0xC + + + GPIOR + General Purpose IO Register 1 bis + [7:0] + + + 0 + 255 + + + + + + + GPIOR2 + General Purpose IO Register 2 + 0xD + + + GPIOR + General Purpose IO Register 2 bis + [7:0] + + + 0 + 255 + + + + + + + MCUCR + MCU Control Register + 0x17 + + + IVCE + Interrupt Vector Change Enable + [0:0] + + + IVSEL + Interrupt Vector Select + [1:1] + + + PUD + Pull-up disable + [4:4] + + + JTD + JTAG Interface Disable + [7:7] + + + + + MCUSR + MCU Status Register + 0x16 + read-only + + + PORF + Power-on reset flag + [0:0] + + + EXTRF + External Reset Flag + [1:1] + + + BORF + Brown-out Reset Flag + [2:2] + + + WDRF + Watchdog Reset Flag + [3:3] + + + JTRF + JTAG Reset Flag + [4:4] + + + + + OSCCAL + Oscillator Calibration Value + 0x28 + + + OSCCAL + Oscillator Calibration + [7:0] + + + 0 + 255 + + + + + + + PRR0 + Power Reduction Register0 + 0x26 + + + PRADC + Power Reduction ADC + [0:0] + + + PRUSART0 + Power Reduction USART0 + [1:1] + + + PRSPI + Power Reduction Serial Peripheral Interface + [2:2] + + + PRTIM1 + Power Reduction Timer/Counter1 + [3:3] + + + PRTIM0 + Power Reduction Timer/Counter0 + [5:5] + + + PRTIM2 + Power Reduction Timer/Counter2 + [6:6] + + + PRTWI + Power Reduction TWI + [7:7] + + + + + PRR1 + Power Reduction Register1 + 0x27 + + + PRUSART1 + Power Reduction USART1 + [0:0] + + + PRUSART2 + Power Reduction USART2 + [1:1] + + + PRUSART3 + Power Reduction USART3 + [2:2] + + + PRTIM3 + Power Reduction Timer/Counter3 + [3:3] + + + PRTIM4 + Power Reduction Timer/Counter4 + [4:4] + + + PRTIM5 + Power Reduction Timer/Counter5 + [5:5] + + + + + RAMPZ + RAM Page Z Select Register + 0x1D + + + 0 + 255 + + + + + SMCR + Sleep Mode Control Register + 0x15 + + + SE + Sleep Enable + [0:0] + + + SM + Sleep Mode Select bits + [3:1] + + true + + + + IDLE + Idle + 0 + + + ADC + ADC Noise Reduction (If Available) + 1 + + + PDOWN + Power Down + 2 + + + PSAVE + Power Save + 3 + + + VAL_0x04 + Reserved + 4 + + + VAL_0x05 + Reserved + 5 + + + STDBY + Standby + 6 + + + ESTDBY + Extended Standby + 7 + + + + + + + XMCRA + External Memory Control Register A + 0x36 + + + SRW0 + Wait state select bit lower page + [1:0] + + true + + + + VAL_0x00 + No wait-states + 0 + + + VAL_0x01 + Wait one cycle during read/write strobe + 1 + + + VAL_0x02 + Wait two cycles during read/write strobe + 2 + + + VAL_0x03 + Wait two cycles during read/write and wait one cycle before driving out new address + 3 + + + + + SRW1 + Wait state select bit upper page + [3:2] + + true + + + + VAL_0x00 + No wait-states + 0 + + + VAL_0x01 + Wait one cycle during read/write strobe + 1 + + + VAL_0x02 + Wait two cycles during read/write strobe + 2 + + + VAL_0x03 + Wait two cycles during read/write and wait one cycle before driving out new address + 3 + + + + + SRL + Wait state page limit + [6:4] + + true + + + + VAL_0x00 + LS = N/A, US = 0x1100 - 0xFFFF + 0 + + + VAL_0x01 + LS = 0x2200 - 0x1FFF, US = 0x2000 - 0xFFFF + 1 + + + VAL_0x02 + LS = 0x2200 - 0x3FFF, US = 0x4000 - 0xFFFF + 2 + + + VAL_0x03 + LS = 0x2200 - 0x5FFF, US = 0x6000 - 0xFFFF + 3 + + + VAL_0x04 + LS = 0x2200 - 0x7FFF, US = 0x8000 - 0xFFFF + 4 + + + VAL_0x05 + LS = 0x2200 - 0x9FFF, US = 0xA000 - 0xFFFF + 5 + + + VAL_0x06 + LS = 0x2200 - 0xBFFF, US = 0xC000 - 0xFFFF + 6 + + + VAL_0x07 + LS = 0x2200 - 0xDFFF, US = 0xE000 - 0xFFFF + 7 + + + + + SRE + External SRAM Enable + [7:7] + + + + + XMCRB + External Memory Control Register B + 0x37 + + + XMM + External Memory High Mask + [2:0] + + + 0 + 7 + + + + + XMBK + External Memory Bus Keeper Enable + [7:7] + + + + + + + EEPROM + EEPROM + 0x3F + + + EEAR + EEPROM Address Register Low Bytes + 0x2 + 16 + + + 0 + 65535 + + + + + EECR + EEPROM Control Register + 0x0 + + + EERE + EEPROM Read Enable + [0:0] + + + EEPE + EEPROM Write Enable + [1:1] + + + EEMPE + EEPROM Master Write Enable + [2:2] + + + EERIE + EEPROM Ready Interrupt Enable + [3:3] + + + EEPM + EEPROM Programming Mode Bits + [5:4] + + true + + + + VAL_0x00 + Erase and Write in one operation + 0 + + + VAL_0x01 + Erase Only + 1 + + + VAL_0x02 + Write Only + 2 + + + + + + + EEDR + EEPROM Data Register + 0x1 + + + 0 + 255 + + + + + + + EXINT + External Interrupts + 0x3B + + + EICRA + External Interrupt Control Register A + 0x2E + + + ISC0 + External Interrupt Sense Control Bit + [1:0] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC1 + External Interrupt Sense Control Bit + [3:2] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC2 + External Interrupt Sense Control Bit + [5:4] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC3 + External Interrupt Sense Control Bit + [7:6] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + + + EICRB + External Interrupt Control Register B + 0x2F + + + ISC4 + External Interrupt 7-4 Sense Control Bit + [1:0] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC5 + External Interrupt 7-4 Sense Control Bit + [3:2] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC6 + External Interrupt 7-4 Sense Control Bit + [5:4] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC7 + External Interrupt 7-4 Sense Control Bit + [7:6] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + + + EIFR + External Interrupt Flag Register + 0x1 + read-only + + + INTF + External Interrupt Flags + [7:0] + + + 0 + 255 + + + + + + + EIMSK + External Interrupt Mask Register + 0x2 + + + INT + External Interrupt Request 7 Enable + [7:0] + + + 0 + 255 + + + + + + + PCICR + Pin Change Interrupt Control Register + 0x2D + + + PCIE + Pin Change Interrupt Enables + [2:0] + + + 0 + 7 + + + + + + + PCIFR + Pin Change Interrupt Flag Register + 0x0 + read-only + + + PCIF + Pin Change Interrupt Flags + [2:0] + + + 0 + 7 + + + + + + + PCMSK0 + Pin Change Mask Register 0 + 0x30 + + + PCINT + Pin Change Enable bits + [7:0] + + + 0 + 255 + + + + + + + PCMSK1 + Pin Change Mask Register 1 + 0x31 + + + PCINT + Pin Change Enable bits + [7:0] + + + 0 + 255 + + + + + + + PCMSK2 + Pin Change Mask Register 2 + 0x32 + + + PCINT + Pin Change Enable bits + [7:0] + + + 0 + 255 + + + + + + + + + FUSE + Fuses + 0x0 + + + EXTENDED + <TBD> + 0x2 + + + BODLEVEL + Brown-out Detector trigger level + [2:0] + + true + + + + 4V3 + Brown-out detection at VCC=4.3 V + 4 + + + 2V7 + Brown-out detection at VCC=2.7 V + 5 + + + 1V8 + Brown-out detection at VCC=1.8 V + 6 + + + DISABLED + Brown-out detection disabled + 7 + + + + + + + HIGH + <TBD> + 0x1 + + + BOOTRST + Boot Reset vector Enabled + [0:0] + + + BOOTSZ + Select Boot Size + [2:1] + + true + + + + 4096W_F000 + Boot Flash size=4096 words start address=$F000 + 0 + + + 2048W_F800 + Boot Flash size=2048 words start address=$F800 + 1 + + + 1024W_FC00 + Boot Flash size=1024 words start address=$FC00 + 2 + + + 512W_FE00 + Boot Flash size=512 words start address=$FE00 + 3 + + + + + EESAVE + Preserve EEPROM through the Chip Erase cycle + [3:3] + + + WDTON + Watchdog timer always on + [4:4] + + + SPIEN + Serial program downloading (SPI) enabled + [5:5] + + + JTAGEN + JTAG Interface Enabled + [6:6] + + + OCDEN + On-Chip Debug Enabled + [7:7] + + + + + LOW + <TBD> + 0x0 + + + SUT_CKSEL + Select Clock Source + [5:0] + + true + + + + EXTCLK_6CK_0MS + Ext. Clock; Start-up time: 6 CK + 0 ms + 0 + + + INTRCOSC_6CK_0MS + Int. RC Osc.; Start-up time: 6 CK + 0 ms + 2 + + + INTRCOSC_128KHZ_6CK_0MS + Int. 128kHz RC Osc.; Start-up time: 6 CK + 0 ms + 3 + + + EXTLOFXTAL_1KCK_0MS + Ext. Low-Freq. Crystal; Start-up time: 1K CK + 0 ms + 4 + + + EXTLOFXTAL_32KCK_0MS + Ext. Low-Freq. Crystal; Start-up time: 32K CK + 0 ms + 5 + + + FSOSC_258CK_4MS1_CRES_FASTPWR + Full Swing Oscillator; Start-up time: 258 CK + 4.1 ms; Ceramic res.; fast rising power + 6 + + + FSOSC_1KCK_65MS_CRES_SLOWPWR + Full Swing Oscillator; Start-up time: 1K CK + 65 ms; Ceramic res.; slowly rising power + 7 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 258 CK + 4.1 ms + 8 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 65 ms + 9 + + + EXTXOSC_0MHZ9_3MHZ_258CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 258 CK + 4.1 ms + 10 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 65 ms + 11 + + + EXTXOSC_3MHZ_8MHZ_258CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 258 CK + 4.1 ms + 12 + + + EXTXOSC_3MHZ_8MHZ_1KCK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 65 ms + 13 + + + EXTXOSC_8MHZ_XX_258CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time: 258 CK + 4.1 ms + 14 + + + EXTXOSC_8MHZ_XX_1KCK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 65 ms + 15 + + + EXTCLK_6CK_4MS1 + Ext. Clock; Start-up time: 6 CK + 4.1 ms + 16 + + + INTRCOSC_6CK_4MS1 + Int. RC Osc.; Start-up time: 6 CK + 4.1 ms + 18 + + + INTRCOSC_128KHZ_6CK_4MS + Int. 128kHz RC Osc.; Start-up time: 6 CK + 4 ms + 19 + + + EXTLOFXTAL_1KCK_4MS1 + Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4.1 ms + 20 + + + EXTLOFXTAL_32KCK_4MS1 + Ext. Low-Freq. Crystal; Start-up time: 32K CK + 4.1 ms + 21 + + + FSOSC_258CK_65MS_CRES_SLOWPWR + Full Swing Oscillator; Start-up time: 258 CK + 65 ms; Ceramic res.; slowly rising power + 22 + + + FSOSC_16KCK_0MS_XOSC_BODEN + Full Swing Oscillator; Start-up time: 16K CK + 0 ms; Crystal Osc.; BOD enabled + 23 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 258 CK + 65 ms + 24 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 0 ms + 25 + + + EXTXOSC_0MHZ9_3MHZ_258CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 258 CK + 65 ms + 26 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 0 ms + 27 + + + EXTXOSC_3MHZ_8MHZ_258CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 258 CK + 65 ms + 28 + + + EXTXOSC_3MHZ_8MHZ_16KCK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 0 ms + 29 + + + EXTXOSC_8MHZ_XX_258CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 258 CK + 65 ms + 30 + + + EXTXOSC_8MHZ_XX_16KCK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 0 ms + 31 + + + EXTCLK_6CK_65MS + Ext. Clock; Start-up time: 6 CK + 65 ms + 32 + + + INTRCOSC_6CK_65MS + Int. RC Osc.; Start-up time: 6 CK + 65 ms + 34 + + + INTRCOSC_128KHZ_6CK_64MS + Int. 128kHz RC Osc.; Start-up time: 6 CK + 64 ms + 35 + + + EXTLOFXTAL_1KCK_65MS + Ext. Low-Freq. Crystal; Start-up time: 1K CK + 65 ms + 36 + + + EXTLOFXTAL_32KCK_65MS + Ext. Low-Freq. Crystal; Start-up time: 32K CK + 65 ms + 37 + + + FSOSC_1KCK_0MS_CRES_BODEN + Full Swing Oscillator; Start-up time: 1K CK + 0 ms; Ceramic res.; BOD enable + 38 + + + FSOSC_16KCK_4MS1_XOSC_FASTPWR + Full Swing Oscillator; Start-up time: 16K CK + 4.1 ms; Crystal Osc.; fast rising power + 39 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 0 ms + 40 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 4.1 ms + 41 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 0 ms + 42 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 4.1 ms + 43 + + + EXTXOSC_3MHZ_8MHZ_1KCK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 0 ms + 44 + + + EXTXOSC_3MHZ_8MHZ_16KCK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 4.1 ms + 45 + + + EXTXOSC_8MHZ_XX_1KCK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 0 ms + 46 + + + EXTXOSC_8MHZ_XX_16KCK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 4.1 ms + 47 + + + FSOSC_1KCK_4MS1_CRES_FASTPWR + Full Swing Oscillator; Start-up time: 1K CK + 4.1 ms; Ceramic res.; fast rising power + 54 + + + FSOSC_16KCK_65MS_XOSC_SLOWPWR + Full Swing Oscillator; Start-up time: 16K CK + 65 ms; Crystal Osc.; slowly rising power + 55 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 4.1 ms + 56 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 65 ms + 57 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 4.1 ms + 58 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 65 ms + 59 + + + EXTXOSC_3MHZ_8MHZ_1KCK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 4.1 ms + 60 + + + EXTXOSC_3MHZ_8MHZ_16KCK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 65 ms + 61 + + + EXTXOSC_8MHZ_XX_1KCK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 4.1 ms + 62 + + + EXTXOSC_8MHZ_XX_16KCK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 65 ms + 63 + + + + + CKOUT + Clock output on PORTE7 + [6:6] + + + CKDIV8 + Divide clock by 8 internally + [7:7] + + + + + + + JTAG + JTAG Interface + 0x51 + + + MCUCR + MCU Control Register + 0x4 + + + JTD + JTAG Interface Disable + [7:7] + + + + + MCUSR + MCU Status Register + 0x3 + read-only + + + JTRF + JTAG Reset Flag + [4:4] + + + + + OCDR + On-Chip Debug Related Register in I/O Memory + 0x0 + + + 0 + 255 + + + + + + + LOCKBIT + Lockbits + 0x0 + + + LOCKBIT + <TBD> + 0x0 + + + LB + Memory Lock + [1:0] + + true + + + + PROG_VER_DISABLED + Further programming and verification disabled + 0 + + + PROG_DISABLED + Further programming disabled + 2 + + + NO_LOCK + No memory lock features enabled + 3 + + + + + BLB0 + Boot Loader Protection Mode + [3:2] + + true + + + + LPM_SPM_DISABLE + LPM and SPM prohibited in Application Section + 0 + + + LPM_DISABLE + LPM prohibited in Application Section + 1 + + + SPM_DISABLE + SPM prohibited in Application Section + 2 + + + NO_LOCK + No lock on SPM and LPM in Application Section + 3 + + + + + BLB1 + Boot Loader Protection Mode + [5:4] + + true + + + + LPM_SPM_DISABLE + LPM and SPM prohibited in Boot Section + 0 + + + LPM_DISABLE + LPM prohibited in Boot Section + 1 + + + SPM_DISABLE + SPM prohibited in Boot Section + 2 + + + NO_LOCK + No lock on SPM and LPM in Boot Section + 3 + + + + + + + + + PORTA + I/O Port + 0x20 + + + DDRA + Port A Data Direction Register + 0x1 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + PINA + Port A Input Pins + 0x0 + read-write + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + PORTA + Port A Data Register + 0x2 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + + + PORTB + I/O Port + 0x23 + + + DDRB + Port B Data Direction Register + 0x1 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PINB + Port B Input Pins + 0x0 + read-write + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PORTB + Port B Data Register + 0x2 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + + + PORTC + I/O Port + 0x26 + + + DDRC + Port C Data Direction Register + 0x1 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + PINC + Port C Input Pins + 0x0 + read-write + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + PORTC + Port C Data Register + 0x2 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + + + PORTD + I/O Port + 0x29 + + + DDRD + Port D Data Direction Register + 0x1 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PIND + Port D Input Pins + 0x0 + read-write + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PORTD + Port D Data Register + 0x2 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + + + PORTE + I/O Port + 0x2C + + + DDRE + Data Direction Register, Port E + 0x1 + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + PE4 + Pin E4 + [4:4] + + + PE5 + Pin E5 + [5:5] + + + PE6 + Pin E6 + [6:6] + + + PE7 + Pin E7 + [7:7] + + + + + PINE + Input Pins, Port E + 0x0 + read-write + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + PE4 + Pin E4 + [4:4] + + + PE5 + Pin E5 + [5:5] + + + PE6 + Pin E6 + [6:6] + + + PE7 + Pin E7 + [7:7] + + + + + PORTE + Data Register, Port E + 0x2 + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + PE4 + Pin E4 + [4:4] + + + PE5 + Pin E5 + [5:5] + + + PE6 + Pin E6 + [6:6] + + + PE7 + Pin E7 + [7:7] + + + + + + + PORTF + I/O Port + 0x2F + + + DDRF + Data Direction Register, Port F + 0x1 + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF2 + Pin F2 + [2:2] + + + PF3 + Pin F3 + [3:3] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + PF7 + Pin F7 + [7:7] + + + + + PINF + Input Pins, Port F + 0x0 + read-write + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF2 + Pin F2 + [2:2] + + + PF3 + Pin F3 + [3:3] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + PF7 + Pin F7 + [7:7] + + + + + PORTF + Data Register, Port F + 0x2 + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF2 + Pin F2 + [2:2] + + + PF3 + Pin F3 + [3:3] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + PF7 + Pin F7 + [7:7] + + + + + + + PORTG + I/O Port + 0x32 + + + DDRG + Data Direction Register, Port G + 0x1 + + + PG0 + Pin G0 + [0:0] + + + PG1 + Pin G1 + [1:1] + + + PG2 + Pin G2 + [2:2] + + + PG3 + Pin G3 + [3:3] + + + PG4 + Pin G4 + [4:4] + + + PG5 + Pin G5 + [5:5] + + + PG6 + Pin G6 + [6:6] + + + PG7 + Pin G7 + [7:7] + + + + + PING + Input Pins, Port G + 0x0 + read-write + + PG0 + Pin G0 + [0:0] + + + PG1 + Pin G1 + [1:1] + + + PG2 + Pin G2 + [2:2] + + + PG3 + Pin G3 + [3:3] + + + PG4 + Pin G4 + [4:4] + + + PG5 + Pin G5 + [5:5] + + + PG6 + Pin G6 + [6:6] + + + PG7 + Pin G7 + [7:7] + + + + + PORTG + Data Register, Port G + 0x2 + + + PG0 + Pin G0 + [0:0] + + + PG1 + Pin G1 + [1:1] + + + PG2 + Pin G2 + [2:2] + + + PG3 + Pin G3 + [3:3] + + + PG4 + Pin G4 + [4:4] + + + PG5 + Pin G5 + [5:5] + + + PG6 + Pin G6 + [6:6] + + + PG7 + Pin G7 + [7:7] + + + + + + + PORTH + I/O Port + 0x100 + + + DDRH + PORT H Data Direction Register + 0x1 + + + PH0 + Pin H0 + [0:0] + + + PH1 + Pin H1 + [1:1] + + + PH2 + Pin H2 + [2:2] + + + PH3 + Pin H3 + [3:3] + + + PH4 + Pin H4 + [4:4] + + + PH5 + Pin H5 + [5:5] + + + PH6 + Pin H6 + [6:6] + + + PH7 + Pin H7 + [7:7] + + + + + PINH + PORT H Input Pins + 0x0 + read-write + + PH0 + Pin H0 + [0:0] + + + PH1 + Pin H1 + [1:1] + + + PH2 + Pin H2 + [2:2] + + + PH3 + Pin H3 + [3:3] + + + PH4 + Pin H4 + [4:4] + + + PH5 + Pin H5 + [5:5] + + + PH6 + Pin H6 + [6:6] + + + PH7 + Pin H7 + [7:7] + + + + + PORTH + PORT H Data Register + 0x2 + + + PH0 + Pin H0 + [0:0] + + + PH1 + Pin H1 + [1:1] + + + PH2 + Pin H2 + [2:2] + + + PH3 + Pin H3 + [3:3] + + + PH4 + Pin H4 + [4:4] + + + PH5 + Pin H5 + [5:5] + + + PH6 + Pin H6 + [6:6] + + + PH7 + Pin H7 + [7:7] + + + + + + + PORTJ + I/O Port + 0x103 + + + DDRJ + PORT J Data Direction Register + 0x1 + + + PJ0 + Pin J0 + [0:0] + + + PJ1 + Pin J1 + [1:1] + + + PJ2 + Pin J2 + [2:2] + + + PJ3 + Pin J3 + [3:3] + + + PJ4 + Pin J4 + [4:4] + + + PJ5 + Pin J5 + [5:5] + + + PJ6 + Pin J6 + [6:6] + + + PJ7 + Pin J7 + [7:7] + + + + + PINJ + PORT J Input Pins + 0x0 + read-write + + PJ0 + Pin J0 + [0:0] + + + PJ1 + Pin J1 + [1:1] + + + PJ2 + Pin J2 + [2:2] + + + PJ3 + Pin J3 + [3:3] + + + PJ4 + Pin J4 + [4:4] + + + PJ5 + Pin J5 + [5:5] + + + PJ6 + Pin J6 + [6:6] + + + PJ7 + Pin J7 + [7:7] + + + + + PORTJ + PORT J Data Register + 0x2 + + + PJ0 + Pin J0 + [0:0] + + + PJ1 + Pin J1 + [1:1] + + + PJ2 + Pin J2 + [2:2] + + + PJ3 + Pin J3 + [3:3] + + + PJ4 + Pin J4 + [4:4] + + + PJ5 + Pin J5 + [5:5] + + + PJ6 + Pin J6 + [6:6] + + + PJ7 + Pin J7 + [7:7] + + + + + + + PORTK + I/O Port + 0x106 + + + DDRK + PORT K Data Direction Register + 0x1 + + + PK0 + Pin K0 + [0:0] + + + PK1 + Pin K1 + [1:1] + + + PK2 + Pin K2 + [2:2] + + + PK3 + Pin K3 + [3:3] + + + PK4 + Pin K4 + [4:4] + + + PK5 + Pin K5 + [5:5] + + + PK6 + Pin K6 + [6:6] + + + PK7 + Pin K7 + [7:7] + + + + + PINK + PORT K Input Pins + 0x0 + read-write + + PK0 + Pin K0 + [0:0] + + + PK1 + Pin K1 + [1:1] + + + PK2 + Pin K2 + [2:2] + + + PK3 + Pin K3 + [3:3] + + + PK4 + Pin K4 + [4:4] + + + PK5 + Pin K5 + [5:5] + + + PK6 + Pin K6 + [6:6] + + + PK7 + Pin K7 + [7:7] + + + + + PORTK + PORT K Data Register + 0x2 + + + PK0 + Pin K0 + [0:0] + + + PK1 + Pin K1 + [1:1] + + + PK2 + Pin K2 + [2:2] + + + PK3 + Pin K3 + [3:3] + + + PK4 + Pin K4 + [4:4] + + + PK5 + Pin K5 + [5:5] + + + PK6 + Pin K6 + [6:6] + + + PK7 + Pin K7 + [7:7] + + + + + + + PORTL + I/O Port + 0x109 + + + DDRL + PORT L Data Direction Register + 0x1 + + + PL0 + Pin L0 + [0:0] + + + PL1 + Pin L1 + [1:1] + + + PL2 + Pin L2 + [2:2] + + + PL3 + Pin L3 + [3:3] + + + PL4 + Pin L4 + [4:4] + + + PL5 + Pin L5 + [5:5] + + + PL6 + Pin L6 + [6:6] + + + PL7 + Pin L7 + [7:7] + + + + + PINL + PORT L Input Pins + 0x0 + read-write + + PL0 + Pin L0 + [0:0] + + + PL1 + Pin L1 + [1:1] + + + PL2 + Pin L2 + [2:2] + + + PL3 + Pin L3 + [3:3] + + + PL4 + Pin L4 + [4:4] + + + PL5 + Pin L5 + [5:5] + + + PL6 + Pin L6 + [6:6] + + + PL7 + Pin L7 + [7:7] + + + + + PORTL + PORT L Data Register + 0x2 + + + PL0 + Pin L0 + [0:0] + + + PL1 + Pin L1 + [1:1] + + + PL2 + Pin L2 + [2:2] + + + PL3 + Pin L3 + [3:3] + + + PL4 + Pin L4 + [4:4] + + + PL5 + Pin L5 + [5:5] + + + PL6 + Pin L6 + [6:6] + + + PL7 + Pin L7 + [7:7] + + + + + + + SPI + Serial Peripheral Interface + 0x4C + + + SPCR + SPI Control Register + 0x0 + + + SPR + SPI Clock Rate Selects + [1:0] + + true + + SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 + + + CPHA + Clock Phase + [2:2] + + + CPOL + Clock polarity + [3:3] + + + MSTR + Master/Slave Select + [4:4] + + + DORD + Data Order + [5:5] + + + SPE + SPI Enable + [6:6] + + + SPIE + SPI Interrupt Enable + [7:7] + + + + + SPDR + SPI Data Register + 0x2 + + + 0 + 255 + + + + + SPSR + SPI Status Register + 0x1 + read-write + + + SPI2X + Double SPI Speed Bit + [0:0] + read-write + + WCOL + Write Collision Flag + [6:6] + read-only + + SPIF + SPI Interrupt Flag + [7:7] + read-only + + + + + + TC0 + Timer/Counter, 8-bit + 0x35 + + + GTCCR + General Timer/Counter Control Register + 0xE + + + PSRSYNC + Prescaler Reset Timer/Counter1 and Timer/Counter0 + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + OCR0A + Timer/Counter0 Output Compare Register + 0x12 + + + 0 + 255 + + + + + OCR0B + Timer/Counter0 Output Compare Register + 0x13 + + + 0 + 255 + + + + + TCCR0A + Timer/Counter Control Register A + 0xF + + + WGM0 + Waveform Generation Mode + [1:0] + + + 0 + 3 + + + + + COM0B + Compare Output Mode, Fast PWm + [5:4] + + + 0 + 3 + + + + + COM0A + Compare Output Mode, Phase Correct PWM Mode + [7:6] + + + 0 + 3 + + + + + + + TCCR0B + Timer/Counter Control Register B + 0x10 + + + CS0 + Clock Select + [2:0] + + true + + + + VAL_0x00 + No Clock Source (Stopped) + 0 + + + VAL_0x01 + Running, No Prescaling + 1 + + + VAL_0x02 + Running, CLK/8 + 2 + + + VAL_0x03 + Running, CLK/64 + 3 + + + VAL_0x04 + Running, CLK/256 + 4 + + + VAL_0x05 + Running, CLK/1024 + 5 + + + VAL_0x06 + Running, ExtClk Tx Falling Edge + 6 + + + VAL_0x07 + Running, ExtClk Tx Rising Edge + 7 + + + + + WGM02 + <TBD> + [3:3] + + + FOC0B + Force Output Compare B + [6:6] + + + FOC0A + Force Output Compare A + [7:7] + + + + + TCNT0 + Timer/Counter0 + 0x11 + + + 0 + 255 + + + + + TIFR0 + Timer/Counter0 Interrupt Flag register + 0x0 + read-only + + + TOV0 + Timer/Counter0 Overflow Flag + [0:0] + + + OCF0A + Timer/Counter0 Output Compare Flag 0A + [1:1] + + + OCF0B + Timer/Counter0 Output Compare Flag 0B + [2:2] + + + + + TIMSK0 + Timer/Counter0 Interrupt Mask Register + 0x39 + + + TOIE0 + Timer/Counter0 Overflow Interrupt Enable + [0:0] + + + OCIE0A + Timer/Counter0 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE0B + Timer/Counter0 Output Compare Match B Interrupt Enable + [2:2] + + + + + + + TC1 + Timer/Counter, 16-bit + 0x36 + + + ICR1 + Timer/Counter1 Input Capture Register Bytes + 0x50 + 16 + + + 0 + 65535 + + + + + OCR1A + Timer/Counter1 Output Compare Register A Bytes + 0x52 + 16 + + + 0 + 65535 + + + + + OCR1B + Timer/Counter1 Output Compare Register B Bytes + 0x54 + 16 + + + 0 + 65535 + + + + + OCR1C + Timer/Counter1 Output Compare Register C Bytes + 0x56 + 16 + + + 0 + 65535 + + + + + TCCR1A + Timer/Counter1 Control Register A + 0x4A + + + WGM1 + Waveform Generation Mode + [1:0] + + + 0 + 3 + + + + + COM1C + Compare Output Mode 1C, bits + [3:2] + + + 0 + 3 + + + + + COM1B + Compare Output Mode 1B, bits + [5:4] + + + 0 + 3 + + + + + COM1A + Compare Output Mode 1A, bits + [7:6] + + + 0 + 3 + + + + + + + TCCR1B + Timer/Counter1 Control Register B + 0x4B + + + CS1 + Prescaler source of Timer/Counter 1 + [2:0] + + true + + + + VAL_0x00 + No Clock Source (Stopped) + 0 + + + VAL_0x01 + Running, No Prescaling + 1 + + + VAL_0x02 + Running, CLK/8 + 2 + + + VAL_0x03 + Running, CLK/64 + 3 + + + VAL_0x04 + Running, CLK/256 + 4 + + + VAL_0x05 + Running, CLK/1024 + 5 + + + VAL_0x06 + Running, ExtClk Tx Falling Edge + 6 + + + VAL_0x07 + Running, ExtClk Tx Rising Edge + 7 + + + + + WGM1 + Waveform Generation Mode + [4:3] + + + 0 + 3 + + + + + ICES1 + Input Capture 1 Edge Select + [6:6] + + + ICNC1 + Input Capture 1 Noise Canceler + [7:7] + + + + + TCCR1C + Timer/Counter 1 Control Register C + 0x4C + + + FOC1C + Force Output Compare 1C + [5:5] + + + FOC1B + Force Output Compare 1B + [6:6] + + + FOC1A + Force Output Compare 1A + [7:7] + + + + + TCNT1 + Timer/Counter1 Bytes + 0x4E + 16 + + + 0 + 65535 + + + + + TIFR1 + Timer/Counter1 Interrupt Flag register + 0x0 + read-only + + + TOV1 + Timer/Counter1 Overflow Flag + [0:0] + + + OCF1A + Output Compare Flag 1A + [1:1] + + + OCF1B + Output Compare Flag 1B + [2:2] + + + OCF1C + Output Compare Flag 1C + [3:3] + + + ICF1 + Input Capture Flag 1 + [5:5] + + + + + TIMSK1 + Timer/Counter1 Interrupt Mask Register + 0x39 + + + TOIE1 + Timer/Counter1 Overflow Interrupt Enable + [0:0] + + + OCIE1A + Timer/Counter1 Output Compare A Match Interrupt Enable + [1:1] + + + OCIE1B + Timer/Counter1 Output Compare B Match Interrupt Enable + [2:2] + + + OCIE1C + Timer/Counter1 Output Compare C Match Interrupt Enable + [3:3] + + + ICIE1 + Timer/Counter1 Input Capture Interrupt Enable + [5:5] + + + + + + + TC2 + Timer/Counter, 8-bit Async + 0x37 + + + ASSR + Asynchronous Status Register + 0x7F + + + TCR2BUB + Timer/Counter Control Register2 Update Busy + [0:0] + + + TCR2AUB + Timer/Counter Control Register2 Update Busy + [1:1] + + + OCR2BUB + Output Compare Register 2 Update Busy + [2:2] + + + OCR2AUB + Output Compare Register2 Update Busy + [3:3] + + + TCN2UB + Timer/Counter2 Update Busy + [4:4] + + + AS2 + Asynchronous Timer/Counter2 + [5:5] + + + EXCLK + Enable External Clock Input + [6:6] + + + + + GTCCR + General Timer Counter Control register + 0xC + + + PSRASY + Prescaler Reset Timer/Counter2 + [1:1] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + OCR2A + Timer/Counter2 Output Compare Register A + 0x7C + + + 0 + 255 + + + + + OCR2B + Timer/Counter2 Output Compare Register B + 0x7D + + + 0 + 255 + + + + + TCCR2A + Timer/Counter2 Control Register A + 0x79 + + + WGM2 + Waveform Genration Mode + [1:0] + + + 0 + 3 + + + + + COM2B + Compare Output Mode bits + [5:4] + + + 0 + 3 + + + + + COM2A + Compare Output Mode bits + [7:6] + + + 0 + 3 + + + + + + + TCCR2B + Timer/Counter2 Control Register B + 0x7A + + + CS2 + Clock Select bits + [2:0] + + true + + + + VAL_0x00 + No Clock Source (Stopped) + 0 + + + VAL_0x01 + Running, No Prescaling + 1 + + + VAL_0x02 + Running, CLK/8 + 2 + + + VAL_0x03 + Running, CLK/32 + 3 + + + VAL_0x04 + Running, CLK/64 + 4 + + + VAL_0x05 + Running, CLK/128 + 5 + + + VAL_0x06 + Running, CLK/256 + 6 + + + VAL_0x07 + Running, CLK/1024 + 7 + + + + + WGM22 + Waveform Generation Mode + [3:3] + + + FOC2B + Force Output Compare B + [6:6] + + + FOC2A + Force Output Compare A + [7:7] + + + + + TCNT2 + Timer/Counter2 + 0x7B + + + 0 + 255 + + + + + TIFR2 + Timer/Counter Interrupt Flag Register + 0x0 + read-only + + + TOV2 + Timer/Counter2 Overflow Flag + [0:0] + + + OCF2A + Output Compare Flag 2A + [1:1] + + + OCF2B + Output Compare Flag 2B + [2:2] + + + + + TIMSK2 + Timer/Counter Interrupt Mask register + 0x39 + + + TOIE2 + Timer/Counter2 Overflow Interrupt Enable + [0:0] + + + OCIE2A + Timer/Counter2 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE2B + Timer/Counter2 Output Compare Match B Interrupt Enable + [2:2] + + + + + + + TC3 + Timer/Counter, 16-bit + 0x38 + + + ICR3 + Timer/Counter3 Input Capture Register Bytes + 0x5E + 16 + + + 0 + 65535 + + + + + OCR3A + Timer/Counter3 Output Compare Register A Bytes + 0x60 + 16 + + + 0 + 65535 + + + + + OCR3B + Timer/Counter3 Output Compare Register B Bytes + 0x62 + 16 + + + 0 + 65535 + + + + + OCR3C + Timer/Counter3 Output Compare Register B Bytes + 0x64 + 16 + + + 0 + 65535 + + + + + TCCR3A + Timer/Counter3 Control Register A + 0x58 + + + WGM3 + Waveform Generation Mode + [1:0] + + + 0 + 3 + + + + + COM3C + Compare Output Mode 3C, bits + [3:2] + + + 0 + 3 + + + + + COM3B + Compare Output Mode 3B, bits + [5:4] + + + 0 + 3 + + + + + COM3A + Compare Output Mode 1A, bits + [7:6] + + + 0 + 3 + + + + + + + TCCR3B + Timer/Counter3 Control Register B + 0x59 + + + CS3 + Prescaler source of Timer/Counter 3 + [2:0] + + true + + + + VAL_0x00 + No Clock Source (Stopped) + 0 + + + VAL_0x01 + Running, No Prescaling + 1 + + + VAL_0x02 + Running, CLK/8 + 2 + + + VAL_0x03 + Running, CLK/64 + 3 + + + VAL_0x04 + Running, CLK/256 + 4 + + + VAL_0x05 + Running, CLK/1024 + 5 + + + VAL_0x06 + Running, ExtClk Tx Falling Edge + 6 + + + VAL_0x07 + Running, ExtClk Tx Rising Edge + 7 + + + + + WGM3 + Waveform Generation Mode + [4:3] + + + 0 + 3 + + + + + ICES3 + Input Capture 3 Edge Select + [6:6] + + + ICNC3 + Input Capture 3 Noise Canceler + [7:7] + + + + + TCCR3C + Timer/Counter 3 Control Register C + 0x5A + + + FOC3C + Force Output Compare 3C + [5:5] + + + FOC3B + Force Output Compare 3B + [6:6] + + + FOC3A + Force Output Compare 3A + [7:7] + + + + + TCNT3 + Timer/Counter3 Bytes + 0x5C + 16 + + + 0 + 65535 + + + + + TIFR3 + Timer/Counter3 Interrupt Flag register + 0x0 + read-only + + + TOV3 + Timer/Counter3 Overflow Flag + [0:0] + + + OCF3A + Output Compare Flag 3A + [1:1] + + + OCF3B + Output Compare Flag 3B + [2:2] + + + OCF3C + Output Compare Flag 3C + [3:3] + + + ICF3 + Input Capture Flag 3 + [5:5] + + + + + TIMSK3 + Timer/Counter3 Interrupt Mask Register + 0x39 + + + TOIE3 + Timer/Counter3 Overflow Interrupt Enable + [0:0] + + + OCIE3A + Timer/Counter3 Output Compare A Match Interrupt Enable + [1:1] + + + OCIE3B + Timer/Counter3 Output Compare B Match Interrupt Enable + [2:2] + + + OCIE3C + Timer/Counter3 Output Compare C Match Interrupt Enable + [3:3] + + + ICIE3 + Timer/Counter3 Input Capture Interrupt Enable + [5:5] + + + + + + + TC4 + Timer/Counter, 16-bit + 0x39 + + + ICR4 + Timer/Counter4 Input Capture Register Bytes + 0x6D + 16 + + + 0 + 65535 + + + + + OCR4A + Timer/Counter4 Output Compare Register A Bytes + 0x6F + 16 + + + 0 + 65535 + + + + + OCR4B + Timer/Counter4 Output Compare Register B Bytes + 0x71 + 16 + + + 0 + 65535 + + + + + OCR4C + Timer/Counter4 Output Compare Register B Bytes + 0x73 + 16 + + + 0 + 65535 + + + + + TCCR4A + Timer/Counter4 Control Register A + 0x67 + + + WGM4 + Waveform Generation Mode + [1:0] + + + 0 + 3 + + + + + COM4C + Compare Output Mode 4C, bits + [3:2] + + + 0 + 3 + + + + + COM4B + Compare Output Mode 4B, bits + [5:4] + + + 0 + 3 + + + + + COM4A + Compare Output Mode 1A, bits + [7:6] + + + 0 + 3 + + + + + + + TCCR4B + Timer/Counter4 Control Register B + 0x68 + + + CS4 + Prescaler source of Timer/Counter 4 + [2:0] + + true + + + + VAL_0x00 + No Clock Source (Stopped) + 0 + + + VAL_0x01 + Running, No Prescaling + 1 + + + VAL_0x02 + Running, CLK/8 + 2 + + + VAL_0x03 + Running, CLK/64 + 3 + + + VAL_0x04 + Running, CLK/256 + 4 + + + VAL_0x05 + Running, CLK/1024 + 5 + + + VAL_0x06 + Running, ExtClk Tx Falling Edge + 6 + + + VAL_0x07 + Running, ExtClk Tx Rising Edge + 7 + + + + + WGM4 + Waveform Generation Mode + [4:3] + + + 0 + 3 + + + + + ICES4 + Input Capture 4 Edge Select + [6:6] + + + ICNC4 + Input Capture 4 Noise Canceler + [7:7] + + + + + TCCR4C + Timer/Counter 4 Control Register C + 0x69 + + + FOC4C + Force Output Compare 4C + [5:5] + + + FOC4B + Force Output Compare 4B + [6:6] + + + FOC4A + Force Output Compare 4A + [7:7] + + + + + TCNT4 + Timer/Counter4 Bytes + 0x6B + 16 + + + 0 + 65535 + + + + + TIFR4 + Timer/Counter4 Interrupt Flag register + 0x0 + + + TOV4 + Timer/Counter4 Overflow Flag + [0:0] + + + OCF4A + Output Compare Flag 4A + [1:1] + + + OCF4B + Output Compare Flag 4B + [2:2] + + + OCF4C + Output Compare Flag 4C + [3:3] + + + ICF4 + Input Capture Flag 4 + [5:5] + + + + + TIMSK4 + Timer/Counter4 Interrupt Mask Register + 0x39 + + + TOIE4 + Timer/Counter4 Overflow Interrupt Enable + [0:0] + + + OCIE4A + Timer/Counter4 Output Compare A Match Interrupt Enable + [1:1] + + + OCIE4B + Timer/Counter4 Output Compare B Match Interrupt Enable + [2:2] + + + OCIE4C + Timer/Counter4 Output Compare C Match Interrupt Enable + [3:3] + + + ICIE4 + Timer/Counter4 Input Capture Interrupt Enable + [5:5] + + + + + + + TC5 + Timer/Counter, 16-bit + 0x3A + + + ICR5 + Timer/Counter5 Input Capture Register Bytes + 0xEC + 16 + + + 0 + 65535 + + + + + OCR5A + Timer/Counter5 Output Compare Register A Bytes + 0xEE + 16 + + + 0 + 65535 + + + + + OCR5B + Timer/Counter5 Output Compare Register B Bytes + 0xF0 + 16 + + + 0 + 65535 + + + + + OCR5C + Timer/Counter5 Output Compare Register B Bytes + 0xF2 + 16 + + + 0 + 65535 + + + + + TCCR5A + Timer/Counter5 Control Register A + 0xE6 + + + WGM5 + Waveform Generation Mode + [1:0] + + + 0 + 3 + + + + + COM5C + Compare Output Mode 5C, bits + [3:2] + + + 0 + 3 + + + + + COM5B + Compare Output Mode 5B, bits + [5:4] + + + 0 + 3 + + + + + COM5A + Compare Output Mode 1A, bits + [7:6] + + + 0 + 3 + + + + + + + TCCR5B + Timer/Counter5 Control Register B + 0xE7 + + + CS5 + Prescaler source of Timer/Counter 5 + [2:0] + + true + + + + VAL_0x00 + No Clock Source (Stopped) + 0 + + + VAL_0x01 + Running, No Prescaling + 1 + + + VAL_0x02 + Running, CLK/8 + 2 + + + VAL_0x03 + Running, CLK/64 + 3 + + + VAL_0x04 + Running, CLK/256 + 4 + + + VAL_0x05 + Running, CLK/1024 + 5 + + + VAL_0x06 + Running, ExtClk Tx Falling Edge + 6 + + + VAL_0x07 + Running, ExtClk Tx Rising Edge + 7 + + + + + WGM5 + Waveform Generation Mode + [4:3] + + + 0 + 3 + + + + + ICES5 + Input Capture 5 Edge Select + [6:6] + + + ICNC5 + Input Capture 5 Noise Canceler + [7:7] + + + + + TCCR5C + Timer/Counter 5 Control Register C + 0xE8 + + + FOC5C + Force Output Compare 5C + [5:5] + + + FOC5B + Force Output Compare 5B + [6:6] + + + FOC5A + Force Output Compare 5A + [7:7] + + + + + TCNT5 + Timer/Counter5 Bytes + 0xEA + 16 + + + 0 + 65535 + + + + + TIFR5 + Timer/Counter5 Interrupt Flag register + 0x0 + + + TOV5 + Timer/Counter5 Overflow Flag + [0:0] + + + OCF5A + Output Compare Flag 5A + [1:1] + + + OCF5B + Output Compare Flag 5B + [2:2] + + + OCF5C + Output Compare Flag 5C + [3:3] + + + ICF5 + Input Capture Flag 5 + [5:5] + + + + + TIMSK5 + Timer/Counter5 Interrupt Mask Register + 0x39 + + + TOIE5 + Timer/Counter5 Overflow Interrupt Enable + [0:0] + + + OCIE5A + Timer/Counter5 Output Compare A Match Interrupt Enable + [1:1] + + + OCIE5B + Timer/Counter5 Output Compare B Match Interrupt Enable + [2:2] + + + OCIE5C + Timer/Counter5 Output Compare C Match Interrupt Enable + [3:3] + + + ICIE5 + Timer/Counter5 Input Capture Interrupt Enable + [5:5] + + + + + + + TWI + Two Wire Serial Interface + 0xB8 + + + TWAMR + TWI (Slave) Address Mask Register + 0x5 + + + TWAM + TWI (Slave) Address Mask Bits + [7:1] + + + 0 + 127 + + + + + + + TWAR + TWI (Slave) Address register + 0x2 + + + TWGCE + TWI General Call Recognition Enable Bit + [0:0] + + + TWA + TWI (Slave) Address register Bits + [7:1] + + + 0 + 127 + + + + + + + TWBR + TWI Bit Rate register + 0x0 + + + 0 + 255 + + + + + TWCR + TWI Control Register + 0x4 + read-write + + + TWIE + TWI Interrupt Enable + [0:0] + + + TWEN + TWI Enable Bit + [2:2] + + + TWWC + TWI Write Collition Flag + [3:3] + read-only + + TWSTO + TWI Stop Condition Bit + [4:4] + + + TWSTA + TWI Start Condition Bit + [5:5] + + + TWEA + TWI Enable Acknowledge Bit + [6:6] + + + TWINT + TWI Interrupt Flag + [7:7] + + + + + TWDR + TWI Data register + 0x3 + + + 0 + 255 + + + + + TWSR + TWI Status Register + 0x1 + + + TWPS + TWI Prescaler + [1:0] + + true + + TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 + + + TWS + TWI Status + [7:3] + read-only + + 0 + 31 + + + + + + + + + USART0 + USART + 0xC0 + + + UBRR0 + USART Baud Rate Register Bytes + 0x4 + 16 + + + 0 + 65535 + + + + + UCSR0A + USART Control and Status Register A + 0x0 + read-write + + + MPCM0 + Multi-processor Communication Mode + [0:0] + + + U2X0 + Double the USART transmission speed + [1:1] + + + UPE0 + Parity Error + [2:2] + read-only + + DOR0 + Data overRun + [3:3] + read-only + + FE0 + Framing Error + [4:4] + read-only + + UDRE0 + USART Data Register Empty + [5:5] + read-only + + TXC0 + USART Transmit Complete + [6:6] + + + RXC0 + USART Receive Complete + [7:7] + read-only + + + + UCSR0B + USART Control and Status Register B + 0x1 + + + TXB80 + Transmit Data Bit 8 + [0:0] + + + RXB80 + Receive Data Bit 8 + [1:1] + read-only + + UCSZ02 + Character Size + [2:2] + + + TXEN0 + Transmitter Enable + [3:3] + + + RXEN0 + Receiver Enable + [4:4] + + + UDRIE0 + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE0 + TX Complete Interrupt Enable + [6:6] + + + RXCIE0 + RX Complete Interrupt Enable + [7:7] + + + + + UCSR0C + USART Control and Status Register C + 0x2 + + + UCPOL0 + Clock Polarity + [0:0] + UCPOL0read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 + + + UCSZ0 + Character Size + [2:1] + + + 0 + 3 + + + UCSZ0read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 + + + USBS0 + Stop Bit Select + [3:3] + + true + + USBS0read-writeSTOP11-bit0STOP22-bit1 + + + UPM0 + Parity Mode Bits + [5:4] + + true + + UPM0read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 + + + UMSEL0 + USART Mode Select + [7:6] + + true + + UMSEL0read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 + + + + + UDR0 + USART I/O Data Register + 0x6 + + + 0 + 255 + + + + + + + USART1 + USART + 0xC8 + + + UBRR1 + USART Baud Rate Register Bytes + 0x4 + 16 + + + 0 + 65535 + + + + + UCSR1A + USART Control and Status Register A + 0x0 + read-write + + + MPCM1 + Multi-processor Communication Mode + [0:0] + + + U2X1 + Double the USART transmission speed + [1:1] + + + UPE1 + Parity Error + [2:2] + read-only + + DOR1 + Data overRun + [3:3] + read-only + + FE1 + Framing Error + [4:4] + read-only + + UDRE1 + USART Data Register Empty + [5:5] + read-only + + TXC1 + USART Transmit Complete + [6:6] + + + RXC1 + USART Receive Complete + [7:7] + read-only + + + + UCSR1B + USART Control and Status Register B + 0x1 + + + TXB81 + Transmit Data Bit 8 + [0:0] + + + RXB81 + Receive Data Bit 8 + [1:1] + read-only + + UCSZ12 + Character Size + [2:2] + + + TXEN1 + Transmitter Enable + [3:3] + + + RXEN1 + Receiver Enable + [4:4] + + + UDRIE1 + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE1 + TX Complete Interrupt Enable + [6:6] + + + RXCIE1 + RX Complete Interrupt Enable + [7:7] + + + + + UCSR1C + USART Control and Status Register C + 0x2 + + + UCPOL1 + Clock Polarity + [0:0] + UCPOL1read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 + + + UCSZ1 + Character Size + [2:1] + + + 0 + 3 + + + UCSZ1read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 + + + USBS1 + Stop Bit Select + [3:3] + + true + + USBS1read-writeSTOP11-bit0STOP22-bit1 + + + UPM1 + Parity Mode Bits + [5:4] + + true + + UPM1read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 + + + UMSEL1 + USART Mode Select + [7:6] + + true + + UMSEL1read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 + + + + + UDR1 + USART I/O Data Register + 0x6 + + + 0 + 255 + + + + + + + USART2 + USART + 0xD0 + + + UBRR2 + USART Baud Rate Register Bytes + 0x4 + 16 + + + 0 + 65535 + + + + + UCSR2A + USART Control and Status Register A + 0x0 + read-write + + + MPCM2 + Multi-processor Communication Mode + [0:0] + + + U2X2 + Double the USART transmission speed + [1:1] + + + UPE2 + Parity Error + [2:2] + read-only + + DOR2 + Data overRun + [3:3] + read-only + + FE2 + Framing Error + [4:4] + read-only + + UDRE2 + USART Data Register Empty + [5:5] + read-only + + TXC2 + USART Transmit Complete + [6:6] + + + RXC2 + USART Receive Complete + [7:7] + read-only + + + + UCSR2B + USART Control and Status Register B + 0x1 + + + TXB82 + Transmit Data Bit 8 + [0:0] + + + RXB82 + Receive Data Bit 8 + [1:1] + read-only + + UCSZ22 + Character Size + [2:2] + + + TXEN2 + Transmitter Enable + [3:3] + + + RXEN2 + Receiver Enable + [4:4] + + + UDRIE2 + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE2 + TX Complete Interrupt Enable + [6:6] + + + RXCIE2 + RX Complete Interrupt Enable + [7:7] + + + + + UCSR2C + USART Control and Status Register C + 0x2 + + + UCPOL2 + Clock Polarity + [0:0] + UCPOL2read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 + + + UCSZ2 + Character Size + [2:1] + + + 0 + 3 + + + UCSZ2read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 + + + USBS2 + Stop Bit Select + [3:3] + + true + + USBS2read-writeSTOP11-bit0STOP22-bit1 + + + UPM2 + Parity Mode Bits + [5:4] + + true + + UPM2read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 + + + UMSEL2 + USART Mode Select + [7:6] + + true + + UMSEL2read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 + + + + + UDR2 + USART I/O Data Register + 0x6 + + + 0 + 255 + + + + + + + USART3 + USART + 0x130 + + + UBRR3 + USART Baud Rate Register Bytes + 0x4 + 16 + + + 0 + 65535 + + + + + UCSR3A + USART Control and Status Register A + 0x0 + read-write + + + MPCM3 + Multi-processor Communication Mode + [0:0] + + + U2X3 + Double the USART transmission speed + [1:1] + + + UPE3 + Parity Error + [2:2] + read-only + + DOR3 + Data overRun + [3:3] + read-only + + FE3 + Framing Error + [4:4] + read-only + + UDRE3 + USART Data Register Empty + [5:5] + read-only + + TXC3 + USART Transmit Complete + [6:6] + + + RXC3 + USART Receive Complete + [7:7] + read-only + + + + UCSR3B + USART Control and Status Register B + 0x1 + + + TXB83 + Transmit Data Bit 8 + [0:0] + + + RXB83 + Receive Data Bit 8 + [1:1] + read-only + + UCSZ32 + Character Size + [2:2] + + + TXEN3 + Transmitter Enable + [3:3] + + + RXEN3 + Receiver Enable + [4:4] + + + UDRIE3 + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE3 + TX Complete Interrupt Enable + [6:6] + + + RXCIE3 + RX Complete Interrupt Enable + [7:7] + + + + + UCSR3C + USART Control and Status Register C + 0x2 + + + UCPOL3 + Clock Polarity + [0:0] + UCPOL3read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 + + + UCSZ3 + Character Size + [2:1] + + + 0 + 3 + + + UCSZ3read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 + + + USBS3 + Stop Bit Select + [3:3] + + true + + USBS3read-writeSTOP11-bit0STOP22-bit1 + + + UPM3 + Parity Mode Bits + [5:4] + + true + + UPM3read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 + + + UMSEL3 + USART Mode Select + [7:6] + + true + + UMSEL3read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 + + + + + UDR3 + USART I/O Data Register + 0x6 + + + 0 + 255 + + + + + + + WDT + Watchdog Timer + 0x60 + + + WDTCSR + Watchdog Timer Control Register + 0x0 + read-write + + + WDE + Watch Dog Enable + [3:3] + + + WDCE + Watchdog Change Enable + [4:4] + + + WDIE + Watchdog Timeout Interrupt Enable + [6:6] + + + WDIF + Watchdog Timeout Interrupt Flag + [7:7] + + WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 + + WDPHWatchdog Timer Prescaler - High Bit[5:5] + + + + + + \ No newline at end of file diff --git a/misc/svd/atmega168.svd b/misc/svd/atmega168.svd new file mode 100644 index 0000000..d8e32bf --- /dev/null +++ b/misc/svd/atmega168.svd @@ -0,0 +1,3030 @@ + + Atmel + ATmega168 + 8 + 8 + read-write + 0 + 0xff + + + AC + Analog Comparator + 0x50 + + + ACSR + Analog Comparator Control And Status Register + 0x0 + read-write + + + ACIS + Analog Comparator Interrupt Mode Select + [1:0] + + true + + ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 + + + ACIC + Analog Comparator Input Capture Enable + [2:2] + + + ACIE + Analog Comparator Interrupt Enable + [3:3] + + + ACI + Analog Comparator Interrupt Flag + [4:4] + + + ACO + Analog Compare Output + [5:5] + read-only + + ACBG + Analog Comparator Bandgap Select + [6:6] + + + ACD + Analog Comparator Disable + [7:7] + + + + + DIDR1 + Digital Input Disable Register 1 + 0x2F + + + AIN0D + AIN0 Digital Input Disable + [0:0] + + + AIN1D + AIN1 Digital Input Disable + [1:1] + + + + + + + ADC + Analog-to-Digital Converter + 0x78 + + + ADC + ADC Data Register Bytes + 0x0 + 16 + + + 0 + 65535 + + + + + ADCSRA + The ADC Control and Status register A + 0x2 + read-write + + + ADPS + ADC Prescaler Select Bits + [2:0] + + true + + ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 + + + ADIE + ADC Interrupt Enable + [3:3] + + + ADIF + ADC Interrupt Flag + [4:4] + + + ADATE + ADC Auto Trigger Enable + [5:5] + + + ADSC + ADC Start Conversion + [6:6] + + + ADEN + ADC Enable + [7:7] + + + + + ADCSRB + The ADC Control and Status register B + 0x3 + + + ADTS + ADC Auto Trigger Source bits + [2:0] + + true + + + + VAL_0x00 + Free Running mode + 0 + + + VAL_0x01 + Analog Comparator + 1 + + + VAL_0x02 + External Interrupt Request 0 + 2 + + + VAL_0x03 + Timer/Counter0 Compare Match A + 3 + + + VAL_0x04 + Timer/Counter0 Overflow + 4 + + + VAL_0x05 + Timer/Counter1 Compare Match B + 5 + + + VAL_0x06 + Timer/Counter1 Overflow + 6 + + + VAL_0x07 + Timer/Counter1 Capture Event + 7 + + + + + ACME + <TBD> + [6:6] + + + + + ADMUX + The ADC multiplexer Selection Register + 0x4 + + + MUX + Analog Channel Selection Bits + [3:0] + + true + + + + ADC0 + ADC Single Ended Input pin 0 + 0 + + + ADC1 + ADC Single Ended Input pin 1 + 1 + + + ADC2 + ADC Single Ended Input pin 2 + 2 + + + ADC3 + ADC Single Ended Input pin 3 + 3 + + + ADC4 + ADC Single Ended Input pin 4 + 4 + + + ADC5 + ADC Single Ended Input pin 5 + 5 + + + ADC6 + ADC Single Ended Input pin 6 + 6 + + + ADC7 + ADC Single Ended Input pin 7 + 7 + + + ADC_VBG + Internal Reference (VBG) + 14 + + + ADC_GND + 0V (GND) + 15 + + + + + ADLAR + Left Adjust Result + [5:5] + + + REFS + Reference Selection Bits + [7:6] + + true + + REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 + + + + + DIDR0 + Digital Input Disable Register + 0x6 + + + ADC0D + <TBD> + [0:0] + + + ADC1D + <TBD> + [1:1] + + + ADC2D + <TBD> + [2:2] + + + ADC3D + <TBD> + [3:3] + + + ADC4D + <TBD> + [4:4] + + + ADC5D + <TBD> + [5:5] + + + + + + + CPU + CPU Registers + 0x3E + + RESET + External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + 0 + + + INT0 + External Interrupt Request 0 + 1 + + + INT1 + External Interrupt Request 1 + 2 + + + PCINT0 + Pin Change Interrupt Request 0 + 3 + + + PCINT1 + Pin Change Interrupt Request 0 + 4 + + + PCINT2 + Pin Change Interrupt Request 1 + 5 + + + WDT + Watchdog Time-out Interrupt + 6 + + + TIMER2_COMPA + Timer/Counter2 Compare Match A + 7 + + + TIMER2_COMPB + Timer/Counter2 Compare Match A + 8 + + + TIMER2_OVF + Timer/Counter2 Overflow + 9 + + + TIMER1_CAPT + Timer/Counter1 Capture Event + 10 + + + TIMER1_COMPA + Timer/Counter1 Compare Match A + 11 + + + TIMER1_COMPB + Timer/Counter1 Compare Match B + 12 + + + TIMER1_OVF + Timer/Counter1 Overflow + 13 + + + TIMER0_COMPA + TimerCounter0 Compare Match A + 14 + + + TIMER0_COMPB + TimerCounter0 Compare Match B + 15 + + + TIMER0_OVF + Timer/Couner0 Overflow + 16 + + + SPI_STC + SPI Serial Transfer Complete + 17 + + + USART_RX + USART Rx Complete + 18 + + + USART_UDRE + USART, Data Register Empty + 19 + + + USART_TX + USART Tx Complete + 20 + + + ADC + ADC Conversion Complete + 21 + + + EE_READY + EEPROM Ready + 22 + + + ANALOG_COMP + Analog Comparator + 23 + + + TWI + Two-wire Serial Interface + 24 + + + SPM_READY + Store Program Memory Read + 25 + + + + CLKPR + Clock Prescale Register + 0x23 + read-only + + + CLKPS + Clock Prescaler Select Bits + [3:0] + + true + + + + VAL_0x00 + 1 + 0 + + + VAL_0x01 + 2 + 1 + + + VAL_0x02 + 4 + 2 + + + VAL_0x03 + 8 + 3 + + + VAL_0x04 + 16 + 4 + + + VAL_0x05 + 32 + 5 + + + VAL_0x06 + 64 + 6 + + + VAL_0x07 + 128 + 7 + + + VAL_0x08 + 256 + 8 + + + + + CLKPCE + Clock Prescaler Change Enable + [7:7] + + + + + GPIOR0 + General Purpose I/O Register 0 + 0x0 + + + 0 + 255 + + + + + GPIOR1 + General Purpose I/O Register 1 + 0xC + + + 0 + 255 + + + + + GPIOR2 + General Purpose I/O Register 2 + 0xD + + + 0 + 255 + + + + + MCUCR + MCU Control Register + 0x17 + + + IVCE + Interrupt Vector Change Enable + [0:0] + + + IVSEL + Interrupt Vector Select + [1:1] + + + PUD + Pull-up Disable + [4:4] + + + + + MCUSR + MCU Status Register + 0x16 + + + PORF + Power-on reset flag + [0:0] + + + EXTRF + External Reset Flag + [1:1] + + + BORF + Brown-out Reset Flag + [2:2] + + + WDRF + Watchdog Reset Flag + [3:3] + + + + + OSCCAL + Oscillator Calibration Value + 0x28 + read-only + + + OSCCAL + Oscillator Calibration + [7:0] + + + 0 + 255 + + + + + + + PRR + Power Reduction Register + 0x26 + read-only + + + PRADC + Power Reduction ADC + [0:0] + + + PRUSART0 + Power Reduction USART + [1:1] + + + PRSPI + Power Reduction Serial Peripheral Interface + [2:2] + + + PRTIM1 + Power Reduction Timer/Counter1 + [3:3] + + + PRTIM0 + Power Reduction Timer/Counter0 + [5:5] + + + PRTIM2 + Power Reduction Timer/Counter2 + [6:6] + + + PRTWI + Power Reduction TWI + [7:7] + + + + + SMCR + Sleep Mode Control Register + 0x15 + + + SE + Sleep Enable + [0:0] + + + SM + Sleep Mode + [3:1] + + true + + + + IDLE + Idle + 0 + + + ADC + ADC Noise Reduction (If Available) + 1 + + + PDOWN + Power Down + 2 + + + PSAVE + Power Save + 3 + + + VAL_0x04 + Reserved + 4 + + + VAL_0x05 + Reserved + 5 + + + STDBY + Standby + 6 + + + VAL_0x07 + Reserved + 7 + + + + + + + SPMCSR + Store Program Memory Control and Status Register + 0x19 + + + SELFPRGEN + Self Programming Enable + [0:0] + + + PGERS + Page Erase + [1:1] + + + PGWRT + Page Write + [2:2] + + + BLBSET + Boot Lock Bit Set + [3:3] + + + RWWSRE + Read-While-Write section read enable + [4:4] + + + RWWSB + Read-While-Write Section Busy + [6:6] + + + SPMIE + SPM Interrupt Enable + [7:7] + + + + + + + EEPROM + EEPROM + 0x3F + + + EEAR + EEPROM Address Register Bytes + 0x2 + 16 + + + 0 + 65535 + + + + + EECR + EEPROM Control Register + 0x0 + + + EERE + EEPROM Read Enable + [0:0] + + + EEPE + EEPROM Write Enable + [1:1] + + + EEMPE + EEPROM Master Write Enable + [2:2] + + + EERIE + EEPROM Ready Interrupt Enable + [3:3] + + + EEPM + EEPROM Programming Mode Bits + [5:4] + + true + + + + VAL_0x00 + Erase and Write in one operation + 0 + + + VAL_0x01 + Erase Only + 1 + + + VAL_0x02 + Write Only + 2 + + + + + + + EEDR + EEPROM Data Register + 0x1 + + + 0 + 255 + + + + + + + EXINT + External Interrupts + 0x3B + + + EICRA + External Interrupt Control Register + 0x2E + + + ISC0 + External Interrupt Sense Control 0 Bits + [1:0] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC1 + External Interrupt Sense Control 1 Bits + [3:2] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + + + EIFR + External Interrupt Flag Register + 0x1 + read-only + + + INTF + External Interrupt Flags + [1:0] + + + 0 + 3 + + + + + + + EIMSK + External Interrupt Mask Register + 0x2 + + + INT + External Interrupt Request 1 Enable + [1:0] + + + 0 + 3 + + + + + + + PCICR + Pin Change Interrupt Control Register + 0x2D + + + PCIE + Pin Change Interrupt Enables + [2:0] + + + 0 + 7 + + + + + + + PCIFR + Pin Change Interrupt Flag Register + 0x0 + read-only + + + PCIF + Pin Change Interrupt Flags + [2:0] + + + 0 + 7 + + + + + + + PCMSK0 + Pin Change Mask Register 0 + 0x30 + + + PCINT + Pin Change Enable Masks + [7:0] + + + 0 + 255 + + + + + + + PCMSK1 + Pin Change Mask Register 1 + 0x31 + + + PCINT + Pin Change Enable Masks + [6:0] + + + 0 + 127 + + + + + + + PCMSK2 + Pin Change Mask Register 2 + 0x32 + + + PCINT + Pin Change Enable Masks + [7:0] + + + 0 + 255 + + + + + + + + + FUSE + Fuses + 0x0 + + + EXTENDED + <TBD> + 0x2 + + + BOOTRST + Boot Reset vector Enabled + [0:0] + + + BOOTSZ + Select boot size + [2:1] + + true + + + + 1024W_1C00 + Boot Flash size=1024 words start address=$1C00 + 0 + + + 512W_1E00 + Boot Flash size=512 words start address=$1E00 + 1 + + + 256W_1F00 + Boot Flash size=256 words start address=$1F00 + 2 + + + 128W_1F80 + Boot Flash size=128 words start address=$1F80 + 3 + + + + + + + HIGH + <TBD> + 0x1 + + + BODLEVEL + Brown-out Detector trigger level + [2:0] + + true + + + + 4V3 + Brown-out detection at VCC=4.3 V + 4 + + + 2V7 + Brown-out detection at VCC=2.7 V + 5 + + + 1V8 + Brown-out detection at VCC=1.8 V + 6 + + + DISABLED + Brown-out detection disabled + 7 + + + + + EESAVE + Preserve EEPROM through the Chip Erase cycle + [3:3] + + + WDTON + Watch-dog Timer always on + [4:4] + + + SPIEN + Serial program downloading (SPI) enabled + [5:5] + + + DWEN + Debug Wire enable + [6:6] + + + RSTDISBL + Reset Disabled (Enable PC6 as i/o pin) + [7:7] + + + + + LOW + <TBD> + 0x0 + + + SUT_CKSEL + Select Clock Source + [5:0] + + true + + + + EXTCLK_6CK_14CK_0MS + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 0 + + + INTRCOSC_8MHZ_6CK_14CK_0MS + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 2 + + + INTRCOSC_128KHZ_6CK_14CK_0MS + Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 3 + + + EXTLOFXTAL_1KCK_14CK_0MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms + 4 + + + EXTLOFXTAL_32KCK_14CK_0MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms + 5 + + + EXTFSXTAL_258CK_14CK_4MS1 + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 6 + + + EXTFSXTAL_1KCK_14CK_65MS + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 7 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 8 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 9 + + + EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 10 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 11 + + + EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 12 + + + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 13 + + + EXTXOSC_8MHZ_XX_258CK_14CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 14 + + + EXTXOSC_8MHZ_XX_1KCK_14CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 15 + + + EXTCLK_6CK_14CK_4MS1 + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + 16 + + + INTRCOSC_8MHZ_6CK_14CK_4MS1 + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + 18 + + + INTRCOSC_128KHZ_6CK_14CK_4MS1 + Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + 19 + + + EXTLOFXTAL_1KCK_14CK_4MS1 + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms + 20 + + + EXTLOFXTAL_32KCK_14CK_4MS1 + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms + 21 + + + EXTFSXTAL_258CK_14CK_65MS + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 22 + + + EXTFSXTAL_16KCK_14CK_0MS + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 23 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 24 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 25 + + + EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 26 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 27 + + + EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 28 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 29 + + + EXTXOSC_8MHZ_XX_258CK_14CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 30 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 31 + + + EXTCLK_6CK_14CK_65MS + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + 32 + + + INTRCOSC_8MHZ_6CK_14CK_65MS + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + 34 + + + INTRCOSC_128KHZ_6CK_14CK_65MS + Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + 35 + + + EXTLOFXTAL_1KCK_14CK_65MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms + 36 + + + EXTLOFXTAL_32KCK_14CK_65MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms + 37 + + + EXTFSXTAL_1KCK_14CK_0MS + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 38 + + + EXTFSXTAL_16KCK_14CK_4MS1 + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 39 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 40 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 41 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 42 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 43 + + + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 44 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 45 + + + EXTXOSC_8MHZ_XX_1KCK_14CK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 46 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 47 + + + EXTFSXTAL_1KCK_14CK_4MS1 + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 54 + + + EXTFSXTAL_16KCK_14CK_65MS + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 55 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 56 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 57 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 58 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 59 + + + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 60 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 61 + + + EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 62 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 63 + + + + + CKOUT + Clock output on PORTB0 + [6:6] + + + CKDIV8 + Divide clock by 8 internally + [7:7] + + + + + + + LOCKBIT + Lockbits + 0x0 + + + LOCKBIT + <TBD> + 0x0 + + + LB + Memory Lock + [1:0] + + true + + + + PROG_VER_DISABLED + Further programming and verification disabled + 0 + + + PROG_DISABLED + Further programming disabled + 2 + + + NO_LOCK + No memory lock features enabled + 3 + + + + + BLB0 + Boot Loader Protection Mode + [3:2] + + true + + + + LPM_SPM_DISABLE + LPM and SPM prohibited in Application Section + 0 + + + LPM_DISABLE + LPM prohibited in Application Section + 1 + + + SPM_DISABLE + SPM prohibited in Application Section + 2 + + + NO_LOCK + No lock on SPM and LPM in Application Section + 3 + + + + + BLB1 + Boot Loader Protection Mode + [5:4] + + true + + + + LPM_SPM_DISABLE + LPM and SPM prohibited in Boot Section + 0 + + + LPM_DISABLE + LPM prohibited in Boot Section + 1 + + + SPM_DISABLE + SPM prohibited in Boot Section + 2 + + + NO_LOCK + No lock on SPM and LPM in Boot Section + 3 + + + + + + + + + PORTB + I/O Port + 0x23 + + + DDRB + Port B Data Direction Register + 0x1 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PINB + Port B Input Pins + 0x0 + read-write + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PORTB + Port B Data Register + 0x2 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + + + PORTC + I/O Port + 0x26 + + + DDRC + Port C Data Direction Register + 0x1 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + + + PINC + Port C Input Pins + 0x0 + read-write + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + + + PORTC + Port C Data Register + 0x2 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + + + + + PORTD + I/O Port + 0x29 + + + DDRD + Port D Data Direction Register + 0x1 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PIND + Port D Input Pins + 0x0 + read-write + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PORTD + Port D Data Register + 0x2 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + + + SPI + Serial Peripheral Interface + 0x4C + + + SPCR + SPI Control Register + 0x0 + + + SPR + SPI Clock Rate Selects + [1:0] + + true + + SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 + + + CPHA + Clock Phase + [2:2] + + + CPOL + Clock polarity + [3:3] + + + MSTR + Master/Slave Select + [4:4] + + + DORD + Data Order + [5:5] + + + SPE + SPI Enable + [6:6] + + + SPIE + SPI Interrupt Enable + [7:7] + + + + + SPDR + SPI Data Register + 0x2 + + + 0 + 255 + + + + + SPSR + SPI Status Register + 0x1 + read-write + + + SPI2X + Double SPI Speed Bit + [0:0] + read-write + + WCOL + Write Collision Flag + [6:6] + read-only + + SPIF + SPI Interrupt Flag + [7:7] + read-only + + + + + + TC0 + Timer/Counter, 8-bit + 0x35 + + + GTCCR + General Timer/Counter Control Register + 0xE + + + PSRSYNC + Prescaler Reset Timer/Counter1 and Timer/Counter0 + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + OCR0A + Timer/Counter0 Output Compare Register + 0x12 + + + 0 + 255 + + + + + OCR0B + Timer/Counter0 Output Compare Register + 0x13 + + + 0 + 255 + + + + + TCCR0A + Timer/Counter Control Register A + 0xF + + + WGM0 + Waveform Generation Mode + [1:0] + + true + WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 + + + COM0B + Compare Output B Mode + [5:4] + + true + COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 + + + COM0A + Compare Output A Mode + [7:6] + + true + + + + + + TCCR0B + Timer/Counter Control Register B + 0x10 + + + CS0 + Clock Select + [2:0] + + true + + CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM02 + Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) + [3:3] + + + FOC0B + Force Output Compare B + [6:6] + write-only + + FOC0A + Force Output Compare A + [7:7] + write-only + + + + TCNT0 + Timer/Counter0 + 0x11 + + + 0 + 255 + + + + + TIFR0 + Timer/Counter0 Interrupt Flag register + 0x0 + read-write + + + TOV0 + Timer/Counter0 Overflow Flag + [0:0] + + + OCF0A + Timer/Counter0 Output Compare Flag 0A + [1:1] + + + OCF0B + Timer/Counter0 Output Compare Flag 0B + [2:2] + + + + + TIMSK0 + Timer/Counter0 Interrupt Mask Register + 0x39 + + + TOIE0 + Timer/Counter0 Overflow Interrupt Enable + [0:0] + + + OCIE0A + Timer/Counter0 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE0B + Timer/Counter0 Output Compare Match B Interrupt Enable + [2:2] + + + + + + + TC1 + Timer/Counter, 16-bit + 0x36 + + + GTCCR + General Timer/Counter Control Register + 0xD + + + PSRSYNC + Prescaler Reset Timer/Counter1 and Timer/Counter0 + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + ICR1 + Timer/Counter1 Input Capture Register Bytes + 0x50 + 16 + + + 0 + 65535 + + + + + OCR1A + Timer/Counter1 Output Compare Register Bytes + 0x52 + 16 + + + 0 + 65535 + + + + + OCR1B + Timer/Counter1 Output Compare Register Bytes + 0x54 + 16 + + + 0 + 65535 + + + + + TCCR1A + Timer/Counter1 Control Register A + 0x4A + + + WGM1 + Waveform Generation Mode + [1:0] + + + 0 + 3 + + + + + COM1B + Compare Output Mode 1B, bits + [5:4] + + true + COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM1A + Compare Output Mode 1A, bits + [7:6] + + true + + + + + + TCCR1B + Timer/Counter1 Control Register B + 0x4B + + + CS1 + Prescaler source of Timer/Counter 1 + [2:0] + + true + CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM1 + Waveform Generation Mode + [4:3] + + + 0 + 3 + + + + + ICES1 + Input Capture 1 Edge Select + [6:6] + + + ICNC1 + Input Capture 1 Noise Canceler + [7:7] + + + + + TCCR1C + Timer/Counter1 Control Register C + 0x4C + + + FOC1B + <TBD> + [6:6] + write-only + + FOC1A + <TBD> + [7:7] + write-only + + + + TCNT1 + Timer/Counter1 Bytes + 0x4E + 16 + + + 0 + 65535 + + + + + TIFR1 + Timer/Counter Interrupt Flag register + 0x0 + read-write + + + TOV1 + Timer/Counter1 Overflow Flag + [0:0] + + + OCF1A + Output Compare Flag 1A + [1:1] + + + OCF1B + Output Compare Flag 1B + [2:2] + + + ICF1 + Input Capture Flag 1 + [5:5] + + + + + TIMSK1 + Timer/Counter Interrupt Mask Register + 0x39 + + + TOIE1 + Timer/Counter1 Overflow Interrupt Enable + [0:0] + + + OCIE1A + Timer/Counter1 Output CompareA Match Interrupt Enable + [1:1] + + + OCIE1B + Timer/Counter1 Output CompareB Match Interrupt Enable + [2:2] + + + ICIE1 + Timer/Counter1 Input Capture Interrupt Enable + [5:5] + + + + + + + TC2 + Timer/Counter, 8-bit Async + 0x37 + + + ASSR + Asynchronous Status Register + 0x7F + + + TCR2BUB + Timer/Counter Control Register2 Update Busy + [0:0] + + + TCR2AUB + Timer/Counter Control Register2 Update Busy + [1:1] + + + OCR2BUB + Output Compare Register 2 Update Busy + [2:2] + + + OCR2AUB + Output Compare Register2 Update Busy + [3:3] + + + TCN2UB + Timer/Counter2 Update Busy + [4:4] + + + AS2 + Asynchronous Timer/Counter2 + [5:5] + + + EXCLK + Enable External Clock Input + [6:6] + + + + + GTCCR + General Timer Counter Control register + 0xC + + + PSRASY + Prescaler Reset Timer/Counter2 + [1:1] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + OCR2A + Timer/Counter2 Output Compare Register A + 0x7C + + + 0 + 255 + + + + + OCR2B + Timer/Counter2 Output Compare Register B + 0x7D + + + 0 + 255 + + + + + TCCR2A + Timer/Counter2 Control Register A + 0x79 + + + WGM2 + Waveform Genration Mode + [1:0] + + true + WGM2read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 + + + COM2B + Compare Output B Mode + [5:4] + + true + COM2Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 + + + COM2A + Compare Output A Mode + [7:6] + + true + + + + + + TCCR2B + Timer/Counter2 Control Register B + 0x7A + + + CS2 + Clock Select bits + [2:0] + + true + + CS2read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_32Running, CLK/323PRESCALE_64Running, CLK/644PRESCALE_128Running, CLK/1285PRESCALE_256Running, CLK/2566PRESCALE_1024Running, CLK/10247 + + + WGM22 + Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) + [3:3] + + + FOC2B + Force Output Compare B + [6:6] + write-only + + FOC2A + Force Output Compare A + [7:7] + write-only + + + + TCNT2 + Timer/Counter2 + 0x7B + + + 0 + 255 + + + + + TIFR2 + Timer/Counter Interrupt Flag Register + 0x0 + read-write + + + TOV2 + Timer/Counter2 Overflow Flag + [0:0] + + + OCF2A + Output Compare Flag 2A + [1:1] + + + OCF2B + Output Compare Flag 2B + [2:2] + + + + + TIMSK2 + Timer/Counter Interrupt Mask register + 0x39 + + + TOIE2 + Timer/Counter2 Overflow Interrupt Enable + [0:0] + + + OCIE2A + Timer/Counter2 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE2B + Timer/Counter2 Output Compare Match B Interrupt Enable + [2:2] + + + + + + + TWI + Two Wire Serial Interface + 0xB8 + + + TWAMR + TWI (Slave) Address Mask Register + 0x5 + + + TWAM + TWI (Slave) Address Mask Bits + [7:1] + + + 0 + 127 + + + + + + + TWAR + TWI (Slave) Address register + 0x2 + + + TWGCE + TWI General Call Recognition Enable Bit + [0:0] + + + TWA + TWI (Slave) Address register Bits + [7:1] + + + 0 + 127 + + + + + + + TWBR + TWI Bit Rate register + 0x0 + + + 0 + 255 + + + + + TWCR + TWI Control Register + 0x4 + read-write + + + TWIE + TWI Interrupt Enable + [0:0] + + + TWEN + TWI Enable Bit + [2:2] + + + TWWC + TWI Write Collition Flag + [3:3] + read-only + + TWSTO + TWI Stop Condition Bit + [4:4] + + + TWSTA + TWI Start Condition Bit + [5:5] + + + TWEA + TWI Enable Acknowledge Bit + [6:6] + + + TWINT + TWI Interrupt Flag + [7:7] + + + + + TWDR + TWI Data register + 0x3 + + + 0 + 255 + + + + + TWSR + TWI Status Register + 0x1 + + + TWPS + TWI Prescaler + [1:0] + + true + + TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 + + + TWS + TWI Status + [7:3] + read-only + + 0 + 31 + + + + + + + + + USART0 + USART + 0xC0 + + + UBRR0 + USART Baud Rate Register Bytes + 0x4 + 16 + + + 0 + 65535 + + + + + UCSR0A + USART Control and Status Register A + 0x0 + read-write + + + MPCM0 + Multi-processor Communication Mode + [0:0] + + + U2X0 + Double the USART transmission speed + [1:1] + + + UPE0 + Parity Error + [2:2] + read-only + + DOR0 + Data overRun + [3:3] + read-only + + FE0 + Framing Error + [4:4] + read-only + + UDRE0 + USART Data Register Empty + [5:5] + read-only + + TXC0 + USART Transmit Complete + [6:6] + + + RXC0 + USART Receive Complete + [7:7] + read-only + + + + UCSR0B + USART Control and Status Register B + 0x1 + + + TXB80 + Transmit Data Bit 8 + [0:0] + + + RXB80 + Receive Data Bit 8 + [1:1] + read-only + + UCSZ02 + Character Size - together with UCSZ0 in UCSR0C + [2:2] + + + TXEN0 + Transmitter Enable + [3:3] + + + RXEN0 + Receiver Enable + [4:4] + + + UDRIE0 + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE0 + TX Complete Interrupt Enable + [6:6] + + + RXCIE0 + RX Complete Interrupt Enable + [7:7] + + + + + UCSR0C + USART Control and Status Register C + 0x2 + + + UCPOL0 + Clock Polarity + [0:0] + UCPOL0read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 + + + UCSZ0 + Character Size - together with UCSZ2 in UCSR0B + [2:1] + + + 0 + 3 + + + UCSZ0read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 + + + USBS0 + Stop Bit Select + [3:3] + + true + + USBS0read-writeSTOP11-bit0STOP22-bit1 + + + UPM0 + Parity Mode Bits + [5:4] + + true + + UPM0read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 + + + UMSEL0 + USART Mode Select + [7:6] + + true + + UMSEL0read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 + + + + + UDR0 + USART I/O Data Register + 0x6 + + + 0 + 255 + + + + + + + WDT + Watchdog Timer + 0x60 + + + WDTCSR + Watchdog Timer Control Register + 0x0 + read-write + + + WDE + Watch Dog Enable + [3:3] + + + WDCE + Watchdog Change Enable + [4:4] + + + WDIE + Watchdog Timeout Interrupt Enable + [6:6] + + + WDIF + Watchdog Timeout Interrupt Flag + [7:7] + + WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 + + WDPHWatchdog Timer Prescaler - High Bit[5:5] + + + + + + \ No newline at end of file diff --git a/misc/svd/atmega2560.svd b/misc/svd/atmega2560.svd new file mode 100644 index 0000000..57369c3 --- /dev/null +++ b/misc/svd/atmega2560.svd @@ -0,0 +1,6318 @@ + + Atmel + ATmega2560 + 8 + 8 + read-write + 0 + 0xff + + + AC + Analog Comparator + 0x50 + + + ACSR + Analog Comparator Control And Status Register + 0x0 + read-write + + + ACIS + Analog Comparator Interrupt Mode Select + [1:0] + + true + + ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 + + + ACIC + Analog Comparator Input Capture Enable + [2:2] + + + ACIE + Analog Comparator Interrupt Enable + [3:3] + + + ACI + Analog Comparator Interrupt Flag + [4:4] + + + ACO + Analog Compare Output + [5:5] + read-only + + ACBG + Analog Comparator Bandgap Select + [6:6] + + + ACD + Analog Comparator Disable + [7:7] + + + + + ADCSRB + ADC Control and Status Register B + 0x2B + + + ACME + Analog Comparator Multiplexer Enable + [6:6] + + + + + DIDR1 + Digital Input Disable Register 1 + 0x2F + + + AIN0D + AIN0 Digital Input Disable + [0:0] + + + AIN1D + AIN1 Digital Input Disable + [1:1] + + + + + + + ADC + Analog-to-Digital Converter + 0x78 + + + ADC + ADC Data Register Bytes + 0x0 + 16 + + + 0 + 65535 + + + + + ADCSRA + The ADC Control and Status register A + 0x2 + read-write + + + ADPS + ADC Prescaler Select Bits + [2:0] + + true + + ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 + + + ADIE + ADC Interrupt Enable + [3:3] + + + ADIF + ADC Interrupt Flag + [4:4] + + + ADATE + ADC Auto Trigger Enable + [5:5] + + + ADSC + ADC Start Conversion + [6:6] + + + ADEN + ADC Enable + [7:7] + + + + + ADCSRB + The ADC Control and Status register B + 0x3 + + + ADTS + ADC Auto Trigger Source bits + [2:0] + + true + + + + VAL_0x00 + Free Running mode + 0 + + + VAL_0x01 + Analog Comparator + 1 + + + VAL_0x02 + External Interrupt Request 0 + 2 + + + VAL_0x03 + Timer/Counter0 Compare Match A + 3 + + + VAL_0x04 + Timer/Counter0 Overflow + 4 + + + VAL_0x05 + Timer/Counter1 Compare Match B + 5 + + + VAL_0x06 + Timer/Counter1 Overflow + 6 + + + VAL_0x07 + Timer/Counter1 Capture Event + 7 + + + + + MUX5 + Analog Channel and Gain Selection Bits + [3:3] + + + ACME + <TBD> + [6:6] + + + + + ADMUX + The ADC multiplexer Selection Register + 0x4 + + + MUX + Analog Channel and Gain Selection Bits + [4:0] + + true + + + + ADC0 + ADC Single Ended Input pin 0 + 0 + + + ADC1 + ADC Single Ended Input pin 1 + 1 + + + ADC2 + ADC Single Ended Input pin 2 + 2 + + + ADC3 + ADC Single Ended Input pin 3 + 3 + + + ADC4 + ADC Single Ended Input pin 4 + 4 + + + ADC5 + ADC Single Ended Input pin 5 + 5 + + + ADC6 + ADC Single Ended Input pin 6 + 6 + + + ADC7 + ADC Single Ended Input pin 7 + 7 + + + ADC0_ADC0_10X + ADC Differential Inputs Postive pin 0 Negative pin 0 10x Gain + 8 + + + ADC1_ADC0_10X + ADC Differential Inputs Postive pin 1 Negative pin 0 10x Gain + 9 + + + ADC0_ADC0_200x + ADC Differential Inputs Postive pin 0 Negative pin 0 200x Gain + 10 + + + ADC1_ADC0_200X + ADC Differential Inputs Postive pin 1 Negative pin 0 200x Gain + 11 + + + ADC2_ADC2_10X + ADC Differential Inputs Postive pin 2 Negative pin 2 10x Gain + 12 + + + ADC3_ADC2_10X + ADC Differential Inputs Postive pin 3 Negative pin 2 10x Gain + 13 + + + ADC2_ADC2_200X + ADC Differential Inputs Postive pin 2 Negative pin 2 200x Gain + 14 + + + ADC3_ADC2_200X + ADC Differential Inputs Postive pin 3 Negative pin 2 200x Gain + 15 + + + ADC0_ADC1_1X + ADC Differential Inputs Postive pin 0 Negative pin 1 1x Gain + 16 + + + ADC1_ADC1_1X + ADC Differential Inputs Postive pin 1 Negative pin 1 1x Gain + 17 + + + ADC2_ADC1_1X + ADC Differential Inputs Postive pin 2 Negative pin 1 1x Gain + 18 + + + ADC3_ADC1_1X + ADC Differential Inputs Postive pin 3 Negative pin 1 1x Gain + 19 + + + ADC4_ADC1_1X + ADC Differential Inputs Postive pin 4 Negative pin 1 1x Gain + 20 + + + ADC5_ADC1_1X + ADC Differential Inputs Postive pin 5 Negative pin 1 1x Gain + 21 + + + ADC6_ADC1_1X + ADC Differential Inputs Postive pin 6 Negative pin 1 1x Gain + 22 + + + ADC7_ADC1_1X + ADC Differential Inputs Postive pin 7 Negative pin 1 1x Gain + 23 + + + ADC0_ADC2_1X + ADC Differential Inputs Postive pin 0 Negative pin 2 1x Gain + 24 + + + ADC1_ADC2_1X + ADC Differential Inputs Postive pin 1 Negative pin 2 1x Gain + 25 + + + ADC2_ADC2_1X + ADC Differential Inputs Postive pin 2 Negative pin 2 1x Gain + 26 + + + ADC3_ADC2_1X + ADC Differential Inputs Postive pin 3 Negative pin 2 1x Gain + 27 + + + ADC4_ADC2_1X + ADC Differential Inputs Postive pin 4 Negative pin 2 1x Gain + 28 + + + ADC5_ADC2_1X + ADC Differential Inputs Postive pin 5 Negative pin 2 1x Gain + 29 + + + ADC_VBG + Internal Reference (VBG) + 30 + + + ADC_GND + 0V (GND) + 31 + + + + + ADLAR + Left Adjust Result + [5:5] + + + REFS + Reference Selection Bits + [7:6] + + true + + REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 + + + + + DIDR0 + Digital Input Disable Register + 0x6 + + + ADC0D + <TBD> + [0:0] + + + ADC1D + <TBD> + [1:1] + + + ADC2D + <TBD> + [2:2] + + + ADC3D + <TBD> + [3:3] + + + ADC4D + <TBD> + [4:4] + + + ADC5D + <TBD> + [5:5] + + + ADC6D + <TBD> + [6:6] + + + ADC7D + <TBD> + [7:7] + + + + + DIDR2 + Digital Input Disable Register + 0x5 + + + ADC8D + <TBD> + [0:0] + + + ADC9D + <TBD> + [1:1] + + + ADC10D + <TBD> + [2:2] + + + ADC11D + <TBD> + [3:3] + + + ADC12D + <TBD> + [4:4] + + + ADC13D + <TBD> + [5:5] + + + ADC14D + <TBD> + [6:6] + + + ADC15D + <TBD> + [7:7] + + + + + + + BOOT_LOAD + Bootloader + 0x57 + + + SPMCSR + Store Program Memory Control Register + 0x0 + + + SPMEN + Store Program Memory Enable + [0:0] + + + PGERS + Page Erase + [1:1] + + + PGWRT + Page Write + [2:2] + + + BLBSET + Boot Lock Bit Set + [3:3] + + + RWWSRE + Read While Write section read enable + [4:4] + + + SIGRD + Signature Row Read + [5:5] + + + RWWSB + Read While Write Section Busy + [6:6] + + + SPMIE + SPM Interrupt Enable + [7:7] + + + + + + + CPU + CPU Registers + 0x3E + + RESET + External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + 0 + + + INT0 + External Interrupt Request 0 + 1 + + + INT1 + External Interrupt Request 1 + 2 + + + INT2 + External Interrupt Request 2 + 3 + + + INT3 + External Interrupt Request 3 + 4 + + + INT4 + External Interrupt Request 4 + 5 + + + INT5 + External Interrupt Request 5 + 6 + + + INT6 + External Interrupt Request 6 + 7 + + + INT7 + External Interrupt Request 7 + 8 + + + PCINT0 + Pin Change Interrupt Request 0 + 9 + + + PCINT1 + Pin Change Interrupt Request 1 + 10 + + + PCINT2 + Pin Change Interrupt Request 2 + 11 + + + WDT + Watchdog Time-out Interrupt + 12 + + + TIMER2_COMPA + Timer/Counter2 Compare Match A + 13 + + + TIMER2_COMPB + Timer/Counter2 Compare Match B + 14 + + + TIMER2_OVF + Timer/Counter2 Overflow + 15 + + + TIMER1_CAPT + Timer/Counter1 Capture Event + 16 + + + TIMER1_COMPA + Timer/Counter1 Compare Match A + 17 + + + TIMER1_COMPB + Timer/Counter1 Compare Match B + 18 + + + TIMER1_COMPC + Timer/Counter1 Compare Match C + 19 + + + TIMER1_OVF + Timer/Counter1 Overflow + 20 + + + TIMER0_COMPA + Timer/Counter0 Compare Match A + 21 + + + TIMER0_COMPB + Timer/Counter0 Compare Match B + 22 + + + TIMER0_OVF + Timer/Counter0 Overflow + 23 + + + SPI_STC + SPI Serial Transfer Complete + 24 + + + USART0_RX + USART0, Rx Complete + 25 + + + USART0_UDRE + USART0 Data register Empty + 26 + + + USART0_TX + USART0, Tx Complete + 27 + + + ANALOG_COMP + Analog Comparator + 28 + + + ADC + ADC Conversion Complete + 29 + + + EE_READY + EEPROM Ready + 30 + + + TIMER3_CAPT + Timer/Counter3 Capture Event + 31 + + + TIMER3_COMPA + Timer/Counter3 Compare Match A + 32 + + + TIMER3_COMPB + Timer/Counter3 Compare Match B + 33 + + + TIMER3_COMPC + Timer/Counter3 Compare Match C + 34 + + + TIMER3_OVF + Timer/Counter3 Overflow + 35 + + + USART1_RX + USART1, Rx Complete + 36 + + + USART1_UDRE + USART1 Data register Empty + 37 + + + USART1_TX + USART1, Tx Complete + 38 + + + TWI + 2-wire Serial Interface + 39 + + + SPM_READY + Store Program Memory Read + 40 + + + TIMER4_CAPT + Timer/Counter4 Capture Event + 41 + + + TIMER4_COMPA + Timer/Counter4 Compare Match A + 42 + + + TIMER4_COMPB + Timer/Counter4 Compare Match B + 43 + + + TIMER4_COMPC + Timer/Counter4 Compare Match C + 44 + + + TIMER4_OVF + Timer/Counter4 Overflow + 45 + + + TIMER5_CAPT + Timer/Counter5 Capture Event + 46 + + + TIMER5_COMPA + Timer/Counter5 Compare Match A + 47 + + + TIMER5_COMPB + Timer/Counter5 Compare Match B + 48 + + + TIMER5_COMPC + Timer/Counter5 Compare Match C + 49 + + + TIMER5_OVF + Timer/Counter5 Overflow + 50 + + + USART2_RX + USART2, Rx Complete + 51 + + + USART2_UDRE + USART2 Data register Empty + 52 + + + USART2_TX + USART2, Tx Complete + 53 + + + USART3_RX + USART3, Rx Complete + 54 + + + USART3_UDRE + USART3 Data register Empty + 55 + + + USART3_TX + USART3, Tx Complete + 56 + + + + CLKPR + <TBD> + 0x23 + + + CLKPS + <TBD> + [3:0] + + true + + + + VAL_0x00 + 1 + 0 + + + VAL_0x01 + 2 + 1 + + + VAL_0x02 + 4 + 2 + + + VAL_0x03 + 8 + 3 + + + VAL_0x04 + 16 + 4 + + + VAL_0x05 + 32 + 5 + + + VAL_0x06 + 64 + 6 + + + VAL_0x07 + 128 + 7 + + + VAL_0x08 + 256 + 8 + + + + + CLKPCE + <TBD> + [7:7] + + + + + EIND + Extended Indirect Register + 0x1E + + + 0 + 255 + + + + + GPIOR0 + General Purpose IO Register 0 + 0x0 + + + GPIOR00 + General Purpose IO Register 0 bit 0 + [0:0] + + + GPIOR01 + General Purpose IO Register 0 bit 1 + [1:1] + + + GPIOR02 + General Purpose IO Register 0 bit 2 + [2:2] + + + GPIOR03 + General Purpose IO Register 0 bit 3 + [3:3] + + + GPIOR04 + General Purpose IO Register 0 bit 4 + [4:4] + + + GPIOR05 + General Purpose IO Register 0 bit 5 + [5:5] + + + GPIOR06 + General Purpose IO Register 0 bit 6 + [6:6] + + + GPIOR07 + General Purpose IO Register 0 bit 7 + [7:7] + + + + + GPIOR1 + General Purpose IO Register 1 + 0xC + + + GPIOR + General Purpose IO Register 1 bis + [7:0] + + + 0 + 255 + + + + + + + GPIOR2 + General Purpose IO Register 2 + 0xD + + + GPIOR + General Purpose IO Register 2 bis + [7:0] + + + 0 + 255 + + + + + + + MCUCR + MCU Control Register + 0x17 + + + IVCE + Interrupt Vector Change Enable + [0:0] + + + IVSEL + Interrupt Vector Select + [1:1] + + + PUD + Pull-up disable + [4:4] + + + JTD + JTAG Interface Disable + [7:7] + + + + + MCUSR + MCU Status Register + 0x16 + read-only + + + PORF + Power-on reset flag + [0:0] + + + EXTRF + External Reset Flag + [1:1] + + + BORF + Brown-out Reset Flag + [2:2] + + + WDRF + Watchdog Reset Flag + [3:3] + + + JTRF + JTAG Reset Flag + [4:4] + + + + + OSCCAL + Oscillator Calibration Value + 0x28 + + + OSCCAL + Oscillator Calibration + [7:0] + + + 0 + 255 + + + + + + + PRR0 + Power Reduction Register0 + 0x26 + + + PRADC + Power Reduction ADC + [0:0] + + + PRUSART0 + Power Reduction USART0 + [1:1] + + + PRSPI + Power Reduction Serial Peripheral Interface + [2:2] + + + PRTIM1 + Power Reduction Timer/Counter1 + [3:3] + + + PRTIM0 + Power Reduction Timer/Counter0 + [5:5] + + + PRTIM2 + Power Reduction Timer/Counter2 + [6:6] + + + PRTWI + Power Reduction TWI + [7:7] + + + + + PRR1 + Power Reduction Register1 + 0x27 + + + PRUSART1 + Power Reduction USART1 + [0:0] + + + PRUSART2 + Power Reduction USART2 + [1:1] + + + PRUSART3 + Power Reduction USART3 + [2:2] + + + PRTIM3 + Power Reduction Timer/Counter3 + [3:3] + + + PRTIM4 + Power Reduction Timer/Counter4 + [4:4] + + + PRTIM5 + Power Reduction Timer/Counter5 + [5:5] + + + + + RAMPZ + RAM Page Z Select Register + 0x1D + + + 0 + 255 + + + + + SMCR + Sleep Mode Control Register + 0x15 + + + SE + Sleep Enable + [0:0] + + + SM + Sleep Mode Select bits + [3:1] + + true + + + + IDLE + Idle + 0 + + + ADC + ADC Noise Reduction (If Available) + 1 + + + PDOWN + Power Down + 2 + + + PSAVE + Power Save + 3 + + + VAL_0x04 + Reserved + 4 + + + VAL_0x05 + Reserved + 5 + + + STDBY + Standby + 6 + + + ESTDBY + Extended Standby + 7 + + + + + + + XMCRA + External Memory Control Register A + 0x36 + + + SRW0 + Wait state select bit lower page + [1:0] + + true + + + + VAL_0x00 + No wait-states + 0 + + + VAL_0x01 + Wait one cycle during read/write strobe + 1 + + + VAL_0x02 + Wait two cycles during read/write strobe + 2 + + + VAL_0x03 + Wait two cycles during read/write and wait one cycle before driving out new address + 3 + + + + + SRW1 + Wait state select bit upper page + [3:2] + + true + + + + VAL_0x00 + No wait-states + 0 + + + VAL_0x01 + Wait one cycle during read/write strobe + 1 + + + VAL_0x02 + Wait two cycles during read/write strobe + 2 + + + VAL_0x03 + Wait two cycles during read/write and wait one cycle before driving out new address + 3 + + + + + SRL + Wait state page limit + [6:4] + + true + + + + VAL_0x00 + LS = N/A, US = 0x1100 - 0xFFFF + 0 + + + VAL_0x01 + LS = 0x2200 - 0x1FFF, US = 0x2000 - 0xFFFF + 1 + + + VAL_0x02 + LS = 0x2200 - 0x3FFF, US = 0x4000 - 0xFFFF + 2 + + + VAL_0x03 + LS = 0x2200 - 0x5FFF, US = 0x6000 - 0xFFFF + 3 + + + VAL_0x04 + LS = 0x2200 - 0x7FFF, US = 0x8000 - 0xFFFF + 4 + + + VAL_0x05 + LS = 0x2200 - 0x9FFF, US = 0xA000 - 0xFFFF + 5 + + + VAL_0x06 + LS = 0x2200 - 0xBFFF, US = 0xC000 - 0xFFFF + 6 + + + VAL_0x07 + LS = 0x2200 - 0xDFFF, US = 0xE000 - 0xFFFF + 7 + + + + + SRE + External SRAM Enable + [7:7] + + + + + XMCRB + External Memory Control Register B + 0x37 + + + XMM + External Memory High Mask + [2:0] + + + 0 + 7 + + + + + XMBK + External Memory Bus Keeper Enable + [7:7] + + + + + + + EEPROM + EEPROM + 0x3F + + + EEAR + EEPROM Address Register Low Bytes + 0x2 + 16 + + + 0 + 65535 + + + + + EECR + EEPROM Control Register + 0x0 + + + EERE + EEPROM Read Enable + [0:0] + + + EEPE + EEPROM Write Enable + [1:1] + + + EEMPE + EEPROM Master Write Enable + [2:2] + + + EERIE + EEPROM Ready Interrupt Enable + [3:3] + + + EEPM + EEPROM Programming Mode Bits + [5:4] + + true + + + + VAL_0x00 + Erase and Write in one operation + 0 + + + VAL_0x01 + Erase Only + 1 + + + VAL_0x02 + Write Only + 2 + + + + + + + EEDR + EEPROM Data Register + 0x1 + + + 0 + 255 + + + + + + + EXINT + External Interrupts + 0x3B + + + EICRA + External Interrupt Control Register A + 0x2E + + + ISC0 + External Interrupt Sense Control Bit + [1:0] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC1 + External Interrupt Sense Control Bit + [3:2] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC2 + External Interrupt Sense Control Bit + [5:4] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC3 + External Interrupt Sense Control Bit + [7:6] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + + + EICRB + External Interrupt Control Register B + 0x2F + + + ISC4 + External Interrupt 7-4 Sense Control Bit + [1:0] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC5 + External Interrupt 7-4 Sense Control Bit + [3:2] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC6 + External Interrupt 7-4 Sense Control Bit + [5:4] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC7 + External Interrupt 7-4 Sense Control Bit + [7:6] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + + + EIFR + External Interrupt Flag Register + 0x1 + read-only + + + INTF + External Interrupt Flags + [7:0] + + + 0 + 255 + + + + + + + EIMSK + External Interrupt Mask Register + 0x2 + + + INT + External Interrupt Request 7 Enable + [7:0] + + + 0 + 255 + + + + + + + PCICR + Pin Change Interrupt Control Register + 0x2D + + + PCIE + Pin Change Interrupt Enables + [2:0] + + + 0 + 7 + + + + + + + PCIFR + Pin Change Interrupt Flag Register + 0x0 + read-only + + + PCIF + Pin Change Interrupt Flags + [2:0] + + + 0 + 7 + + + + + + + PCMSK0 + Pin Change Mask Register 0 + 0x30 + + + PCINT + Pin Change Mask interrupt + [7:0] + + + 0 + 255 + + + + + + + PCMSK1 + Pin Change Mask Register 1 + 0x31 + + + PCINT + Pin Change Mask interrupt + [7:0] + + + 0 + 255 + + + + + + + PCMSK2 + Pin Change Mask Register 2 + 0x32 + + + PCINT + Pin Change Mask interrupt + [7:0] + + + 0 + 255 + + + + + + + + + FUSE + Fuses + 0x0 + + + EXTENDED + <TBD> + 0x2 + + + BODLEVEL + Brown-out Detector trigger level + [2:0] + + true + + + + 4V3 + Brown-out detection at VCC=4.3 V + 4 + + + 2V7 + Brown-out detection at VCC=2.7 V + 5 + + + 1V8 + Brown-out detection at VCC=1.8 V + 6 + + + DISABLED + Brown-out detection disabled + 7 + + + + + + + HIGH + <TBD> + 0x1 + + + BOOTRST + Boot Reset vector Enabled + [0:0] + + + BOOTSZ + Select Boot Size + [2:1] + + true + + + + 4096W_1F000 + Boot Flash size=4096 words start address=$1F000 + 0 + + + 2048W_1F800 + Boot Flash size=2048 words start address=$1F800 + 1 + + + 1024W_1FC00 + Boot Flash size=1024 words start address=$1FC00 + 2 + + + 512W_1FE00 + Boot Flash size=512 words start address=$1FE00 + 3 + + + + + EESAVE + Preserve EEPROM through the Chip Erase cycle + [3:3] + + + WDTON + Watchdog timer always on + [4:4] + + + SPIEN + Serial program downloading (SPI) enabled + [5:5] + + + JTAGEN + JTAG Interface Enabled + [6:6] + + + OCDEN + On-Chip Debug Enabled + [7:7] + + + + + LOW + <TBD> + 0x0 + + + SUT_CKSEL + Select Clock Source + [5:0] + + true + + + + EXTCLK_6CK_0MS + Ext. Clock; Start-up time: 6 CK + 0 ms + 0 + + + INTRCOSC_6CK_0MS + Int. RC Osc.; Start-up time: 6 CK + 0 ms + 2 + + + INTRCOSC_128KHZ_6CK_0MS + Int. 128kHz RC Osc.; Start-up time: 6 CK + 0 ms + 3 + + + EXTLOFXTAL_1KCK_0MS + Ext. Low-Freq. Crystal; Start-up time: 1K CK + 0 ms + 4 + + + EXTLOFXTAL_32KCK_0MS + Ext. Low-Freq. Crystal; Start-up time: 32K CK + 0 ms + 5 + + + FSOSC_258CK_4MS1_CRES_FASTPWR + Full Swing Oscillator; Start-up time: 258 CK + 4.1 ms; Ceramic res.; fast rising power + 6 + + + FSOSC_1KCK_65MS_CRES_SLOWPWR + Full Swing Oscillator; Start-up time: 1K CK + 65 ms; Ceramic res.; slowly rising power + 7 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 258 CK + 4.1 ms + 8 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 65 ms + 9 + + + EXTXOSC_0MHZ9_3MHZ_258CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 258 CK + 4.1 ms + 10 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 65 ms + 11 + + + EXTXOSC_3MHZ_8MHZ_258CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 258 CK + 4.1 ms + 12 + + + EXTXOSC_3MHZ_8MHZ_1KCK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 65 ms + 13 + + + EXTXOSC_8MHZ_XX_258CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time: 258 CK + 4.1 ms + 14 + + + EXTXOSC_8MHZ_XX_1KCK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 65 ms + 15 + + + EXTCLK_6CK_4MS1 + Ext. Clock; Start-up time: 6 CK + 4.1 ms + 16 + + + INTRCOSC_6CK_4MS1 + Int. RC Osc.; Start-up time: 6 CK + 4.1 ms + 18 + + + INTRCOSC_128KHZ_6CK_4MS + Int. 128kHz RC Osc.; Start-up time: 6 CK + 4 ms + 19 + + + EXTLOFXTAL_1KCK_4MS1 + Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4.1 ms + 20 + + + EXTLOFXTAL_32KCK_4MS1 + Ext. Low-Freq. Crystal; Start-up time: 32K CK + 4.1 ms + 21 + + + FSOSC_258CK_65MS_CRES_SLOWPWR + Full Swing Oscillator; Start-up time: 258 CK + 65 ms; Ceramic res.; slowly rising power + 22 + + + FSOSC_16KCK_0MS_XOSC_BODEN + Full Swing Oscillator; Start-up time: 16K CK + 0 ms; Crystal Osc.; BOD enabled + 23 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 258 CK + 65 ms + 24 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 0 ms + 25 + + + EXTXOSC_0MHZ9_3MHZ_258CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 258 CK + 65 ms + 26 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 0 ms + 27 + + + EXTXOSC_3MHZ_8MHZ_258CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 258 CK + 65 ms + 28 + + + EXTXOSC_3MHZ_8MHZ_16KCK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 0 ms + 29 + + + EXTXOSC_8MHZ_XX_258CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 258 CK + 65 ms + 30 + + + EXTXOSC_8MHZ_XX_16KCK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 0 ms + 31 + + + EXTCLK_6CK_65MS + Ext. Clock; Start-up time: 6 CK + 65 ms + 32 + + + INTRCOSC_6CK_65MS + Int. RC Osc.; Start-up time: 6 CK + 65 ms + 34 + + + INTRCOSC_128KHZ_6CK_64MS + Int. 128kHz RC Osc.; Start-up time: 6 CK + 64 ms + 35 + + + EXTLOFXTAL_1KCK_65MS + Ext. Low-Freq. Crystal; Start-up time: 1K CK + 65 ms + 36 + + + EXTLOFXTAL_32KCK_65MS + Ext. Low-Freq. Crystal; Start-up time: 32K CK + 65 ms + 37 + + + FSOSC_1KCK_0MS_CRES_BODEN + Full Swing Oscillator; Start-up time: 1K CK + 0 ms; Ceramic res.; BOD enable + 38 + + + FSOSC_16KCK_4MS1_XOSC_FASTPWR + Full Swing Oscillator; Start-up time: 16K CK + 4.1 ms; Crystal Osc.; fast rising power + 39 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 0 ms + 40 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 4.1 ms + 41 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 0 ms + 42 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 4.1 ms + 43 + + + EXTXOSC_3MHZ_8MHZ_1KCK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 0 ms + 44 + + + EXTXOSC_3MHZ_8MHZ_16KCK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 4.1 ms + 45 + + + EXTXOSC_8MHZ_XX_1KCK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 0 ms + 46 + + + EXTXOSC_8MHZ_XX_16KCK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 4.1 ms + 47 + + + FSOSC_1KCK_4MS1_CRES_FASTPWR + Full Swing Oscillator; Start-up time: 1K CK + 4.1 ms; Ceramic res.; fast rising power + 54 + + + FSOSC_16KCK_65MS_XOSC_SLOWPWR + Full Swing Oscillator; Start-up time: 16K CK + 65 ms; Crystal Osc.; slowly rising power + 55 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 4.1 ms + 56 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 65 ms + 57 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 4.1 ms + 58 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 65 ms + 59 + + + EXTXOSC_3MHZ_8MHZ_1KCK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 4.1 ms + 60 + + + EXTXOSC_3MHZ_8MHZ_16KCK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 65 ms + 61 + + + EXTXOSC_8MHZ_XX_1KCK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 4.1 ms + 62 + + + EXTXOSC_8MHZ_XX_16KCK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 65 ms + 63 + + + + + CKOUT + Clock output on PORTE7 + [6:6] + + + CKDIV8 + Divide clock by 8 internally + [7:7] + + + + + + + JTAG + JTAG Interface + 0x51 + + + MCUCR + MCU Control Register + 0x4 + + + JTD + JTAG Interface Disable + [7:7] + + + + + MCUSR + MCU Status Register + 0x3 + read-only + + + JTRF + JTAG Reset Flag + [4:4] + + + + + OCDR + On-Chip Debug Related Register in I/O Memory + 0x0 + + + 0 + 255 + + + + + + + LOCKBIT + Lockbits + 0x0 + + + LOCKBIT + <TBD> + 0x0 + + + LB + Memory Lock + [1:0] + + true + + + + PROG_VER_DISABLED + Further programming and verification disabled + 0 + + + PROG_DISABLED + Further programming disabled + 2 + + + NO_LOCK + No memory lock features enabled + 3 + + + + + BLB0 + Boot Loader Protection Mode + [3:2] + + true + + + + LPM_SPM_DISABLE + LPM and SPM prohibited in Application Section + 0 + + + LPM_DISABLE + LPM prohibited in Application Section + 1 + + + SPM_DISABLE + SPM prohibited in Application Section + 2 + + + NO_LOCK + No lock on SPM and LPM in Application Section + 3 + + + + + BLB1 + Boot Loader Protection Mode + [5:4] + + true + + + + LPM_SPM_DISABLE + LPM and SPM prohibited in Boot Section + 0 + + + LPM_DISABLE + LPM prohibited in Boot Section + 1 + + + SPM_DISABLE + SPM prohibited in Boot Section + 2 + + + NO_LOCK + No lock on SPM and LPM in Boot Section + 3 + + + + + + + + + PORTA + I/O Port + 0x20 + + + DDRA + Port A Data Direction Register + 0x1 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + PINA + Port A Input Pins + 0x0 + read-write + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + PORTA + Port A Data Register + 0x2 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + + + PORTB + I/O Port + 0x23 + + + DDRB + Port B Data Direction Register + 0x1 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PINB + Port B Input Pins + 0x0 + read-write + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PORTB + Port B Data Register + 0x2 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + + + PORTC + I/O Port + 0x26 + + + DDRC + Port C Data Direction Register + 0x1 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + PINC + Port C Input Pins + 0x0 + read-write + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + PORTC + Port C Data Register + 0x2 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + + + PORTD + I/O Port + 0x29 + + + DDRD + Port D Data Direction Register + 0x1 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PIND + Port D Input Pins + 0x0 + read-write + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PORTD + Port D Data Register + 0x2 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + + + PORTE + I/O Port + 0x2C + + + DDRE + Data Direction Register, Port E + 0x1 + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + PE4 + Pin E4 + [4:4] + + + PE5 + Pin E5 + [5:5] + + + PE6 + Pin E6 + [6:6] + + + PE7 + Pin E7 + [7:7] + + + + + PINE + Input Pins, Port E + 0x0 + read-write + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + PE4 + Pin E4 + [4:4] + + + PE5 + Pin E5 + [5:5] + + + PE6 + Pin E6 + [6:6] + + + PE7 + Pin E7 + [7:7] + + + + + PORTE + Data Register, Port E + 0x2 + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + PE4 + Pin E4 + [4:4] + + + PE5 + Pin E5 + [5:5] + + + PE6 + Pin E6 + [6:6] + + + PE7 + Pin E7 + [7:7] + + + + + + + PORTF + I/O Port + 0x2F + + + DDRF + Data Direction Register, Port F + 0x1 + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF2 + Pin F2 + [2:2] + + + PF3 + Pin F3 + [3:3] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + PF7 + Pin F7 + [7:7] + + + + + PINF + Input Pins, Port F + 0x0 + read-write + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF2 + Pin F2 + [2:2] + + + PF3 + Pin F3 + [3:3] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + PF7 + Pin F7 + [7:7] + + + + + PORTF + Data Register, Port F + 0x2 + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF2 + Pin F2 + [2:2] + + + PF3 + Pin F3 + [3:3] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + PF7 + Pin F7 + [7:7] + + + + + + + PORTG + I/O Port + 0x32 + + + DDRG + Data Direction Register, Port G + 0x1 + + + PG0 + Pin G0 + [0:0] + + + PG1 + Pin G1 + [1:1] + + + PG2 + Pin G2 + [2:2] + + + PG3 + Pin G3 + [3:3] + + + PG4 + Pin G4 + [4:4] + + + PG5 + Pin G5 + [5:5] + + + PG6 + Pin G6 + [6:6] + + + PG7 + Pin G7 + [7:7] + + + + + PING + Input Pins, Port G + 0x0 + read-write + + PG0 + Pin G0 + [0:0] + + + PG1 + Pin G1 + [1:1] + + + PG2 + Pin G2 + [2:2] + + + PG3 + Pin G3 + [3:3] + + + PG4 + Pin G4 + [4:4] + + + PG5 + Pin G5 + [5:5] + + + PG6 + Pin G6 + [6:6] + + + PG7 + Pin G7 + [7:7] + + + + + PORTG + Data Register, Port G + 0x2 + + + PG0 + Pin G0 + [0:0] + + + PG1 + Pin G1 + [1:1] + + + PG2 + Pin G2 + [2:2] + + + PG3 + Pin G3 + [3:3] + + + PG4 + Pin G4 + [4:4] + + + PG5 + Pin G5 + [5:5] + + + PG6 + Pin G6 + [6:6] + + + PG7 + Pin G7 + [7:7] + + + + + + + PORTH + I/O Port + 0x100 + + + DDRH + PORT H Data Direction Register + 0x1 + + + PH0 + Pin H0 + [0:0] + + + PH1 + Pin H1 + [1:1] + + + PH2 + Pin H2 + [2:2] + + + PH3 + Pin H3 + [3:3] + + + PH4 + Pin H4 + [4:4] + + + PH5 + Pin H5 + [5:5] + + + PH6 + Pin H6 + [6:6] + + + PH7 + Pin H7 + [7:7] + + + + + PINH + PORT H Input Pins + 0x0 + read-write + + PH0 + Pin H0 + [0:0] + + + PH1 + Pin H1 + [1:1] + + + PH2 + Pin H2 + [2:2] + + + PH3 + Pin H3 + [3:3] + + + PH4 + Pin H4 + [4:4] + + + PH5 + Pin H5 + [5:5] + + + PH6 + Pin H6 + [6:6] + + + PH7 + Pin H7 + [7:7] + + + + + PORTH + PORT H Data Register + 0x2 + + + PH0 + Pin H0 + [0:0] + + + PH1 + Pin H1 + [1:1] + + + PH2 + Pin H2 + [2:2] + + + PH3 + Pin H3 + [3:3] + + + PH4 + Pin H4 + [4:4] + + + PH5 + Pin H5 + [5:5] + + + PH6 + Pin H6 + [6:6] + + + PH7 + Pin H7 + [7:7] + + + + + + + PORTJ + I/O Port + 0x103 + + + DDRJ + PORT J Data Direction Register + 0x1 + + + PJ0 + Pin J0 + [0:0] + + + PJ1 + Pin J1 + [1:1] + + + PJ2 + Pin J2 + [2:2] + + + PJ3 + Pin J3 + [3:3] + + + PJ4 + Pin J4 + [4:4] + + + PJ5 + Pin J5 + [5:5] + + + PJ6 + Pin J6 + [6:6] + + + PJ7 + Pin J7 + [7:7] + + + + + PINJ + PORT J Input Pins + 0x0 + read-write + + PJ0 + Pin J0 + [0:0] + + + PJ1 + Pin J1 + [1:1] + + + PJ2 + Pin J2 + [2:2] + + + PJ3 + Pin J3 + [3:3] + + + PJ4 + Pin J4 + [4:4] + + + PJ5 + Pin J5 + [5:5] + + + PJ6 + Pin J6 + [6:6] + + + PJ7 + Pin J7 + [7:7] + + + + + PORTJ + PORT J Data Register + 0x2 + + + PJ0 + Pin J0 + [0:0] + + + PJ1 + Pin J1 + [1:1] + + + PJ2 + Pin J2 + [2:2] + + + PJ3 + Pin J3 + [3:3] + + + PJ4 + Pin J4 + [4:4] + + + PJ5 + Pin J5 + [5:5] + + + PJ6 + Pin J6 + [6:6] + + + PJ7 + Pin J7 + [7:7] + + + + + + + PORTK + I/O Port + 0x106 + + + DDRK + PORT K Data Direction Register + 0x1 + + + PK0 + Pin K0 + [0:0] + + + PK1 + Pin K1 + [1:1] + + + PK2 + Pin K2 + [2:2] + + + PK3 + Pin K3 + [3:3] + + + PK4 + Pin K4 + [4:4] + + + PK5 + Pin K5 + [5:5] + + + PK6 + Pin K6 + [6:6] + + + PK7 + Pin K7 + [7:7] + + + + + PINK + PORT K Input Pins + 0x0 + read-write + + PK0 + Pin K0 + [0:0] + + + PK1 + Pin K1 + [1:1] + + + PK2 + Pin K2 + [2:2] + + + PK3 + Pin K3 + [3:3] + + + PK4 + Pin K4 + [4:4] + + + PK5 + Pin K5 + [5:5] + + + PK6 + Pin K6 + [6:6] + + + PK7 + Pin K7 + [7:7] + + + + + PORTK + PORT K Data Register + 0x2 + + + PK0 + Pin K0 + [0:0] + + + PK1 + Pin K1 + [1:1] + + + PK2 + Pin K2 + [2:2] + + + PK3 + Pin K3 + [3:3] + + + PK4 + Pin K4 + [4:4] + + + PK5 + Pin K5 + [5:5] + + + PK6 + Pin K6 + [6:6] + + + PK7 + Pin K7 + [7:7] + + + + + + + PORTL + I/O Port + 0x109 + + + DDRL + PORT L Data Direction Register + 0x1 + + + PL0 + Pin L0 + [0:0] + + + PL1 + Pin L1 + [1:1] + + + PL2 + Pin L2 + [2:2] + + + PL3 + Pin L3 + [3:3] + + + PL4 + Pin L4 + [4:4] + + + PL5 + Pin L5 + [5:5] + + + PL6 + Pin L6 + [6:6] + + + PL7 + Pin L7 + [7:7] + + + + + PINL + PORT L Input Pins + 0x0 + read-write + + PL0 + Pin L0 + [0:0] + + + PL1 + Pin L1 + [1:1] + + + PL2 + Pin L2 + [2:2] + + + PL3 + Pin L3 + [3:3] + + + PL4 + Pin L4 + [4:4] + + + PL5 + Pin L5 + [5:5] + + + PL6 + Pin L6 + [6:6] + + + PL7 + Pin L7 + [7:7] + + + + + PORTL + PORT L Data Register + 0x2 + + + PL0 + Pin L0 + [0:0] + + + PL1 + Pin L1 + [1:1] + + + PL2 + Pin L2 + [2:2] + + + PL3 + Pin L3 + [3:3] + + + PL4 + Pin L4 + [4:4] + + + PL5 + Pin L5 + [5:5] + + + PL6 + Pin L6 + [6:6] + + + PL7 + Pin L7 + [7:7] + + + + + + + SPI + Serial Peripheral Interface + 0x4C + + + SPCR + SPI Control Register + 0x0 + + + SPR + SPI Clock Rate Selects + [1:0] + + true + + SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 + + + CPHA + Clock Phase + [2:2] + + + CPOL + Clock polarity + [3:3] + + + MSTR + Master/Slave Select + [4:4] + + + DORD + Data Order + [5:5] + + + SPE + SPI Enable + [6:6] + + + SPIE + SPI Interrupt Enable + [7:7] + + + + + SPDR + SPI Data Register + 0x2 + + + 0 + 255 + + + + + SPSR + SPI Status Register + 0x1 + read-write + + + SPI2X + Double SPI Speed Bit + [0:0] + read-write + + WCOL + Write Collision Flag + [6:6] + read-only + + SPIF + SPI Interrupt Flag + [7:7] + read-only + + + + + + TC0 + Timer/Counter, 8-bit + 0x35 + + + GTCCR + General Timer/Counter Control Register + 0xE + + + PSRSYNC + Prescaler Reset Timer/Counter1 and Timer/Counter0 + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + OCR0A + Timer/Counter0 Output Compare Register + 0x12 + + + 0 + 255 + + + + + OCR0B + Timer/Counter0 Output Compare Register + 0x13 + + + 0 + 255 + + + + + TCCR0A + Timer/Counter Control Register A + 0xF + + + WGM0 + Waveform Generation Mode + [1:0] + + true + WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 + + + COM0B + Compare Output B Mode + [5:4] + + true + COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 + + + COM0A + Compare Output A Mode + [7:6] + + true + + + + + + TCCR0B + Timer/Counter Control Register B + 0x10 + + + CS0 + Clock Select + [2:0] + + true + + CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM02 + Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) + [3:3] + + + FOC0B + Force Output Compare B + [6:6] + write-only + + FOC0A + Force Output Compare A + [7:7] + write-only + + + + TCNT0 + Timer/Counter0 + 0x11 + + + 0 + 255 + + + + + TIFR0 + Timer/Counter0 Interrupt Flag register + 0x0 + read-write + + + TOV0 + Timer/Counter0 Overflow Flag + [0:0] + + + OCF0A + Timer/Counter0 Output Compare Flag 0A + [1:1] + + + OCF0B + Timer/Counter0 Output Compare Flag 0B + [2:2] + + + + + TIMSK0 + Timer/Counter0 Interrupt Mask Register + 0x39 + + + TOIE0 + Timer/Counter0 Overflow Interrupt Enable + [0:0] + + + OCIE0A + Timer/Counter0 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE0B + Timer/Counter0 Output Compare Match B Interrupt Enable + [2:2] + + + + + + + TC1 + Timer/Counter, 16-bit + 0x36 + + + ICR1 + Timer/Counter1 Input Capture Register Bytes + 0x50 + 16 + + + 0 + 65535 + + + + + OCR1A + Timer/Counter1 Output Compare Register A Bytes + 0x52 + 16 + + + 0 + 65535 + + + + + OCR1B + Timer/Counter1 Output Compare Register B Bytes + 0x54 + 16 + + + 0 + 65535 + + + + + OCR1C + Timer/Counter1 Output Compare Register C Bytes + 0x56 + 16 + + + 0 + 65535 + + + + + TCCR1A + Timer/Counter1 Control Register A + 0x4A + + + WGM1 + Waveform Generation Mode + [1:0] + + + 0 + 3 + + + + + COM1C + Compare Output Mode 1C, bits + [3:2] + + true + COM1Cread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM1B + Compare Output Mode 1B, bits + [5:4] + + true + + + + COM1A + Compare Output Mode 1A, bits + [7:6] + + true + + + + + + TCCR1B + Timer/Counter1 Control Register B + 0x4B + + + CS1 + Prescaler source of Timer/Counter 1 + [2:0] + + true + CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM1 + Waveform Generation Mode + [4:3] + + + 0 + 3 + + + + + ICES1 + Input Capture 1 Edge Select + [6:6] + + + ICNC1 + Input Capture 1 Noise Canceler + [7:7] + + + + + TCCR1C + Timer/Counter 1 Control Register C + 0x4C + + + FOC1C + Force Output Compare 1C + [5:5] + write-only + + FOC1B + Force Output Compare 1B + [6:6] + write-only + + FOC1A + Force Output Compare 1A + [7:7] + write-only + + + + TCNT1 + Timer/Counter1 Bytes + 0x4E + 16 + + + 0 + 65535 + + + + + TIFR1 + Timer/Counter1 Interrupt Flag register + 0x0 + read-write + + + TOV1 + Timer/Counter1 Overflow Flag + [0:0] + + + OCF1A + Output Compare Flag 1A + [1:1] + + + OCF1B + Output Compare Flag 1B + [2:2] + + + OCF1C + Output Compare Flag 1C + [3:3] + + + ICF1 + Input Capture Flag 1 + [5:5] + + + + + TIMSK1 + Timer/Counter1 Interrupt Mask Register + 0x39 + + + TOIE1 + Timer/Counter1 Overflow Interrupt Enable + [0:0] + + + OCIE1A + Timer/Counter1 Output Compare A Match Interrupt Enable + [1:1] + + + OCIE1B + Timer/Counter1 Output Compare B Match Interrupt Enable + [2:2] + + + OCIE1C + Timer/Counter1 Output Compare C Match Interrupt Enable + [3:3] + + + ICIE1 + Timer/Counter1 Input Capture Interrupt Enable + [5:5] + + + + + + + TC2 + Timer/Counter, 8-bit Async + 0x37 + + + ASSR + Asynchronous Status Register + 0x7F + + + TCR2BUB + Timer/Counter Control Register2 Update Busy + [0:0] + + + TCR2AUB + Timer/Counter Control Register2 Update Busy + [1:1] + + + OCR2BUB + Output Compare Register 2 Update Busy + [2:2] + + + OCR2AUB + Output Compare Register2 Update Busy + [3:3] + + + TCN2UB + Timer/Counter2 Update Busy + [4:4] + + + AS2 + Asynchronous Timer/Counter2 + [5:5] + + + EXCLK + Enable External Clock Input + [6:6] + + + + + GTCCR + General Timer Counter Control register + 0xC + + + PSRASY + Prescaler Reset Timer/Counter2 + [1:1] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + OCR2A + Timer/Counter2 Output Compare Register A + 0x7C + + + 0 + 255 + + + + + OCR2B + Timer/Counter2 Output Compare Register B + 0x7D + + + 0 + 255 + + + + + TCCR2A + Timer/Counter2 Control Register A + 0x79 + + + WGM2 + Waveform Genration Mode + [1:0] + + true + WGM2read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 + + + COM2B + Compare Output B Mode + [5:4] + + true + COM2Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 + + + COM2A + Compare Output A Mode + [7:6] + + true + + + + + + TCCR2B + Timer/Counter2 Control Register B + 0x7A + + + CS2 + Clock Select bits + [2:0] + + true + + CS2read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_32Running, CLK/323PRESCALE_64Running, CLK/644PRESCALE_128Running, CLK/1285PRESCALE_256Running, CLK/2566PRESCALE_1024Running, CLK/10247 + + + WGM22 + Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) + [3:3] + + + FOC2B + Force Output Compare B + [6:6] + write-only + + FOC2A + Force Output Compare A + [7:7] + write-only + + + + TCNT2 + Timer/Counter2 + 0x7B + + + 0 + 255 + + + + + TIFR2 + Timer/Counter Interrupt Flag Register + 0x0 + read-write + + + TOV2 + Timer/Counter2 Overflow Flag + [0:0] + + + OCF2A + Output Compare Flag 2A + [1:1] + + + OCF2B + Output Compare Flag 2B + [2:2] + + + + + TIMSK2 + Timer/Counter Interrupt Mask register + 0x39 + + + TOIE2 + Timer/Counter2 Overflow Interrupt Enable + [0:0] + + + OCIE2A + Timer/Counter2 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE2B + Timer/Counter2 Output Compare Match B Interrupt Enable + [2:2] + + + + + + + TC3 + Timer/Counter, 16-bit + 0x38 + + + ICR3 + Timer/Counter3 Input Capture Register Bytes + 0x5E + 16 + + + 0 + 65535 + + + + + OCR3A + Timer/Counter3 Output Compare Register A Bytes + 0x60 + 16 + + + 0 + 65535 + + + + + OCR3B + Timer/Counter3 Output Compare Register B Bytes + 0x62 + 16 + + + 0 + 65535 + + + + + OCR3C + Timer/Counter3 Output Compare Register B Bytes + 0x64 + 16 + + + 0 + 65535 + + + + + TCCR3A + Timer/Counter3 Control Register A + 0x58 + + + WGM3 + Waveform Generation Mode + [1:0] + + + 0 + 3 + + + + + COM3C + Compare Output Mode 3C, bits + [3:2] + + true + COM3Cread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM3B + Compare Output Mode 3B, bits + [5:4] + + true + + + + COM3A + Compare Output Mode 1A, bits + [7:6] + + true + + + + + + TCCR3B + Timer/Counter3 Control Register B + 0x59 + + + CS3 + Prescaler source of Timer/Counter 3 + [2:0] + + true + CS3read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM3 + Waveform Generation Mode + [4:3] + + + 0 + 3 + + + + + ICES3 + Input Capture 3 Edge Select + [6:6] + + + ICNC3 + Input Capture 3 Noise Canceler + [7:7] + + + + + TCCR3C + Timer/Counter 3 Control Register C + 0x5A + + + FOC3C + Force Output Compare 3C + [5:5] + write-only + + FOC3B + Force Output Compare 3B + [6:6] + write-only + + FOC3A + Force Output Compare 3A + [7:7] + write-only + + + + TCNT3 + Timer/Counter3 Bytes + 0x5C + 16 + + + 0 + 65535 + + + + + TIFR3 + Timer/Counter3 Interrupt Flag register + 0x0 + read-write + + + TOV3 + Timer/Counter3 Overflow Flag + [0:0] + + + OCF3A + Output Compare Flag 3A + [1:1] + + + OCF3B + Output Compare Flag 3B + [2:2] + + + OCF3C + Output Compare Flag 3C + [3:3] + + + ICF3 + Input Capture Flag 3 + [5:5] + + + + + TIMSK3 + Timer/Counter3 Interrupt Mask Register + 0x39 + + + TOIE3 + Timer/Counter3 Overflow Interrupt Enable + [0:0] + + + OCIE3A + Timer/Counter3 Output Compare A Match Interrupt Enable + [1:1] + + + OCIE3B + Timer/Counter3 Output Compare B Match Interrupt Enable + [2:2] + + + OCIE3C + Timer/Counter3 Output Compare C Match Interrupt Enable + [3:3] + + + ICIE3 + Timer/Counter3 Input Capture Interrupt Enable + [5:5] + + + + + + + TC4 + Timer/Counter, 16-bit + 0x39 + + + ICR4 + Timer/Counter4 Input Capture Register Bytes + 0x6D + 16 + + + 0 + 65535 + + + + + OCR4A + Timer/Counter4 Output Compare Register A Bytes + 0x6F + 16 + + + 0 + 65535 + + + + + OCR4B + Timer/Counter4 Output Compare Register B Bytes + 0x71 + 16 + + + 0 + 65535 + + + + + OCR4C + Timer/Counter4 Output Compare Register B Bytes + 0x73 + 16 + + + 0 + 65535 + + + + + TCCR4A + Timer/Counter4 Control Register A + 0x67 + + + WGM4 + Waveform Generation Mode + [1:0] + + + 0 + 3 + + + + + COM4C + Compare Output Mode 4C, bits + [3:2] + + true + COM4Cread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM4B + Compare Output Mode 4B, bits + [5:4] + + true + + + + COM4A + Compare Output Mode 1A, bits + [7:6] + + true + + + + + + TCCR4B + Timer/Counter4 Control Register B + 0x68 + + + CS4 + Prescaler source of Timer/Counter 4 + [2:0] + + true + CS4read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM4 + Waveform Generation Mode + [4:3] + + + 0 + 3 + + + + + ICES4 + Input Capture 4 Edge Select + [6:6] + + + ICNC4 + Input Capture 4 Noise Canceler + [7:7] + + + + + TCCR4C + Timer/Counter 4 Control Register C + 0x69 + + + FOC4C + Force Output Compare 4C + [5:5] + write-only + + FOC4B + Force Output Compare 4B + [6:6] + write-only + + FOC4A + Force Output Compare 4A + [7:7] + write-only + + + + TCNT4 + Timer/Counter4 Bytes + 0x6B + 16 + + + 0 + 65535 + + + + + TIFR4 + Timer/Counter4 Interrupt Flag register + 0x0 + read-write + + TOV4 + Timer/Counter4 Overflow Flag + [0:0] + + + OCF4A + Output Compare Flag 4A + [1:1] + + + OCF4B + Output Compare Flag 4B + [2:2] + + + OCF4C + Output Compare Flag 4C + [3:3] + + + ICF4 + Input Capture Flag 4 + [5:5] + + + + + TIMSK4 + Timer/Counter4 Interrupt Mask Register + 0x39 + + + TOIE4 + Timer/Counter4 Overflow Interrupt Enable + [0:0] + + + OCIE4A + Timer/Counter4 Output Compare A Match Interrupt Enable + [1:1] + + + OCIE4B + Timer/Counter4 Output Compare B Match Interrupt Enable + [2:2] + + + OCIE4C + Timer/Counter4 Output Compare C Match Interrupt Enable + [3:3] + + + ICIE4 + Timer/Counter4 Input Capture Interrupt Enable + [5:5] + + + + + + + TC5 + Timer/Counter, 16-bit + 0x3A + + + ICR5 + Timer/Counter5 Input Capture Register Bytes + 0xEC + 16 + + + 0 + 65535 + + + + + OCR5A + Timer/Counter5 Output Compare Register A Bytes + 0xEE + 16 + + + 0 + 65535 + + + + + OCR5B + Timer/Counter5 Output Compare Register B Bytes + 0xF0 + 16 + + + 0 + 65535 + + + + + OCR5C + Timer/Counter5 Output Compare Register B Bytes + 0xF2 + 16 + + + 0 + 65535 + + + + + TCCR5A + Timer/Counter5 Control Register A + 0xE6 + + + WGM5 + Waveform Generation Mode + [1:0] + + + 0 + 3 + + + + + COM5C + Compare Output Mode 5C, bits + [3:2] + + true + COM5Cread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM5B + Compare Output Mode 5B, bits + [5:4] + + true + + + + COM5A + Compare Output Mode 1A, bits + [7:6] + + true + + + + + + TCCR5B + Timer/Counter5 Control Register B + 0xE7 + + + CS5 + Prescaler source of Timer/Counter 5 + [2:0] + + true + CS5read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM5 + Waveform Generation Mode + [4:3] + + + 0 + 3 + + + + + ICES5 + Input Capture 5 Edge Select + [6:6] + + + ICNC5 + Input Capture 5 Noise Canceler + [7:7] + + + + + TCCR5C + Timer/Counter 5 Control Register C + 0xE8 + + + FOC5C + Force Output Compare 5C + [5:5] + write-only + + FOC5B + Force Output Compare 5B + [6:6] + write-only + + FOC5A + Force Output Compare 5A + [7:7] + write-only + + + + TCNT5 + Timer/Counter5 Bytes + 0xEA + 16 + + + 0 + 65535 + + + + + TIFR5 + Timer/Counter5 Interrupt Flag register + 0x0 + read-write + + TOV5 + Timer/Counter5 Overflow Flag + [0:0] + + + OCF5A + Output Compare Flag 5A + [1:1] + + + OCF5B + Output Compare Flag 5B + [2:2] + + + OCF5C + Output Compare Flag 5C + [3:3] + + + ICF5 + Input Capture Flag 5 + [5:5] + + + + + TIMSK5 + Timer/Counter5 Interrupt Mask Register + 0x39 + + + TOIE5 + Timer/Counter5 Overflow Interrupt Enable + [0:0] + + + OCIE5A + Timer/Counter5 Output Compare A Match Interrupt Enable + [1:1] + + + OCIE5B + Timer/Counter5 Output Compare B Match Interrupt Enable + [2:2] + + + OCIE5C + Timer/Counter5 Output Compare C Match Interrupt Enable + [3:3] + + + ICIE5 + Timer/Counter5 Input Capture Interrupt Enable + [5:5] + + + + + + + TWI + Two Wire Serial Interface + 0xB8 + + + TWAMR + TWI (Slave) Address Mask Register + 0x5 + + + TWAM + TWI (Slave) Address Mask Bits + [7:1] + + + 0 + 127 + + + + + + + TWAR + TWI (Slave) Address register + 0x2 + + + TWGCE + TWI General Call Recognition Enable Bit + [0:0] + + + TWA + TWI (Slave) Address register Bits + [7:1] + + + 0 + 127 + + + + + + + TWBR + TWI Bit Rate register + 0x0 + + + 0 + 255 + + + + + TWCR + TWI Control Register + 0x4 + read-write + + + TWIE + TWI Interrupt Enable + [0:0] + + + TWEN + TWI Enable Bit + [2:2] + + + TWWC + TWI Write Collition Flag + [3:3] + read-only + + TWSTO + TWI Stop Condition Bit + [4:4] + + + TWSTA + TWI Start Condition Bit + [5:5] + + + TWEA + TWI Enable Acknowledge Bit + [6:6] + + + TWINT + TWI Interrupt Flag + [7:7] + + + + + TWDR + TWI Data register + 0x3 + + + 0 + 255 + + + + + TWSR + TWI Status Register + 0x1 + + + TWPS + TWI Prescaler + [1:0] + + true + + TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 + + + TWS + TWI Status + [7:3] + read-only + + 0 + 31 + + + + + + + + + USART0 + USART + 0xC0 + + + UBRR0 + USART Baud Rate Register Bytes + 0x4 + 16 + + + 0 + 65535 + + + + + UCSR0A + USART Control and Status Register A + 0x0 + read-write + + + MPCM0 + Multi-processor Communication Mode + [0:0] + + + U2X0 + Double the USART transmission speed + [1:1] + + + UPE0 + Parity Error + [2:2] + read-only + + DOR0 + Data overRun + [3:3] + read-only + + FE0 + Framing Error + [4:4] + read-only + + UDRE0 + USART Data Register Empty + [5:5] + read-only + + TXC0 + USART Transmit Complete + [6:6] + + + RXC0 + USART Receive Complete + [7:7] + read-only + + + + UCSR0B + USART Control and Status Register B + 0x1 + + + TXB80 + Transmit Data Bit 8 + [0:0] + + + RXB80 + Receive Data Bit 8 + [1:1] + read-only + + UCSZ02 + Character Size + [2:2] + + + TXEN0 + Transmitter Enable + [3:3] + + + RXEN0 + Receiver Enable + [4:4] + + + UDRIE0 + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE0 + TX Complete Interrupt Enable + [6:6] + + + RXCIE0 + RX Complete Interrupt Enable + [7:7] + + + + + UCSR0C + USART Control and Status Register C + 0x2 + + + UCPOL0 + Clock Polarity + [0:0] + UCPOL0read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 + + + UCSZ0 + Character Size + [2:1] + + + 0 + 3 + + + UCSZ0read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 + + + USBS0 + Stop Bit Select + [3:3] + + true + + USBS0read-writeSTOP11-bit0STOP22-bit1 + + + UPM0 + Parity Mode Bits + [5:4] + + true + + UPM0read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 + + + UMSEL0 + USART Mode Select + [7:6] + + true + + UMSEL0read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 + + + + + UDR0 + USART I/O Data Register + 0x6 + + + 0 + 255 + + + + + + + USART1 + USART + 0xC8 + + + UBRR1 + USART Baud Rate Register Bytes + 0x4 + 16 + + + 0 + 65535 + + + + + UCSR1A + USART Control and Status Register A + 0x0 + read-write + + + MPCM1 + Multi-processor Communication Mode + [0:0] + + + U2X1 + Double the USART transmission speed + [1:1] + + + UPE1 + Parity Error + [2:2] + read-only + + DOR1 + Data overRun + [3:3] + read-only + + FE1 + Framing Error + [4:4] + read-only + + UDRE1 + USART Data Register Empty + [5:5] + read-only + + TXC1 + USART Transmit Complete + [6:6] + + + RXC1 + USART Receive Complete + [7:7] + read-only + + + + UCSR1B + USART Control and Status Register B + 0x1 + + + TXB81 + Transmit Data Bit 8 + [0:0] + + + RXB81 + Receive Data Bit 8 + [1:1] + read-only + + UCSZ12 + Character Size + [2:2] + + + TXEN1 + Transmitter Enable + [3:3] + + + RXEN1 + Receiver Enable + [4:4] + + + UDRIE1 + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE1 + TX Complete Interrupt Enable + [6:6] + + + RXCIE1 + RX Complete Interrupt Enable + [7:7] + + + + + UCSR1C + USART Control and Status Register C + 0x2 + + + UCPOL1 + Clock Polarity + [0:0] + UCPOL1read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 + + + UCSZ1 + Character Size + [2:1] + + + 0 + 3 + + + UCSZ1read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 + + + USBS1 + Stop Bit Select + [3:3] + + true + + USBS1read-writeSTOP11-bit0STOP22-bit1 + + + UPM1 + Parity Mode Bits + [5:4] + + true + + UPM1read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 + + + UMSEL1 + USART Mode Select + [7:6] + + true + + UMSEL1read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 + + + + + UDR1 + USART I/O Data Register + 0x6 + + + 0 + 255 + + + + + + + USART2 + USART + 0xD0 + + + UBRR2 + USART Baud Rate Register Bytes + 0x4 + 16 + + + 0 + 65535 + + + + + UCSR2A + USART Control and Status Register A + 0x0 + read-write + + + MPCM2 + Multi-processor Communication Mode + [0:0] + + + U2X2 + Double the USART transmission speed + [1:1] + + + UPE2 + Parity Error + [2:2] + read-only + + DOR2 + Data overRun + [3:3] + read-only + + FE2 + Framing Error + [4:4] + read-only + + UDRE2 + USART Data Register Empty + [5:5] + read-only + + TXC2 + USART Transmit Complete + [6:6] + + + RXC2 + USART Receive Complete + [7:7] + read-only + + + + UCSR2B + USART Control and Status Register B + 0x1 + + + TXB82 + Transmit Data Bit 8 + [0:0] + + + RXB82 + Receive Data Bit 8 + [1:1] + read-only + + UCSZ22 + Character Size + [2:2] + + + TXEN2 + Transmitter Enable + [3:3] + + + RXEN2 + Receiver Enable + [4:4] + + + UDRIE2 + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE2 + TX Complete Interrupt Enable + [6:6] + + + RXCIE2 + RX Complete Interrupt Enable + [7:7] + + + + + UCSR2C + USART Control and Status Register C + 0x2 + + + UCPOL2 + Clock Polarity + [0:0] + UCPOL2read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 + + + UCSZ2 + Character Size + [2:1] + + + 0 + 3 + + + UCSZ2read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 + + + USBS2 + Stop Bit Select + [3:3] + + true + + USBS2read-writeSTOP11-bit0STOP22-bit1 + + + UPM2 + Parity Mode Bits + [5:4] + + true + + UPM2read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 + + + UMSEL2 + USART Mode Select + [7:6] + + true + + UMSEL2read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 + + + + + UDR2 + USART I/O Data Register + 0x6 + + + 0 + 255 + + + + + + + USART3 + USART + 0x130 + + + UBRR3 + USART Baud Rate Register Bytes + 0x4 + 16 + + + 0 + 65535 + + + + + UCSR3A + USART Control and Status Register A + 0x0 + read-write + + + MPCM3 + Multi-processor Communication Mode + [0:0] + + + U2X3 + Double the USART transmission speed + [1:1] + + + UPE3 + Parity Error + [2:2] + read-only + + DOR3 + Data overRun + [3:3] + read-only + + FE3 + Framing Error + [4:4] + read-only + + UDRE3 + USART Data Register Empty + [5:5] + read-only + + TXC3 + USART Transmit Complete + [6:6] + + + RXC3 + USART Receive Complete + [7:7] + read-only + + + + UCSR3B + USART Control and Status Register B + 0x1 + + + TXB83 + Transmit Data Bit 8 + [0:0] + + + RXB83 + Receive Data Bit 8 + [1:1] + read-only + + UCSZ32 + Character Size + [2:2] + + + TXEN3 + Transmitter Enable + [3:3] + + + RXEN3 + Receiver Enable + [4:4] + + + UDRIE3 + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE3 + TX Complete Interrupt Enable + [6:6] + + + RXCIE3 + RX Complete Interrupt Enable + [7:7] + + + + + UCSR3C + USART Control and Status Register C + 0x2 + + + UCPOL3 + Clock Polarity + [0:0] + UCPOL3read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 + + + UCSZ3 + Character Size + [2:1] + + + 0 + 3 + + + UCSZ3read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 + + + USBS3 + Stop Bit Select + [3:3] + + true + + USBS3read-writeSTOP11-bit0STOP22-bit1 + + + UPM3 + Parity Mode Bits + [5:4] + + true + + UPM3read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 + + + UMSEL3 + USART Mode Select + [7:6] + + true + + UMSEL3read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 + + + + + UDR3 + USART I/O Data Register + 0x6 + + + 0 + 255 + + + + + + + WDT + Watchdog Timer + 0x60 + + + WDTCSR + Watchdog Timer Control Register + 0x0 + read-write + + + WDE + Watch Dog Enable + [3:3] + + + WDCE + Watchdog Change Enable + [4:4] + + + WDIE + Watchdog Timeout Interrupt Enable + [6:6] + + + WDIF + Watchdog Timeout Interrupt Flag + [7:7] + + WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 + + WDPHWatchdog Timer Prescaler - High Bit[5:5] + + + + + + \ No newline at end of file diff --git a/misc/svd/atmega328p.svd b/misc/svd/atmega328p.svd new file mode 100644 index 0000000..b169013 --- /dev/null +++ b/misc/svd/atmega328p.svd @@ -0,0 +1,3040 @@ + + + Atmel + ATmega328P + 8 + 8 + read-write + 0 + 0xff + + + AC + Analog Comparator + 0x50 + + + ACSR + Analog Comparator Control And Status Register + 0x0 + read-write + + + ACIS + Analog Comparator Interrupt Mode Select + [1:0] + + true + + ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 + + + ACIC + Analog Comparator Input Capture Enable + [2:2] + + + ACIE + Analog Comparator Interrupt Enable + [3:3] + + + ACI + Analog Comparator Interrupt Flag + [4:4] + + + ACO + Analog Compare Output + [5:5] + read-only + + ACBG + Analog Comparator Bandgap Select + [6:6] + + + ACD + Analog Comparator Disable + [7:7] + + + + + DIDR1 + Digital Input Disable Register 1 + 0x2F + + + AIN0D + AIN0 Digital Input Disable + [0:0] + + + AIN1D + AIN1 Digital Input Disable + [1:1] + + + + + + + ADC + Analog-to-Digital Converter + 0x78 + + + ADC + ADC Data Register Bytes + 0x0 + 16 + + + 0 + 65535 + + + + + ADCSRA + The ADC Control and Status register A + 0x2 + read-write + + + ADPS + ADC Prescaler Select Bits + [2:0] + + true + + ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 + + + ADIE + ADC Interrupt Enable + [3:3] + + + ADIF + ADC Interrupt Flag + [4:4] + + + ADATE + ADC Auto Trigger Enable + [5:5] + + + ADSC + ADC Start Conversion + [6:6] + + + ADEN + ADC Enable + [7:7] + + + + + ADCSRB + The ADC Control and Status register B + 0x3 + + + ADTS + ADC Auto Trigger Source bits + [2:0] + + true + + + + VAL_0x00 + Free Running mode + 0 + + + VAL_0x01 + Analog Comparator + 1 + + + VAL_0x02 + External Interrupt Request 0 + 2 + + + VAL_0x03 + Timer/Counter0 Compare Match A + 3 + + + VAL_0x04 + Timer/Counter0 Overflow + 4 + + + VAL_0x05 + Timer/Counter1 Compare Match B + 5 + + + VAL_0x06 + Timer/Counter1 Overflow + 6 + + + VAL_0x07 + Timer/Counter1 Capture Event + 7 + + + + + ACME + <TBD> + [6:6] + + + + + ADMUX + The ADC multiplexer Selection Register + 0x4 + + + MUX + Analog Channel Selection Bits + [3:0] + + true + + + + ADC0 + ADC Single Ended Input pin 0 + 0 + + + ADC1 + ADC Single Ended Input pin 1 + 1 + + + ADC2 + ADC Single Ended Input pin 2 + 2 + + + ADC3 + ADC Single Ended Input pin 3 + 3 + + + ADC4 + ADC Single Ended Input pin 4 + 4 + + + ADC5 + ADC Single Ended Input pin 5 + 5 + + + ADC6 + ADC Single Ended Input pin 6 + 6 + + + ADC7 + ADC Single Ended Input pin 7 + 7 + + + TEMPSENS + Temperature sensor + 8 + + + ADC_VBG + Internal Reference (VBG) + 14 + + + ADC_GND + 0V (GND) + 15 + + + + + ADLAR + Left Adjust Result + [5:5] + + + REFS + Reference Selection Bits + [7:6] + + true + + REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 + + + + + DIDR0 + Digital Input Disable Register + 0x6 + + + ADC0D + <TBD> + [0:0] + + + ADC1D + <TBD> + [1:1] + + + ADC2D + <TBD> + [2:2] + + + ADC3D + <TBD> + [3:3] + + + ADC4D + <TBD> + [4:4] + + + ADC5D + <TBD> + [5:5] + + + + + + + CPU + CPU Registers + 0x3E + + RESET + External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + 0 + + + INT0 + External Interrupt Request 0 + 1 + + + INT1 + External Interrupt Request 1 + 2 + + + PCINT0 + Pin Change Interrupt Request 0 + 3 + + + PCINT1 + Pin Change Interrupt Request 1 + 4 + + + PCINT2 + Pin Change Interrupt Request 2 + 5 + + + WDT + Watchdog Time-out Interrupt + 6 + + + TIMER2_COMPA + Timer/Counter2 Compare Match A + 7 + + + TIMER2_COMPB + Timer/Counter2 Compare Match B + 8 + + + TIMER2_OVF + Timer/Counter2 Overflow + 9 + + + TIMER1_CAPT + Timer/Counter1 Capture Event + 10 + + + TIMER1_COMPA + Timer/Counter1 Compare Match A + 11 + + + TIMER1_COMPB + Timer/Counter1 Compare Match B + 12 + + + TIMER1_OVF + Timer/Counter1 Overflow + 13 + + + TIMER0_COMPA + TimerCounter0 Compare Match A + 14 + + + TIMER0_COMPB + TimerCounter0 Compare Match B + 15 + + + TIMER0_OVF + Timer/Couner0 Overflow + 16 + + + SPI_STC + SPI Serial Transfer Complete + 17 + + + USART_RX + USART Rx Complete + 18 + + + USART_UDRE + USART, Data Register Empty + 19 + + + USART_TX + USART Tx Complete + 20 + + + ADC + ADC Conversion Complete + 21 + + + EE_READY + EEPROM Ready + 22 + + + ANALOG_COMP + Analog Comparator + 23 + + + TWI + Two-wire Serial Interface + 24 + + + SPM_Ready + Store Program Memory Read + 25 + + + + CLKPR + Clock Prescale Register + 0x23 + read-only + + + CLKPS + Clock Prescaler Select Bits + [3:0] + + true + + + + VAL_0x00 + 1 + 0 + + + VAL_0x01 + 2 + 1 + + + VAL_0x02 + 4 + 2 + + + VAL_0x03 + 8 + 3 + + + VAL_0x04 + 16 + 4 + + + VAL_0x05 + 32 + 5 + + + VAL_0x06 + 64 + 6 + + + VAL_0x07 + 128 + 7 + + + VAL_0x08 + 256 + 8 + + + + + CLKPCE + Clock Prescaler Change Enable + [7:7] + + + + + GPIOR0 + General Purpose I/O Register 0 + 0x0 + + + 0 + 255 + + + + + GPIOR1 + General Purpose I/O Register 1 + 0xC + + + 0 + 255 + + + + + GPIOR2 + General Purpose I/O Register 2 + 0xD + + + 0 + 255 + + + + + MCUCR + MCU Control Register + 0x17 + + + IVCE + <TBD> + [0:0] + + + IVSEL + <TBD> + [1:1] + + + PUD + <TBD> + [4:4] + + + BODSE + BOD Sleep Enable + [5:5] + + + BODS + BOD Sleep + [6:6] + + + + + MCUSR + MCU Status Register + 0x16 + + + PORF + Power-on reset flag + [0:0] + + + EXTRF + External Reset Flag + [1:1] + + + BORF + Brown-out Reset Flag + [2:2] + + + WDRF + Watchdog Reset Flag + [3:3] + + + + + OSCCAL + Oscillator Calibration Value + 0x28 + read-only + + + OSCCAL + Oscillator Calibration + [7:0] + + + 0 + 255 + + + + + + + PRR + Power Reduction Register + 0x26 + read-write + + + PRADC + Power Reduction ADC + [0:0] + + + PRUSART0 + Power Reduction USART + [1:1] + + + PRSPI + Power Reduction Serial Peripheral Interface + [2:2] + + + PRTIM1 + Power Reduction Timer/Counter1 + [3:3] + + + PRTIM0 + Power Reduction Timer/Counter0 + [5:5] + + + PRTIM2 + Power Reduction Timer/Counter2 + [6:6] + + + PRTWI + Power Reduction TWI + [7:7] + + + + + SMCR + Sleep Mode Control Register + 0x15 + + + SE + Sleep Enable + [0:0] + + + SM + Sleep Mode Select Bits + [3:1] + + true + + + + IDLE + Idle + 0 + + + ADC + ADC Noise Reduction (If Available) + 1 + + + PDOWN + Power Down + 2 + + + PSAVE + Power Save + 3 + + + VAL_0x04 + Reserved + 4 + + + VAL_0x05 + Reserved + 5 + + + STDBY + Standby + 6 + + + ESTDBY + Extended Standby + 7 + + + + + + + SPMCSR + Store Program Memory Control and Status Register + 0x19 + + + SPMEN + Store Program Memory + [0:0] + + + PGERS + Page Erase + [1:1] + + + PGWRT + Page Write + [2:2] + + + BLBSET + Boot Lock Bit Set + [3:3] + + + RWWSRE + Read-While-Write section read enable + [4:4] + + + SIGRD + Signature Row Read + [5:5] + + + RWWSB + Read-While-Write Section Busy + [6:6] + + + SPMIE + SPM Interrupt Enable + [7:7] + + + + + + + EEPROM + EEPROM + 0x3F + + + EEAR + EEPROM Address Register Bytes + 0x2 + 16 + + + 0 + 65535 + + + + + EECR + EEPROM Control Register + 0x0 + + + EERE + EEPROM Read Enable + [0:0] + + + EEPE + EEPROM Write Enable + [1:1] + + + EEMPE + EEPROM Master Write Enable + [2:2] + + + EERIE + EEPROM Ready Interrupt Enable + [3:3] + + + EEPM + EEPROM Programming Mode Bits + [5:4] + + true + + + + VAL_0x00 + Erase and Write in one operation + 0 + + + VAL_0x01 + Erase Only + 1 + + + VAL_0x02 + Write Only + 2 + + + + + + + EEDR + EEPROM Data Register + 0x1 + + + 0 + 255 + + + + + + + EXINT + External Interrupts + 0x3B + + + EICRA + External Interrupt Control Register + 0x2E + + + ISC0 + External Interrupt Sense Control 0 Bits + [1:0] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC1 + External Interrupt Sense Control 1 Bits + [3:2] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + + + EIFR + External Interrupt Flag Register + 0x1 + read-only + + + INTF + External Interrupt Flags + [1:0] + + + 0 + 3 + + + + + + + EIMSK + External Interrupt Mask Register + 0x2 + + INT0External Interrupt Request Enable01INT1External Interrupt Request Enable11 + + + PCICR + Pin Change Interrupt Control Register + 0x2D + + + PCIE + Pin Change Interrupt Enables + [2:0] + + + 0 + 7 + + + + + + + PCIFR + Pin Change Interrupt Flag Register + 0x0 + read-only + + + PCIF + Pin Change Interrupt Flags + [2:0] + + + 0 + 7 + + + + + + + PCMSK0 + Pin Change Mask Register 0 + 0x30 + + + PCINT + Pin Change Enable Masks + [7:0] + + + 0 + 255 + + + + + + + PCMSK1 + Pin Change Mask Register 1 + 0x31 + + + PCINT + Pin Change Enable Masks + [6:0] + + + 0 + 127 + + + + + + + PCMSK2 + Pin Change Mask Register 2 + 0x32 + + + PCINT + Pin Change Enable Masks + [7:0] + + + 0 + 255 + + + + + + + + + FUSE + Fuses + 0x0 + + + EXTENDED + <TBD> + 0x2 + + + BODLEVEL + Brown-out Detector trigger level + [2:0] + + true + + + + 4V3 + Brown-out detection at VCC=4.3 V + 4 + + + 2V7 + Brown-out detection at VCC=2.7 V + 5 + + + 1V8 + Brown-out detection at VCC=1.8 V + 6 + + + DISABLED + Brown-out detection disabled + 7 + + + + + + + HIGH + <TBD> + 0x1 + + + BOOTRST + Boot Reset vector Enabled + [0:0] + + + BOOTSZ + Select boot size + [2:1] + + true + + + + 2048W_3800 + Boot Flash size=2048 words start address=$3800 + 0 + + + 1024W_3C00 + Boot Flash size=1024 words start address=$3C00 + 1 + + + 512W_3E00 + Boot Flash size=512 words start address=$3E00 + 2 + + + 256W_3F00 + Boot Flash size=256 words start address=$3F00 + 3 + + + + + EESAVE + Preserve EEPROM through the Chip Erase cycle + [3:3] + + + WDTON + Watch-dog Timer always on + [4:4] + + + SPIEN + Serial program downloading (SPI) enabled + [5:5] + + + DWEN + Debug Wire enable + [6:6] + + + RSTDISBL + Reset Disabled (Enable PC6 as i/o pin) + [7:7] + + + + + LOW + <TBD> + 0x0 + + + SUT_CKSEL + Select Clock Source + [5:0] + + true + + + + EXTCLK_6CK_14CK_0MS + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 0 + + + INTRCOSC_8MHZ_6CK_14CK_0MS + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 2 + + + INTRCOSC_128KHZ_6CK_14CK_0MS + Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 3 + + + EXTLOFXTAL_1KCK_14CK_0MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms + 4 + + + EXTLOFXTAL_32KCK_14CK_0MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms + 5 + + + EXTFSXTAL_258CK_14CK_4MS1 + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 6 + + + EXTFSXTAL_1KCK_14CK_65MS + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 7 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 8 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 9 + + + EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 10 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 11 + + + EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 12 + + + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 13 + + + EXTXOSC_8MHZ_XX_258CK_14CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 14 + + + EXTXOSC_8MHZ_XX_1KCK_14CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 15 + + + EXTCLK_6CK_14CK_4MS1 + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + 16 + + + INTRCOSC_8MHZ_6CK_14CK_4MS1 + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + 18 + + + INTRCOSC_128KHZ_6CK_14CK_4MS1 + Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + 19 + + + EXTLOFXTAL_1KCK_14CK_4MS1 + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms + 20 + + + EXTLOFXTAL_32KCK_14CK_4MS1 + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms + 21 + + + EXTFSXTAL_258CK_14CK_65MS + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 22 + + + EXTFSXTAL_16KCK_14CK_0MS + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 23 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 24 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 25 + + + EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 26 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 27 + + + EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 28 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 29 + + + EXTXOSC_8MHZ_XX_258CK_14CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 30 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 31 + + + EXTCLK_6CK_14CK_65MS + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + 32 + + + INTRCOSC_8MHZ_6CK_14CK_65MS + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + 34 + + + INTRCOSC_128KHZ_6CK_14CK_65MS + Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + 35 + + + EXTLOFXTAL_1KCK_14CK_65MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms + 36 + + + EXTLOFXTAL_32KCK_14CK_65MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms + 37 + + + EXTFSXTAL_1KCK_14CK_0MS + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 38 + + + EXTFSXTAL_16KCK_14CK_4MS1 + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 39 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 40 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 41 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 42 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 43 + + + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 44 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 45 + + + EXTXOSC_8MHZ_XX_1KCK_14CK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 46 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 47 + + + EXTFSXTAL_1KCK_14CK_4MS1 + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 54 + + + EXTFSXTAL_16KCK_14CK_65MS + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 55 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 56 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 57 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 58 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 59 + + + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 60 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 61 + + + EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 62 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 63 + + + + + CKOUT + Clock output on PORTB0 + [6:6] + + + CKDIV8 + Divide clock by 8 internally + [7:7] + + + + + + + LOCKBIT + Lockbits + 0x0 + + + LOCKBIT + <TBD> + 0x0 + + + LB + Memory Lock + [1:0] + + true + + + + PROG_VER_DISABLED + Further programming and verification disabled + 0 + + + PROG_DISABLED + Further programming disabled + 2 + + + NO_LOCK + No memory lock features enabled + 3 + + + + + BLB0 + Boot Loader Protection Mode + [3:2] + + true + + + + LPM_SPM_DISABLE + LPM and SPM prohibited in Application Section + 0 + + + LPM_DISABLE + LPM prohibited in Application Section + 1 + + + SPM_DISABLE + SPM prohibited in Application Section + 2 + + + NO_LOCK + No lock on SPM and LPM in Application Section + 3 + + + + + BLB1 + Boot Loader Protection Mode + [5:4] + + true + + + + LPM_SPM_DISABLE + LPM and SPM prohibited in Boot Section + 0 + + + LPM_DISABLE + LPM prohibited in Boot Section + 1 + + + SPM_DISABLE + SPM prohibited in Boot Section + 2 + + + NO_LOCK + No lock on SPM and LPM in Boot Section + 3 + + + + + + + + + PORTB + I/O Port + 0x23 + + + DDRB + Port B Data Direction Register + 0x1 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PINB + Port B Input Pins + 0x0 + read-write + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PORTB + Port B Data Register + 0x2 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + + + PORTC + I/O Port + 0x26 + + + DDRC + Port C Data Direction Register + 0x1 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + + + PINC + Port C Input Pins + 0x0 + read-write + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + + + PORTC + Port C Data Register + 0x2 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + + + + + PORTD + I/O Port + 0x29 + + + DDRD + Port D Data Direction Register + 0x1 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PIND + Port D Input Pins + 0x0 + read-write + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PORTD + Port D Data Register + 0x2 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + + + SPI + Serial Peripheral Interface + 0x4C + + + SPCR + SPI Control Register + 0x0 + + + SPR + SPI Clock Rate Selects + [1:0] + + true + + SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 + + + CPHA + Clock Phase + [2:2] + + + CPOL + Clock polarity + [3:3] + + + MSTR + Master/Slave Select + [4:4] + + + DORD + Data Order + [5:5] + + + SPE + SPI Enable + [6:6] + + + SPIE + SPI Interrupt Enable + [7:7] + + + + + SPDR + SPI Data Register + 0x2 + + + 0 + 255 + + + + + SPSR + SPI Status Register + 0x1 + read-write + + + SPI2X + Double SPI Speed Bit + [0:0] + read-write + + WCOL + Write Collision Flag + [6:6] + read-only + + SPIF + SPI Interrupt Flag + [7:7] + read-only + + + + + + TC0 + Timer/Counter, 8-bit + 0x35 + + + GTCCR + General Timer/Counter Control Register + 0xE + + + PSRSYNC + Prescaler Reset Timer/Counter1 and Timer/Counter0 + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + OCR0A + Timer/Counter0 Output Compare Register + 0x12 + + + 0 + 255 + + + + + OCR0B + Timer/Counter0 Output Compare Register + 0x13 + + + 0 + 255 + + + + + TCCR0A + Timer/Counter Control Register A + 0xF + + + WGM0 + Waveform Generation Mode + [1:0] + + true + WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 + + + COM0B + Compare Output B Mode + [5:4] + + true + COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 + + + COM0A + Compare Output A Mode + [7:6] + + true + + + + + + TCCR0B + Timer/Counter Control Register B + 0x10 + + + CS0 + Clock Select + [2:0] + + true + + CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM02 + Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) + [3:3] + + + FOC0B + Force Output Compare B + [6:6] + write-only + + FOC0A + Force Output Compare A + [7:7] + write-only + + + + TCNT0 + Timer/Counter0 + 0x11 + + + 0 + 255 + + + + + TIFR0 + Timer/Counter0 Interrupt Flag register + 0x0 + read-write + + + TOV0 + Timer/Counter0 Overflow Flag + [0:0] + + + OCF0A + Timer/Counter0 Output Compare Flag 0A + [1:1] + + + OCF0B + Timer/Counter0 Output Compare Flag 0B + [2:2] + + + + + TIMSK0 + Timer/Counter0 Interrupt Mask Register + 0x39 + + + TOIE0 + Timer/Counter0 Overflow Interrupt Enable + [0:0] + + + OCIE0A + Timer/Counter0 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE0B + Timer/Counter0 Output Compare Match B Interrupt Enable + [2:2] + + + + + + + TC1 + Timer/Counter, 16-bit + 0x36 + + + GTCCR + General Timer/Counter Control Register + 0xD + + + PSRSYNC + Prescaler Reset Timer/Counter1 and Timer/Counter0 + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + ICR1 + Timer/Counter1 Input Capture Register Bytes + 0x50 + 16 + + + 0 + 65535 + + + + + OCR1A + Timer/Counter1 Output Compare Register Bytes + 0x52 + 16 + + + 0 + 65535 + + + + + OCR1B + Timer/Counter1 Output Compare Register Bytes + 0x54 + 16 + + + 0 + 65535 + + + + + TCCR1A + Timer/Counter1 Control Register A + 0x4A + + + WGM1 + Waveform Generation Mode + [1:0] + + + 0 + 3 + + + + + COM1B + Compare Output Mode 1B, bits + [5:4] + + true + COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM1A + Compare Output Mode 1A, bits + [7:6] + + true + + + + + + TCCR1B + Timer/Counter1 Control Register B + 0x4B + + + CS1 + Prescaler source of Timer/Counter 1 + [2:0] + + true + CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM1 + Waveform Generation Mode + [4:3] + + + 0 + 3 + + + + + ICES1 + Input Capture 1 Edge Select + [6:6] + + + ICNC1 + Input Capture 1 Noise Canceler + [7:7] + + + + + TCCR1C + Timer/Counter1 Control Register C + 0x4C + + + FOC1B + <TBD> + [6:6] + write-only + + FOC1A + <TBD> + [7:7] + write-only + + + + TCNT1 + Timer/Counter1 Bytes + 0x4E + 16 + + + 0 + 65535 + + + + + TIFR1 + Timer/Counter Interrupt Flag register + 0x0 + read-write + + + TOV1 + Timer/Counter1 Overflow Flag + [0:0] + + + OCF1A + Output Compare Flag 1A + [1:1] + + + OCF1B + Output Compare Flag 1B + [2:2] + + + ICF1 + Input Capture Flag 1 + [5:5] + + + + + TIMSK1 + Timer/Counter Interrupt Mask Register + 0x39 + + + TOIE1 + Timer/Counter1 Overflow Interrupt Enable + [0:0] + + + OCIE1A + Timer/Counter1 Output CompareA Match Interrupt Enable + [1:1] + + + OCIE1B + Timer/Counter1 Output CompareB Match Interrupt Enable + [2:2] + + + ICIE1 + Timer/Counter1 Input Capture Interrupt Enable + [5:5] + + + + + + + TC2 + Timer/Counter, 8-bit Async + 0x37 + + + ASSR + Asynchronous Status Register + 0x7F + + + TCR2BUB + Timer/Counter Control Register2 Update Busy + [0:0] + + + TCR2AUB + Timer/Counter Control Register2 Update Busy + [1:1] + + + OCR2BUB + Output Compare Register 2 Update Busy + [2:2] + + + OCR2AUB + Output Compare Register2 Update Busy + [3:3] + + + TCN2UB + Timer/Counter2 Update Busy + [4:4] + + + AS2 + Asynchronous Timer/Counter2 + [5:5] + + + EXCLK + Enable External Clock Input + [6:6] + + + + + GTCCR + General Timer Counter Control register + 0xC + + + PSRASY + Prescaler Reset Timer/Counter2 + [1:1] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + OCR2A + Timer/Counter2 Output Compare Register A + 0x7C + + + 0 + 255 + + + + + OCR2B + Timer/Counter2 Output Compare Register B + 0x7D + + + 0 + 255 + + + + + TCCR2A + Timer/Counter2 Control Register A + 0x79 + + + WGM2 + Waveform Genration Mode + [1:0] + + true + WGM2read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 + + + COM2B + Compare Output B Mode + [5:4] + + true + COM2Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 + + + COM2A + Compare Output A Mode + [7:6] + + true + + + + + + TCCR2B + Timer/Counter2 Control Register B + 0x7A + + + CS2 + Clock Select bits + [2:0] + + true + + CS2read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_32Running, CLK/323PRESCALE_64Running, CLK/644PRESCALE_128Running, CLK/1285PRESCALE_256Running, CLK/2566PRESCALE_1024Running, CLK/10247 + + + WGM22 + Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) + [3:3] + + + FOC2B + Force Output Compare B + [6:6] + write-only + + FOC2A + Force Output Compare A + [7:7] + write-only + + + + TCNT2 + Timer/Counter2 + 0x7B + + + 0 + 255 + + + + + TIFR2 + Timer/Counter Interrupt Flag Register + 0x0 + read-write + + + TOV2 + Timer/Counter2 Overflow Flag + [0:0] + + + OCF2A + Output Compare Flag 2A + [1:1] + + + OCF2B + Output Compare Flag 2B + [2:2] + + + + + TIMSK2 + Timer/Counter Interrupt Mask register + 0x39 + + + TOIE2 + Timer/Counter2 Overflow Interrupt Enable + [0:0] + + + OCIE2A + Timer/Counter2 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE2B + Timer/Counter2 Output Compare Match B Interrupt Enable + [2:2] + + + + + + + TWI + Two Wire Serial Interface + 0xB8 + + + TWAMR + TWI (Slave) Address Mask Register + 0x5 + + + TWAM + TWI (Slave) Address Mask Bits + [7:1] + + + 0 + 127 + + + + + + + TWAR + TWI (Slave) Address register + 0x2 + + + TWGCE + TWI General Call Recognition Enable Bit + [0:0] + + + TWA + TWI (Slave) Address register Bits + [7:1] + + + 0 + 127 + + + + + + + TWBR + TWI Bit Rate register + 0x0 + + + 0 + 255 + + + + + TWCR + TWI Control Register + 0x4 + read-write + + + TWIE + TWI Interrupt Enable + [0:0] + + + TWEN + TWI Enable Bit + [2:2] + + + TWWC + TWI Write Collition Flag + [3:3] + read-only + + TWSTO + TWI Stop Condition Bit + [4:4] + + + TWSTA + TWI Start Condition Bit + [5:5] + + + TWEA + TWI Enable Acknowledge Bit + [6:6] + + + TWINT + TWI Interrupt Flag + [7:7] + + + + + TWDR + TWI Data register + 0x3 + + + 0 + 255 + + + + + TWSR + TWI Status Register + 0x1 + + + TWPS + TWI Prescaler + [1:0] + + true + + TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 + + + TWS + TWI Status + [7:3] + read-only + + 0 + 31 + + + + + + + + + USART0 + USART + 0xC0 + + + UBRR0 + USART Baud Rate Register Bytes + 0x4 + 16 + + + 0 + 65535 + + + + + UCSR0A + USART Control and Status Register A + 0x0 + read-write + + + MPCM0 + Multi-processor Communication Mode + [0:0] + + + U2X0 + Double the USART transmission speed + [1:1] + + + UPE0 + Parity Error + [2:2] + read-only + + DOR0 + Data overRun + [3:3] + read-only + + FE0 + Framing Error + [4:4] + read-only + + UDRE0 + USART Data Register Empty + [5:5] + read-only + + TXC0 + USART Transmit Complete + [6:6] + + + RXC0 + USART Receive Complete + [7:7] + read-only + + + + UCSR0B + USART Control and Status Register B + 0x1 + + + TXB80 + Transmit Data Bit 8 + [0:0] + + + RXB80 + Receive Data Bit 8 + [1:1] + read-only + + UCSZ02 + Character Size + [2:2] + + + TXEN0 + Transmitter Enable + [3:3] + + + RXEN0 + Receiver Enable + [4:4] + + + UDRIE0 + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE0 + TX Complete Interrupt Enable + [6:6] + + + RXCIE0 + RX Complete Interrupt Enable + [7:7] + + + + + UCSR0C + USART Control and Status Register C + 0x2 + + + UCPOL0 + Clock Polarity + [0:0] + UCPOL0read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 + + + UCSZ0 + Character Size + [2:1] + + + 0 + 3 + + + UCSZ0read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 + + + USBS0 + Stop Bit Select + [3:3] + + true + + USBS0read-writeSTOP11-bit0STOP22-bit1 + + + UPM0 + Parity Mode Bits + [5:4] + + true + + UPM0read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 + + + UMSEL0 + USART Mode Select + [7:6] + + true + + UMSEL0read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 + + + + + UDR0 + USART I/O Data Register + 0x6 + + + 0 + 255 + + + + + + + WDT + Watchdog Timer + 0x60 + + + WDTCSR + Watchdog Timer Control Register + 0x0 + read-write + + + WDE + Watch Dog Enable + [3:3] + + + WDCE + Watchdog Change Enable + [4:4] + + + WDIE + Watchdog Timeout Interrupt Enable + [6:6] + + + WDIF + Watchdog Timeout Interrupt Flag + [7:7] + + WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 + + WDPHWatchdog Timer Prescaler - High Bit[5:5] + + + + + + \ No newline at end of file diff --git a/misc/svd/atmega328pb.svd b/misc/svd/atmega328pb.svd new file mode 100644 index 0000000..4d665ad --- /dev/null +++ b/misc/svd/atmega328pb.svd @@ -0,0 +1,4127 @@ + + Atmel + ATmega328PB + 8 + 8 + read-write + 0 + 0xff + + + AC + <TBD> + 0x4F + + + ACSR + Analog Comparator Control And Status Register + 0x1 + read-write + + + ACIS + Analog Comparator Interrupt Mode Select + [1:0] + + true + + ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 + + + ACIC + Analog Comparator Input Capture Enable + [2:2] + + + ACIE + Analog Comparator Interrupt Enable + [3:3] + + + ACI + Analog Comparator Interrupt Flag + [4:4] + + + ACO + Analog Compare Output + [5:5] + read-only + + ACBG + Analog Comparator Bandgap Select + [6:6] + + + ACD + Analog Comparator Disable + [7:7] + + + + + ACSRA + Analog Comparator Control And Status Register-A + 0x1 + read-only + + + 0 + 255 + + + + + ACSRB + Analog Comparator Control And Status Register-B + 0x0 + + + ACOE + Analog Comparator Output Enable + [0:0] + + + + + DIDR1 + Digital Input Disable Register 1 + 0x30 + + + AIN0D + AIN0 Digital Input Disable + [0:0] + + + AIN1D + AIN1 Digital Input Disable + [1:1] + + + + + + + ADC + Analog-to-Digital Converter + 0x78 + + + ADC + ADC Data Register Bytes + 0x0 + 16 + + + 0 + 65535 + + + + + ADCSRA + The ADC Control and Status register A + 0x2 + read-write + + + ADPS + ADC Prescaler Select Bits + [2:0] + + true + + ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 + + + ADIE + ADC Interrupt Enable + [3:3] + + + ADIF + ADC Interrupt Flag + [4:4] + + + ADATE + ADC Auto Trigger Enable + [5:5] + + + ADSC + ADC Start Conversion + [6:6] + + + ADEN + ADC Enable + [7:7] + + + + + ADCSRB + The ADC Control and Status register B + 0x3 + + + ADTS + ADC Auto Trigger Source bits + [2:0] + + true + + + + VAL_0x00 + Free Running mode + 0 + + + VAL_0x01 + Analog Comparator + 1 + + + VAL_0x02 + External Interrupt Request 0 + 2 + + + VAL_0x03 + Timer/Counter0 Compare Match A + 3 + + + VAL_0x04 + Timer/Counter0 Overflow + 4 + + + VAL_0x05 + Timer/Counter1 Compare Match B + 5 + + + VAL_0x06 + Timer/Counter1 Overflow + 6 + + + VAL_0x07 + Timer/Counter1 Capture Event + 7 + + + + + ACME + Analog Comparator Multiplexer Enable + [6:6] + + + + + ADMUX + The ADC multiplexer Selection Register + 0x4 + + + MUX + Analog Channel Selection Bits + [3:0] + + true + + + + ADC0 + ADC Single Ended Input pin 0 + 0 + + + ADC1 + ADC Single Ended Input pin 1 + 1 + + + ADC2 + ADC Single Ended Input pin 2 + 2 + + + ADC3 + ADC Single Ended Input pin 3 + 3 + + + ADC4 + ADC Single Ended Input pin 4 + 4 + + + ADC5 + ADC Single Ended Input pin 5 + 5 + + + ADC6 + ADC Single Ended Input pin 6 + 6 + + + ADC7 + ADC Single Ended Input pin 7 + 7 + + + TEMPSENS + Temperature sensor + 8 + + + ADC_VBG + Internal Reference (VBG) + 14 + + + ADC_GND + 0V (GND) + 15 + + + + + ADLAR + Left Adjust Result + [5:5] + + + REFS + Reference Selection Bits + [7:6] + + true + + REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 + + + + + DIDR0 + Digital Input Disable Register + 0x6 + + + ADC0D + ADC Digital Input Disable + [0:0] + + + ADC1D + ADC Digital Input Disable + [1:1] + + + ADC2D + ADC Digital Input Disable + [2:2] + + + ADC3D + ADC Digital Input Disable + [3:3] + + + ADC4D + ADC Digital Input Disable + [4:4] + + + ADC5D + ADC Digital Input Disable + [5:5] + + + ADC6D + ADC Digital Input Disable + [6:6] + + + ADC7D + ADC Digital Input Disable + [7:7] + + + + + + + CFD + <TBD> + 0x62 + + + XFDCSR + XOSC Failure Detection Control and Status Register + 0x0 + + + XFDIE + Failure Detection Interrupt Enable + [0:0] + + + XFDIF + Failure Detection Interrupt Flag + [1:1] + + + + + + + CPU + <TBD> + 0x3E + + RESET + External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + 0 + + + INT0 + External Interrupt Request 0 + 1 + + + INT1 + External Interrupt Request 1 + 2 + + + PCINT0 + Pin Change Interrupt Request 0 + 3 + + + PCINT1 + Pin Change Interrupt Request 1 + 4 + + + PCINT2 + Pin Change Interrupt Request 2 + 5 + + + WDT + Watchdog Time-out Interrupt + 6 + + + TIMER2_COMPA + Timer/Counter2 Compare Match A + 7 + + + TIMER2_COMPB + Timer/Counter2 Compare Match B + 8 + + + TIMER2_OVF + Timer/Counter2 Overflow + 9 + + + TIMER1_CAPT + Timer/Counter1 Capture Event + 10 + + + TIMER1_COMPA + Timer/Counter1 Compare Match A + 11 + + + TIMER1_COMPB + Timer/Counter1 Compare Match B + 12 + + + TIMER1_OVF + Timer/Counter1 Overflow + 13 + + + TIMER0_COMPA + TimerCounter0 Compare Match A + 14 + + + TIMER0_COMPB + TimerCounter0 Compare Match B + 15 + + + TIMER0_OVF + Timer/Couner0 Overflow + 16 + + + SPI0_STC + SPI Serial Transfer Complete + 17 + + + USART0_RX + USART0 Rx Complete + 18 + + + USART0_UDRE + USART0, Data Register Empty + 19 + + + USART0_TX + USART0 Tx Complete + 20 + + + ADC + ADC Conversion Complete + 21 + + + EE_READY + EEPROM Ready + 22 + + + ANALOG_COMP + Analog Comparator + 23 + + + TWI0 + Two-wire Serial Interface + 24 + + + SPM_Ready + Store Program Memory Read + 25 + + + USART0_START + USART0 Start frame detection + 26 + + + PCINT3 + Pin Change Interrupt Request 3 + 27 + + + USART1_RX + USART1 Rx Complete + 28 + + + USART1_UDRE + USART1, Data Register Empty + 29 + + + USART1_TX + USART1 Tx Complete + 30 + + + USART1_START + USART1 Start frame detection + 31 + + + TIMER3_CAPT + Timer/Counter3 Capture Event + 32 + + + TIMER3_COMPA + Timer/Counter3 Compare Match A + 33 + + + TIMER3_COMPB + Timer/Counter3 Compare Match B + 34 + + + TIMER3_OVF + Timer/Counter3 Overflow + 35 + + + CFD + Clock failure detection interrupt + 36 + + + PTC_EOC + PTC End of conversion + 37 + + + PTC_WCOMP + PTC Window comparator mode + 38 + + + SPI1_STC + SPI1 Serial Transfer Complete + 39 + + + TWI1 + TWI Transfer Complete + 40 + + + TIMER4_CAPT + Timer/Counter4 Capture Event + 41 + + + TIMER4_COMPA + Timer/Counter4 Compare Match A + 42 + + + TIMER4_COMPB + Timer/Counter4 Compare Match B + 43 + + + TIMER4_OVF + Timer/Counter4 Overflow + 44 + + + + CLKPR + Clock Prescale Register + 0x23 + read-only + + + CLKPS + Clock Prescaler Select Bits + [3:0] + + true + + + + VAL_0x00 + 1 + 0 + + + VAL_0x01 + 2 + 1 + + + VAL_0x02 + 4 + 2 + + + VAL_0x03 + 8 + 3 + + + VAL_0x04 + 16 + 4 + + + VAL_0x05 + 32 + 5 + + + VAL_0x06 + 64 + 6 + + + VAL_0x07 + 128 + 7 + + + VAL_0x08 + 256 + 8 + + + + + CLKPCE + Clock Prescaler Change Enable + [7:7] + + + + + GPIOR0 + General Purpose I/O Register 0 + 0x0 + + + 0 + 255 + + + + + GPIOR1 + General Purpose I/O Register 1 + 0xC + + + 0 + 255 + + + + + GPIOR2 + General Purpose I/O Register 2 + 0xD + + + 0 + 255 + + + + + MCUCR + MCU Control Register + 0x17 + + + IVCE + <TBD> + [0:0] + + + IVSEL + <TBD> + [1:1] + + + PUD + <TBD> + [4:4] + + + BODSE + BOD Sleep Enable + [5:5] + + + BODS + BOD Sleep + [6:6] + + + + + MCUSR + MCU Status Register + 0x16 + + + PORF + Power-on reset flag + [0:0] + + + EXTRF + External Reset Flag + [1:1] + + + BORF + Brown-out Reset Flag + [2:2] + + + WDRF + Watchdog Reset Flag + [3:3] + + + + + OSCCAL + Oscillator Calibration Value + 0x28 + read-only + + + OSCCAL + Oscillator Calibration + [7:0] + + + 0 + 255 + + + + + + + PRR0 + Power Reduction Register 0 + 0x26 + read-write + + + PRADC + Power Reduction ADC + [0:0] + + + PRUSART0 + Power Reduction USART0 + [1:1] + + + PRSPI0 + Power Reduction Serial Peripheral Interface 1 + [2:2] + + + PRTIM1 + Power Reduction Timer/Counter1 + [3:3] + + + PRUSART1 + Power Reduction USART1 + [4:4] + + + PRTIM0 + Power Reduction Timer/Counter0 + [5:5] + + + PRTIM2 + Power Reduction Timer/Counter2 + [6:6] + + + PRTWI0 + Power Reduction TWI0 + [7:7] + + + + + PRR1 + Power Reduction Register 1 + 0x27 + read-write + + + PRTIM3 + Power Reduction Timer/Counter3 + [0:0] + + + PRSPI1 + Power Reduction Serial Peripheral Interface 1 + [2:2] + + + PRTIM4 + Power Reduction Timer/Counter4 + [3:3] + + + PRPTC + Power Reduction Peripheral Touch Controller + [4:4] + + + PRTWI1 + Power Reduction TWI1 + [5:5] + + + + + SMCR + Sleep Mode Control Register + 0x15 + + + SE + Sleep Enable + [0:0] + + + SM + Sleep Mode Select Bits + [3:1] + + true + + + + IDLE + Idle + 0 + + + ADC + ADC Noise Reduction (If Available) + 1 + + + PDOWN + Power Down + 2 + + + PSAVE + Power Save + 3 + + + VAL_0x04 + Reserved + 4 + + + VAL_0x05 + Reserved + 5 + + + STDBY + Standby + 6 + + + ESTDBY + Extended Standby + 7 + + + + + + + SPMCSR + Store Program Memory Control and Status Register + 0x19 + + + SPMEN + Store Program Memory + [0:0] + + + PGERS + Page Erase + [1:1] + + + PGWRT + Page Write + [2:2] + + + BLBSET + Boot Lock Bit Set + [3:3] + + + RWWSRE + Read-While-Write section read enable + [4:4] + + + SIGRD + Signature Row Read + [5:5] + + + RWWSB + Read-While-Write Section Busy + [6:6] + + + SPMIE + SPM Interrupt Enable + [7:7] + + + + + + + EEPROM + <TBD> + 0x3F + + + EEAR + EEPROM Address Register Bytes + 0x2 + 16 + + + 0 + 65535 + + + + + EECR + EEPROM Control Register + 0x0 + + + EERE + EEPROM Read Enable + [0:0] + + + EEPE + EEPROM Write Enable + [1:1] + + + EEMPE + EEPROM Master Write Enable + [2:2] + + + EERIE + EEPROM Ready Interrupt Enable + [3:3] + + + EEPM + EEPROM Programming Mode Bits + [5:4] + + true + + + + VAL_0x00 + Erase and Write in one operation + 0 + + + VAL_0x01 + Erase Only + 1 + + + VAL_0x02 + Write Only + 2 + + + + + + + EEDR + EEPROM Data Register + 0x1 + + + 0 + 255 + + + + + + + EXINT + <TBD> + 0x3B + + + EICRA + External Interrupt Control Register + 0x2E + + + ISC0 + External Interrupt Sense Control 0 Bits + [1:0] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC1 + External Interrupt Sense Control 1 Bits + [3:2] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + + + EIFR + External Interrupt Flag Register + 0x1 + read-only + + + INTF + External Interrupt Flags + [1:0] + + + 0 + 3 + + + + + + + EIMSK + External Interrupt Mask Register + 0x2 + + INT0External Interrupt Request Enable01INT1External Interrupt Request Enable11 + + + PCICR + Pin Change Interrupt Control Register + 0x2D + + + PCIE + Pin Change Interrupt Enables + [3:0] + + + 0 + 15 + + + + + + + PCIFR + Pin Change Interrupt Flag Register + 0x0 + read-only + + + PCIF + Pin Change Interrupt Flags + [3:0] + + + 0 + 15 + + + + + + + PCMSK0 + Pin Change Mask Register 0 + 0x30 + + + PCINT + Pin Change Enable Masks + [7:0] + + + 0 + 255 + + + + + + + PCMSK1 + Pin Change Mask Register 1 + 0x31 + + + PCINT + Pin Change Enable Masks + [6:0] + + + 0 + 127 + + + + + + + PCMSK2 + Pin Change Mask Register 2 + 0x32 + + + PCINT + Pin Change Enable Masks + [7:0] + + + 0 + 255 + + + + + + + PCMSK3 + Pin Change Mask Register 3 + 0x38 + + + PCINT + Pin Change Enable Masks + [3:0] + + + 0 + 15 + + + + + + + + + FUSE + Fuses + 0x0 + + + EXTENDED + <TBD> + 0x2 + + + BODLEVEL + Brown-out Detector trigger level + [2:0] + + true + + + + 4V3 + Brown-out detection at VCC=4.3 V + 4 + + + 2V7 + Brown-out detection at VCC=2.7 V + 5 + + + 1V8 + Brown-out detection at VCC=1.8 V + 6 + + + DISABLED + Brown-out detection disabled + 7 + + + + + CFD + Clock Failure Detection + [3:3] + + true + + + + CFD_DISABLED + Disabled + 0 + + + CFD_ENABLED + Enabled + 1 + + + + + + + HIGH + <TBD> + 0x1 + + + BOOTRST + Boot Reset vector Enabled + [0:0] + + + BOOTSZ + Select boot size + [2:1] + + true + + + + 2048W_3800 + Boot Flash size=2048 words start address=$3800 + 0 + + + 1024W_3C00 + Boot Flash size=1024 words start address=$3C00 + 1 + + + 512W_3E00 + Boot Flash size=512 words start address=$3E00 + 2 + + + 256W_3F00 + Boot Flash size=256 words start address=$3F00 + 3 + + + + + EESAVE + Preserve EEPROM through the Chip Erase cycle + [3:3] + + + WDTON + Watch-dog Timer always on + [4:4] + + + SPIEN + Serial program downloading (SPI) enabled + [5:5] + + + DWEN + Debug Wire enable + [6:6] + + + RSTDISBL + Reset Disabled (Enable PC6 as i/o pin) + [7:7] + + + + + LOW + <TBD> + 0x0 + + + SUT_CKSEL + Select Clock Source + [5:0] + + true + + + + EXTCLK_6CK_14CK_0MS + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 0 + + + INTRCOSC_8MHZ_6CK_14CK_0MS + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 2 + + + INTRCOSC_128KHZ_6CK_14CK_0MS + Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 3 + + + EXTLOFXTAL_1KCK_14CK_0MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms + 4 + + + EXTLOFXTAL_32KCK_14CK_0MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms + 5 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 8 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 9 + + + EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 10 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 11 + + + EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 12 + + + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 13 + + + EXTXOSC_8MHZ_XX_258CK_14CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 14 + + + EXTXOSC_8MHZ_XX_1KCK_14CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 15 + + + EXTCLK_6CK_14CK_4MS1 + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + 16 + + + INTRCOSC_8MHZ_6CK_14CK_4MS1 + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + 18 + + + INTRCOSC_128KHZ_6CK_14CK_4MS1 + Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + 19 + + + EXTLOFXTAL_1KCK_14CK_4MS1 + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms + 20 + + + EXTLOFXTAL_32KCK_14CK_4MS1 + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms + 21 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 24 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 25 + + + EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 26 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 27 + + + EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 28 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 29 + + + EXTXOSC_8MHZ_XX_258CK_14CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 30 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 31 + + + EXTCLK_6CK_14CK_65MS + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + 32 + + + INTRCOSC_8MHZ_6CK_14CK_65MS + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + 34 + + + INTRCOSC_128KHZ_6CK_14CK_65MS + Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + 35 + + + EXTLOFXTAL_1KCK_14CK_65MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms + 36 + + + EXTLOFXTAL_32KCK_14CK_65MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms + 37 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 40 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 41 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 42 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 43 + + + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 44 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 45 + + + EXTXOSC_8MHZ_XX_1KCK_14CK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 46 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 47 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 56 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 57 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 58 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 59 + + + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 60 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 61 + + + EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 62 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 63 + + + + + CKOUT + Clock output on PORTB0 + [6:6] + + + CKDIV8 + Divide clock by 8 internally + [7:7] + + + + + + + LOCKBIT + Lockbits + 0x0 + + + LOCKBIT + <TBD> + 0x0 + + + LB + Memory Lock + [1:0] + + true + + + + PROG_VER_DISABLED + Further programming and verification disabled + 0 + + + PROG_DISABLED + Further programming disabled + 2 + + + NO_LOCK + No memory lock features enabled + 3 + + + + + BLB0 + Boot Loader Protection Mode + [3:2] + + true + + + + LPM_SPM_DISABLE + LPM and SPM prohibited in Application Section + 0 + + + LPM_DISABLE + LPM prohibited in Application Section + 1 + + + SPM_DISABLE + SPM prohibited in Application Section + 2 + + + NO_LOCK + No lock on SPM and LPM in Application Section + 3 + + + + + BLB1 + Boot Loader Protection Mode + [5:4] + + true + + + + LPM_SPM_DISABLE + LPM and SPM prohibited in Boot Section + 0 + + + LPM_DISABLE + LPM prohibited in Boot Section + 1 + + + SPM_DISABLE + SPM prohibited in Boot Section + 2 + + + NO_LOCK + No lock on SPM and LPM in Boot Section + 3 + + + + + + + + + PORTB + I/O Port + 0x23 + + + DDRB + Port B Data Direction Register + 0x1 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PINB + Port B Input Pins + 0x0 + read-write + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PORTB + Port B Data Register + 0x2 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + + + PORTC + I/O Port + 0x26 + + + DDRC + Port C Data Direction Register + 0x1 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + + + PINC + Port C Input Pins + 0x0 + read-write + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + + + PORTC + Port C Data Register + 0x2 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + + + + + PORTD + I/O Port + 0x29 + + + DDRD + Port D Data Direction Register + 0x1 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PIND + Port D Input Pins + 0x0 + read-write + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PORTD + Port D Data Register + 0x2 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + + + PORTE + I/O Port + 0x2C + + + DDRE + Port E Data Direction Register + 0x1 + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + + + PINE + Port E Input Pins + 0x0 + read-write + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + + + PORTE + Port E Data Register + 0x2 + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + + + + + SPI0 + <TBD> + 0x4C + + + SPCR + SPI Control Register + 0x0 + + + SPR + SPI Clock Rate Selects + [1:0] + + true + + SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 + + + CPHA + Clock Phase + [2:2] + + + CPOL + Clock polarity + [3:3] + + + MSTR + Master/Slave Select + [4:4] + + + DORD + Data Order + [5:5] + + + SPE + SPI Enable + [6:6] + + + SPIE + SPI Interrupt Enable + [7:7] + + + + + SPDR + SPI Data Register + 0x2 + + + 0 + 255 + + + + + SPSR + SPI Status Register + 0x1 + read-write + + + SPI2X + Double SPI Speed Bit + [0:0] + read-write + + WCOL + Write Collision Flag + [6:6] + read-only + + SPIF + SPI Interrupt Flag + [7:7] + read-only + + + + + + SPI1 + <TBD> + 0xAC + + + SPCR + SPI Control Register + 0x0 + + + SPR + SPI Clock Rate Selects + [1:0] + + true + + SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 + + + CPHA + Clock Phase + [2:2] + + + CPOL + Clock polarity + [3:3] + + + MSTR + Master/Slave Select + [4:4] + + + DORD + Data Order + [5:5] + + + SPE + SPI Enable + [6:6] + + + SPIE + SPI Interrupt Enable + [7:7] + + + + + SPDR + SPI Data Register + 0x2 + + + 0 + 255 + + + + + SPSR + SPI Status Register + 0x1 + read-write + + + SPI2X + Double SPI Speed Bit + [0:0] + read-write + + WCOL + Write Collision Flag + [6:6] + read-only + + SPIF + SPI Interrupt Flag + [7:7] + read-only + + + + + + TC0 + <TBD> + 0x35 + + + GTCCR + General Timer/Counter Control Register + 0xE + + + PSRSYNC + Prescaler Reset Timer/Counter1 and Timer/Counter0 + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + OCR0A + Timer/Counter0 Output Compare Register + 0x12 + + + 0 + 255 + + + + + OCR0B + Timer/Counter0 Output Compare Register + 0x13 + + + 0 + 255 + + + + + TCCR0A + Timer/Counter Control Register A + 0xF + + + WGM0 + Waveform Generation Mode + [1:0] + + true + WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 + + + COM0B + Compare Output B Mode + [5:4] + + true + COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 + + + COM0A + Compare Output A Mode + [7:6] + + true + + + + + + TCCR0B + Timer/Counter Control Register B + 0x10 + + + CS0 + Clock Select + [2:0] + + true + + CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM02 + Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) + [3:3] + + + FOC0B + Force Output Compare B + [6:6] + write-only + + FOC0A + Force Output Compare A + [7:7] + write-only + + + + TCNT0 + Timer/Counter0 + 0x11 + + + 0 + 255 + + + + + TIFR0 + Timer/Counter0 Interrupt Flag register + 0x0 + read-write + + + TOV0 + Timer/Counter0 Overflow Flag + [0:0] + + + OCF0A + Timer/Counter0 Output Compare Flag 0A + [1:1] + + + OCF0B + Timer/Counter0 Output Compare Flag 0B + [2:2] + + + + + TIMSK0 + Timer/Counter0 Interrupt Mask Register + 0x39 + + + TOIE0 + Timer/Counter0 Overflow Interrupt Enable + [0:0] + + + OCIE0A + Timer/Counter0 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE0B + Timer/Counter0 Output Compare Match B Interrupt Enable + [2:2] + + + + + + + TC1 + <TBD> + 0x36 + + + GTCCR + General Timer/Counter Control Register + 0xD + + + PSRSYNC + Prescaler Reset Timer/Counter1 and Timer/Counter0 + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + ICR1 + Timer/Counter1 Input Capture Register Bytes + 0x50 + 16 + + + 0 + 65535 + + + + + OCR1A + Timer/Counter1 Output Compare Register Bytes + 0x52 + 16 + + + 0 + 65535 + + + + + OCR1B + Timer/Counter1 Output Compare Register Bytes + 0x54 + 16 + + + 0 + 65535 + + + + + TCCR1A + Timer/Counter1 Control Register A + 0x4A + + + WGM1 + Waveform Generation Mode + [1:0] + + + 0 + 3 + + + + + COM1B + Compare Output Mode 1B, bits + [5:4] + + true + COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM1A + Compare Output Mode 1A, bits + [7:6] + + true + + + + + + TCCR1B + Timer/Counter1 Control Register B + 0x4B + + + CS1 + Prescaler source of Timer/Counter 1 + [2:0] + + true + CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM1 + Waveform Generation Mode + [4:3] + + + 0 + 3 + + + + + ICES1 + Input Capture 1 Edge Select + [6:6] + + + ICNC1 + Input Capture 1 Noise Canceler + [7:7] + + + + + TCCR1C + Timer/Counter1 Control Register C + 0x4C + + + FOC1B + <TBD> + [6:6] + write-only + + FOC1A + <TBD> + [7:7] + write-only + + + + TCNT1 + Timer/Counter1 Bytes + 0x4E + 16 + + + 0 + 65535 + + + + + TIFR1 + Timer/Counter Interrupt Flag register + 0x0 + read-write + + + TOV1 + Timer/Counter1 Overflow Flag + [0:0] + + + OCF1A + Output Compare Flag 1A + [1:1] + + + OCF1B + Output Compare Flag 1B + [2:2] + + + ICF1 + Input Capture Flag 1 + [5:5] + + + + + TIMSK1 + Timer/Counter Interrupt Mask Register + 0x39 + + + TOIE1 + Timer/Counter1 Overflow Interrupt Enable + [0:0] + + + OCIE1A + Timer/Counter1 Output CompareA Match Interrupt Enable + [1:1] + + + OCIE1B + Timer/Counter1 Output CompareB Match Interrupt Enable + [2:2] + + + ICIE1 + Timer/Counter1 Input Capture Interrupt Enable + [5:5] + + + + + + + TC2 + Timer/Counter, 8-bit Async + 0x37 + + + ASSR + Asynchronous Status Register + 0x7F + + + TCR2BUB + Timer/Counter Control Register2 Update Busy + [0:0] + + + TCR2AUB + Timer/Counter Control Register2 Update Busy + [1:1] + + + OCR2BUB + Output Compare Register 2 Update Busy + [2:2] + + + OCR2AUB + Output Compare Register2 Update Busy + [3:3] + + + TCN2UB + Timer/Counter2 Update Busy + [4:4] + + + AS2 + Asynchronous Timer/Counter2 + [5:5] + + + EXCLK + Enable External Clock Input + [6:6] + + + + + GTCCR + General Timer Counter Control register + 0xC + + + PSRASY + Prescaler Reset Timer/Counter2 + [1:1] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + OCR2A + Timer/Counter2 Output Compare Register A + 0x7C + + + 0 + 255 + + + + + OCR2B + Timer/Counter2 Output Compare Register B + 0x7D + + + 0 + 255 + + + + + TCCR2A + Timer/Counter2 Control Register A + 0x79 + + + WGM2 + Waveform Genration Mode + [1:0] + + true + WGM2read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 + + + COM2B + Compare Output B Mode + [5:4] + + true + COM2Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 + + + COM2A + Compare Output A Mode + [7:6] + + true + + + + + + TCCR2B + Timer/Counter2 Control Register B + 0x7A + + + CS2 + Clock Select bits + [2:0] + + true + + CS2read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_32Running, CLK/323PRESCALE_64Running, CLK/644PRESCALE_128Running, CLK/1285PRESCALE_256Running, CLK/2566PRESCALE_1024Running, CLK/10247 + + + WGM22 + Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) + [3:3] + + + FOC2B + Force Output Compare B + [6:6] + write-only + + FOC2A + Force Output Compare A + [7:7] + write-only + + + + TCNT2 + Timer/Counter2 + 0x7B + + + 0 + 255 + + + + + TIFR2 + Timer/Counter Interrupt Flag Register + 0x0 + read-write + + + TOV2 + Timer/Counter2 Overflow Flag + [0:0] + + + OCF2A + Output Compare Flag 2A + [1:1] + + + OCF2B + Output Compare Flag 2B + [2:2] + + + + + TIMSK2 + Timer/Counter Interrupt Mask register + 0x39 + + + TOIE2 + Timer/Counter2 Overflow Interrupt Enable + [0:0] + + + OCIE2A + Timer/Counter2 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE2B + Timer/Counter2 Output Compare Match B Interrupt Enable + [2:2] + + + + + + + TC3 + <TBD> + 0x38 + + + ICR3 + Timer/Counter3 Input Capture Register Bytes + 0x5E + 16 + + + 0 + 65535 + + + + + OCR3A + Timer/Counter3 Output Compare Register Bytes + 0x60 + 16 + + + 0 + 65535 + + + + + OCR3B + Timer/Counter3 Output Compare Register Bytes + 0x62 + 16 + + + 0 + 65535 + + + + + TCCR3A + Timer/Counter3 Control Register A + 0x58 + + + WGM3 + Waveform Genration Mode + [1:0] + + + 0 + 3 + + + + + COM3B + Compare Output Mode bits + [5:4] + + true + COM3Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM3A + Compare Output Mode bits + [7:6] + + true + + + + + + TCCR3B + Timer/Counter3 Control Register B + 0x59 + + + CS3 + Clock Select bits + [2:0] + + true + CS3read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + ICES3 + Input Capture Edge Select + [6:6] + + + ICNC3 + Input Capture Noise Canceler + [7:7] + + WGM3Waveform Generation Mode32read-write + + + + TCCR3C + Timer/Counter3 Control Register C + 0x5A + + + FOC3B + Force Output Compare for Channel B + [6:6] + write-only + + FOC3A + Force Output Compare for Channel A + [7:7] + write-only + + + + TCNT3 + Timer/Counter3 Bytes + 0x5C + 16 + + + 0 + 65535 + + + + + TIFR3 + Timer/Counter3 Interrupt Flag register + 0x0 + read-write + + + TOV3 + Timer/Counter3 Overflow Flag + [0:0] + + + OCF3A + Output Compare Flag 3A + [1:1] + + + OCF3B + Output Compare Flag 3B + [2:2] + + + ICF3 + Timer/Counter3 Input Capture Flag + [5:5] + + + + + TIMSK3 + Timer/Counter Interrupt Mask Register + 0x39 + + + TOIE3 + Timer/Counter3 Overflow Interrupt Enable + [0:0] + + + OCIE3A + Timer/Counter3 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE3B + Timer/Counter3 Output Compare Match B Interrupt Enable + [2:2] + + + ICIE3 + Timer/Counter3 Input Capture Interrupt Enable + [5:5] + + + + + + + TC4 + <TBD> + 0x39 + + + ICR4 + Timer/Counter4 Input Capture Register Bytes + 0x6D + 16 + + + 0 + 65535 + + + + + OCR4A + Timer/Counter4 Output Compare Register Bytes + 0x6F + 16 + + + 0 + 65535 + + + + + OCR4B + Timer/Counter4 Output Compare Register Bytes + 0x71 + 16 + + + 0 + 65535 + + + + + TCCR4A + Timer/Counter4 Control Register A + 0x67 + + + WGM4 + Waveform Generation Mode + [1:0] + + + 0 + 3 + + + + + COM4B + Compare Output Mode bits + [5:4] + + true + COM4Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM4A + Compare Output Mode bits + [7:6] + + true + + + + + + TCCR4B + Timer/Counter4 Control Register B + 0x68 + + + CS4 + Clock Select bits + [2:0] + + true + CS4read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + ICES4 + Input Capture Edge Select + [6:6] + + + ICNC4 + Input Capture Noise Canceler + [7:7] + + WGM4Waveform Generation Mode32read-write + + + + TCCR4C + Timer/Counter4 Control Register C + 0x69 + + + FOC4B + Force Output Compare for Channel B + [6:6] + write-only + + FOC4A + Force Output Compare for Channel A + [7:7] + write-only + + + + TCNT4 + Timer/Counter4 Bytes + 0x6B + 16 + + + 0 + 65535 + + + + + TIFR4 + Timer/Counter4 Interrupt Flag register + 0x0 + read-write + + + TOV4 + Timer/Counter4 Overflow Flag + [0:0] + + + OCF4A + Output Compare Flag 4A + [1:1] + + + OCF4B + Output Compare Flag 4B + [2:2] + + + ICF4 + Timer/Counter4 Input Capture Flag + [5:5] + + + + + TIMSK4 + Timer/Counter4 Interrupt Mask Register + 0x39 + + + TOIE4 + Timer/Counter4 Overflow Interrupt Enable + [0:0] + + + OCIE4A + Timer/Counter4 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE4B + Timer/Counter4 Output Compare Match B Interrupt Enable + [2:2] + + + ICIE4 + Timer/Counter4 Input Capture Interrupt Enable + [5:5] + + + + + + + TWI0 + Two Wire Serial Interface + 0xB8 + + + TWAMR + TWI (Slave) Address Mask Register + 0x5 + + + TWAM + TWI (Slave) Address Mask Bits + [7:1] + + + 0 + 127 + + + + + + + TWAR + TWI (Slave) Address register + 0x2 + + + TWGCE + TWI General Call Recognition Enable Bit + [0:0] + + + TWA + TWI (Slave) Address register Bits + [7:1] + + + 0 + 127 + + + + + + + TWBR + TWI Bit Rate register + 0x0 + + + 0 + 255 + + + + + TWCR + TWI Control Register + 0x4 + read-write + + + TWIE + TWI Interrupt Enable + [0:0] + + + TWEN + TWI Enable Bit + [2:2] + + + TWWC + TWI Write Collition Flag + [3:3] + read-only + + TWSTO + TWI Stop Condition Bit + [4:4] + + + TWSTA + TWI Start Condition Bit + [5:5] + + + TWEA + TWI Enable Acknowledge Bit + [6:6] + + + TWINT + TWI Interrupt Flag + [7:7] + + + + + TWDR + TWI Data register + 0x3 + + + 0 + 255 + + + + + TWSR + TWI Status Register + 0x1 + + + TWPS + TWI Prescaler + [1:0] + + true + + TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 + + + TWS + TWI Status + [7:3] + read-only + + 0 + 31 + + + + + + + + + TWI1 + Two Wire Serial Interface + 0xD8 + + + TWAMR + TWI (Slave) Address Mask Register + 0x5 + + + TWAM1 + <TBD> + [7:1] + + + 0 + 127 + + + + + + + TWAR + TWI (Slave) Address register + 0x2 + + + 0 + 255 + + + + + TWBR + TWI Bit Rate register + 0x0 + + + 0 + 255 + + + + + TWCR + TWI Control Register + 0x4 + read-write + + + TWIE + TWI Interrupt Enable + [0:0] + + + TWEN + TWI Enable Bit + [2:2] + + + TWWC + TWI Write Collition Flag + [3:3] + read-only + + TWSTO + TWI Stop Condition Bit + [4:4] + + + TWSTA + TWI Start Condition Bit + [5:5] + + + TWEA + TWI Enable Acknowledge Bit + [6:6] + + + TWINT + TWI Interrupt Flag + [7:7] + + + + + TWDR + TWI Data register + 0x3 + + + 0 + 255 + + + + + TWSR + TWI Status Register + 0x1 + + + TWPS + TWI Prescaler + [1:0] + + true + + TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 + + + TWS + TWI Status + [7:3] + read-only + + 0 + 31 + + + + + + + + + USART0 + USART + 0xC0 + + + UBRR0 + USART Baud Rate Register Bytes + 0x4 + 16 + + + 0 + 65535 + + + + + UCSR0A + USART Control and Status Register A + 0x0 + read-write + + + MPCM0 + Multi-processor Communication Mode + [0:0] + + + U2X0 + Double the USART transmission speed + [1:1] + + + UPE0 + Parity Error + [2:2] + read-only + + DOR0 + Data overRun + [3:3] + read-only + + FE0 + Framing Error + [4:4] + read-only + + UDRE0 + USART Data Register Empty + [5:5] + read-only + + TXC0 + USART Transmit Complete + [6:6] + + + RXC0 + USART Receive Complete + [7:7] + read-only + + + + UCSR0B + USART Control and Status Register B + 0x1 + + + TXB80 + Transmit Data Bit 8 + [0:0] + + + RXB80 + Receive Data Bit 8 + [1:1] + read-only + + UCSZ02 + Character Size - together with UCSZ0 in UCSR0C + [2:2] + + + TXEN0 + Transmitter Enable + [3:3] + + + RXEN0 + Receiver Enable + [4:4] + + + UDRIE0 + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE0 + TX Complete Interrupt Enable + [6:6] + + + RXCIE0 + RX Complete Interrupt Enable + [7:7] + + + + + UCSR0C + USART Control and Status Register C + 0x2 + + + UCPOL0 + Clock Polarity + [0:0] + UCPOL0read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 + + + UCSZ0 + Character Size - together with UCSZ2 in UCSR0B + [2:1] + + + 0 + 3 + + + UCSZ0read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 + + + USBS0 + Stop Bit Select + [3:3] + + true + + USBS0read-writeSTOP11-bit0STOP22-bit1 + + + UPM0 + Parity Mode Bits + [5:4] + + true + + UPM0read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 + + + UMSEL0 + USART Mode Select + [7:6] + + true + + UMSEL0read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 + + + + + UCSR0D + USART Control and Status Register D + 0x3 + + + SFDE + Start frame detection enable + [5:5] + + + RXS + USART RX Start + [6:6] + + + RXSIE + USART RX Start Interrupt Enable + [7:7] + + + + + UDR0 + USART I/O Data Register 0 + 0x6 + + + 0 + 255 + + + + + + + USART1 + USART + 0xC8 + + + UBRR1 + USART Baud Rate Register Bytes + 0x4 + 16 + + + 0 + 65535 + + + + + UCSR1A + USART Control and Status Register A + 0x0 + read-write + + + MPCM1 + Multi-processor Communication Mode + [0:0] + + + U2X1 + Double the USART transmission speed + [1:1] + + + UPE1 + Parity Error + [2:2] + read-only + + DOR1 + Data overRun + [3:3] + read-only + + FE1 + Framing Error + [4:4] + read-only + + UDRE1 + USART Data Register Empty + [5:5] + read-only + + TXC1 + USART Transmit Complete + [6:6] + + + RXC1 + USART Receive Complete + [7:7] + read-only + + + + UCSR1B + USART Control and Status Register B + 0x1 + + + TXB81 + Transmit Data Bit 8 + [0:0] + + + RXB81 + Receive Data Bit 8 + [1:1] + read-only + + UCSZ12 + Character Size - together with UCSZ0 in UCSR1C + [2:2] + + + TXEN1 + Transmitter Enable + [3:3] + + + RXEN1 + Receiver Enable + [4:4] + + + UDRIE1 + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE1 + TX Complete Interrupt Enable + [6:6] + + + RXCIE1 + RX Complete Interrupt Enable + [7:7] + + + + + UCSR1C + USART Control and Status Register C + 0x2 + + + UCPOL1 + Clock Polarity + [0:0] + UCPOL1read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 + + + UCSZ1 + Character Size - together with UCSZ12 in UCSR1B + [2:1] + + + 0 + 3 + + + UCSZ1read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 + + + USBS1 + Stop Bit Select + [3:3] + + true + + USBS1read-writeSTOP11-bit0STOP22-bit1 + + + UPM1 + Parity Mode Bits + [5:4] + + true + + UPM1read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 + + + UMSEL1 + USART Mode Select + [7:6] + + true + + UMSEL1read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 + + + + + UCSR1D + USART Control and Status Register D + 0x3 + + + SFDE1 + Start frame detection enable + [5:5] + + + RXS1 + USART RX Start + [6:6] + + + RXSIE1 + USART RX Start Interrupt Enable + [7:7] + + + + + UDR1 + USART I/O Data Register + 0x6 + + + 0 + 255 + + + + + + + WDT + <TBD> + 0x60 + + + WDTCSR + Watchdog Timer Control Register + 0x0 + read-write + + + WDE + Watch Dog Enable + [3:3] + + + WDCE + Watchdog Change Enable + [4:4] + + + WDIE + Watchdog Timeout Interrupt Enable + [6:6] + + + WDIF + Watchdog Timeout Interrupt Flag + [7:7] + + WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 + + WDPHWatchdog Timer Prescaler - High Bit[5:5] + + + + + + \ No newline at end of file diff --git a/misc/svd/atmega32u4.svd b/misc/svd/atmega32u4.svd new file mode 100644 index 0000000..704a006 --- /dev/null +++ b/misc/svd/atmega32u4.svd @@ -0,0 +1,4649 @@ + + Atmel + ATmega32U4 + 8 + 8 + read-write + 0 + 0xff + + + AC + Analog Comparator + 0x50 + + + ACSR + Analog Comparator Control And Status Register + 0x0 + read-write + + + ACIS + Analog Comparator Interrupt Mode Select + [1:0] + + true + + ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 + + + ACIC + Analog Comparator Input Capture Enable + [2:2] + + + ACIE + Analog Comparator Interrupt Enable + [3:3] + + + ACI + Analog Comparator Interrupt Flag + [4:4] + + + ACO + Analog Compare Output + [5:5] + read-only + + ACBG + Analog Comparator Bandgap Select + [6:6] + + + ACD + Analog Comparator Disable + [7:7] + + + + + ADCSRB + ADC Control and Status Register B + 0x2B + + + ACME + Analog Comparator Multiplexer Enable + [6:6] + + + + + DIDR1 + <TBD> + 0x2F + + + AIN0D + AIN0 Digital Input Disable + [0:0] + + + AIN1D + AIN1 Digital Input Disable + [1:1] + + + + + + + ADC + Analog-to-Digital Converter + 0x78 + + + ADC + ADC Data Register Bytes + 0x0 + 16 + + + 0 + 65535 + + + + + ADCSRA + The ADC Control and Status register + 0x2 + read-write + + + ADPS + ADC Prescaler Select Bits + [2:0] + + true + + ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 + + + ADIE + ADC Interrupt Enable + [3:3] + + + ADIF + ADC Interrupt Flag + [4:4] + + + ADATE + ADC Auto Trigger Enable + [5:5] + + + ADSC + ADC Start Conversion + [6:6] + + + ADEN + ADC Enable + [7:7] + + + + + ADCSRB + ADC Control and Status Register B + 0x3 + + + ADTS + ADC Auto Trigger Sources + [4:0] + + true + + + + VAL_0x00 + Free Running mode + 0 + + + VAL_0x01 + Analog Comparator + 1 + + + VAL_0x02 + External Interrupt Request 0 + 2 + + + VAL_0x03 + Timer/Counter0 Compare Match A + 3 + + + VAL_0x04 + Timer/Counter0 Overflow + 4 + + + VAL_0x05 + Timer/Counter1 Compare Match B + 5 + + + VAL_0x06 + Timer/Counter1 Overflow + 6 + + + VAL_0x07 + Timer/Counter1 Capture Event + 7 + + + + + MUX5 + Analog Channel and Gain Selection Bits + [5:5] + + + ADHSM + ADC High Speed Mode + [7:7] + + + + + ADMUX + The ADC multiplexer Selection Register + 0x4 + + + MUX + Analog Channel and Gain Selection Bits + [4:0] + + + 0 + 31 + + + + + ADLAR + Left Adjust Result + [5:5] + + + REFS + Reference Selection Bits + [7:6] + + true + + REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 + + + + + DIDR0 + Digital Input Disable Register 0 + 0x6 + + + ADC0D + ADC0 Digital input Disable + [0:0] + + + ADC1D + ADC1 Digital input Disable + [1:1] + + + ADC2D + ADC2 Digital input Disable + [2:2] + + + ADC3D + ADC3 Digital input Disable + [3:3] + + + ADC4D + ADC4 Digital input Disable + [4:4] + + + ADC5D + ADC5 Digital input Disable + [5:5] + + + ADC6D + ADC6 Digital input Disable + [6:6] + + + ADC7D + ADC7 Digital input Disable + [7:7] + + + + + DIDR2 + Digital Input Disable Register 2 + 0x5 + + + ADC8D + ADC8 Digital input Disable + [0:0] + + + ADC9D + ADC9 Digital input Disable + [1:1] + + + ADC10D + ADC10 Digital input Disable + [2:2] + + + ADC11D + ADC11 Digital input Disable + [3:3] + + + ADC12D + ADC12 Digital input Disable + [4:4] + + + ADC13D + ADC13 Digital input Disable + [5:5] + + + + + + + BOOT_LOAD + Bootloader + 0x57 + + + SPMCSR + Store Program Memory Control Register + 0x0 + + + SPMEN + Store Program Memory Enable + [0:0] + + + PGERS + Page Erase + [1:1] + + + PGWRT + Page Write + [2:2] + + + BLBSET + Boot Lock Bit Set + [3:3] + + + RWWSRE + Read While Write section read enable + [4:4] + + + SIGRD + Signature Row Read + [5:5] + + + RWWSB + Read While Write Section Busy + [6:6] + + + SPMIE + SPM Interrupt Enable + [7:7] + + + + + + + CPU + CPU Registers + 0x3E + + RESET + External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + 0 + + + INT0 + External Interrupt Request 0 + 1 + + + INT1 + External Interrupt Request 1 + 2 + + + INT2 + External Interrupt Request 2 + 3 + + + INT3 + External Interrupt Request 3 + 4 + + + Reserved1 + Reserved1 + 5 + + + Reserved2 + Reserved2 + 6 + + + INT6 + External Interrupt Request 6 + 7 + + + Reserved3 + Reserved3 + 8 + + + PCINT0 + Pin Change Interrupt Request 0 + 9 + + + USB_GEN + USB General Interrupt Request + 10 + + + USB_COM + USB Endpoint/Pipe Interrupt Communication Request + 11 + + + WDT + Watchdog Time-out Interrupt + 12 + + + Reserved4 + Reserved4 + 13 + + + Reserved5 + Reserved5 + 14 + + + Reserved6 + Reserved6 + 15 + + + TIMER1_CAPT + Timer/Counter1 Capture Event + 16 + + + TIMER1_COMPA + Timer/Counter1 Compare Match A + 17 + + + TIMER1_COMPB + Timer/Counter1 Compare Match B + 18 + + + TIMER1_COMPC + Timer/Counter1 Compare Match C + 19 + + + TIMER1_OVF + Timer/Counter1 Overflow + 20 + + + TIMER0_COMPA + Timer/Counter0 Compare Match A + 21 + + + TIMER0_COMPB + Timer/Counter0 Compare Match B + 22 + + + TIMER0_OVF + Timer/Counter0 Overflow + 23 + + + SPI_STC + SPI Serial Transfer Complete + 24 + + + USART1_RX + USART1, Rx Complete + 25 + + + USART1_UDRE + USART1 Data register Empty + 26 + + + USART1_TX + USART1, Tx Complete + 27 + + + ANALOG_COMP + Analog Comparator + 28 + + + ADC + ADC Conversion Complete + 29 + + + EE_READY + EEPROM Ready + 30 + + + TIMER3_CAPT + Timer/Counter3 Capture Event + 31 + + + TIMER3_COMPA + Timer/Counter3 Compare Match A + 32 + + + TIMER3_COMPB + Timer/Counter3 Compare Match B + 33 + + + TIMER3_COMPC + Timer/Counter3 Compare Match C + 34 + + + TIMER3_OVF + Timer/Counter3 Overflow + 35 + + + TWI + 2-wire Serial Interface + 36 + + + SPM_READY + Store Program Memory Read + 37 + + + TIMER4_COMPA + Timer/Counter4 Compare Match A + 38 + + + TIMER4_COMPB + Timer/Counter4 Compare Match B + 39 + + + TIMER4_COMPD + Timer/Counter4 Compare Match D + 40 + + + TIMER4_OVF + Timer/Counter4 Overflow + 41 + + + TIMER4_FPF + Timer/Counter4 Fault Protection Interrupt + 42 + + + + CLKPR + <TBD> + 0x23 + + + CLKPS + <TBD> + [3:0] + + true + + + + VAL_0x00 + 1 + 0 + + + VAL_0x01 + 2 + 1 + + + VAL_0x02 + 4 + 2 + + + VAL_0x03 + 8 + 3 + + + VAL_0x04 + 16 + 4 + + + VAL_0x05 + 32 + 5 + + + VAL_0x06 + 64 + 6 + + + VAL_0x07 + 128 + 7 + + + VAL_0x08 + 256 + 8 + + + + + CLKPCE + <TBD> + [7:7] + + + + + CLKSEL0 + <TBD> + 0x87 + + + CLKS + <TBD> + [0:0] + + + EXTE + <TBD> + [2:2] + + + RCE + <TBD> + [3:3] + + + EXSUT + <TBD> + [5:4] + + + 0 + 3 + + + + + RCSUT + <TBD> + [7:6] + + + 0 + 3 + + + + + + + CLKSEL1 + <TBD> + 0x88 + + + EXCKSEL + <TBD> + [3:0] + + + 0 + 15 + + + + + RCCKSEL + <TBD> + [7:4] + + + 0 + 15 + + + + + + + CLKSTA + <TBD> + 0x89 + read-only + + + EXTON + <TBD> + [0:0] + + + RCON + <TBD> + [1:1] + + + + + EIND + Extended Indirect Register + 0x1E + + + 0 + 255 + + + + + GPIOR0 + General Purpose IO Register 0 + 0x0 + + + GPIOR00 + General Purpose IO Register 0 bit 0 + [0:0] + + + GPIOR01 + General Purpose IO Register 0 bit 1 + [1:1] + + + GPIOR02 + General Purpose IO Register 0 bit 2 + [2:2] + + + GPIOR03 + General Purpose IO Register 0 bit 3 + [3:3] + + + GPIOR04 + General Purpose IO Register 0 bit 4 + [4:4] + + + GPIOR05 + General Purpose IO Register 0 bit 5 + [5:5] + + + GPIOR06 + General Purpose IO Register 0 bit 6 + [6:6] + + + GPIOR07 + General Purpose IO Register 0 bit 7 + [7:7] + + + + + GPIOR1 + General Purpose IO Register 1 + 0xC + + + GPIOR + General Purpose IO Register 1 bis + [7:0] + + + 0 + 255 + + + + + + + GPIOR2 + General Purpose IO Register 2 + 0xD + + + GPIOR + General Purpose IO Register 2 bis + [7:0] + + + 0 + 255 + + + + + + + MCUCR + MCU Control Register + 0x17 + + + IVCE + Interrupt Vector Change Enable + [0:0] + + + IVSEL + Interrupt Vector Select + [1:1] + + + PUD + Pull-up disable + [4:4] + + + JTD + JTAG Interface Disable + [7:7] + + + + + MCUSR + MCU Status Register + 0x16 + + + PORF + Power-on reset flag + [0:0] + + + EXTRF + External Reset Flag + [1:1] + + + BORF + Brown-out Reset Flag + [2:2] + + + WDRF + Watchdog Reset Flag + [3:3] + + + JTRF + JTAG Reset Flag + [4:4] + + + + + OSCCAL + Oscillator Calibration Value + 0x28 + + + OSCCAL + Oscillator Calibration + [7:0] + + + 0 + 255 + + + + + + + PRR0 + Power Reduction Register0 + 0x26 + + + PRADC + Power Reduction ADC + [0:0] + + + PRUSART0 + Power Reduction USART + [1:1] + + + PRSPI + Power Reduction Serial Peripheral Interface + [2:2] + + + PRTIM1 + Power Reduction Timer/Counter1 + [3:3] + + + PRTIM0 + Power Reduction Timer/Counter0 + [5:5] + + + PRTIM2 + Power Reduction Timer/Counter2 + [6:6] + + + PRTWI + Power Reduction TWI + [7:7] + + + + + PRR1 + Power Reduction Register1 + 0x27 + + + PRUSART1 + Power Reduction USART1 + [0:0] + + + PRTIM3 + Power Reduction Timer/Counter3 + [3:3] + + + PRTIM4 + Power Reduction Timer/Counter4 + [4:4] + + + PRUSB + Power Reduction USB + [7:7] + + + + + RAMPZ + Extended Z-pointer Register for ELPM/SPM + 0x1D + + + RAMPZ + Extended Z-Pointer Value + [1:0] + + true + + + + VAL_0 + Default value of Z-pointer MSB's. + 0 + + + + + Res + Reserved + [7:2] + + + 0 + 63 + + + + + + + RCCTRL + Oscillator Control Register + 0x29 + + + RCFREQ + <TBD> + [0:0] + + + + + SMCR + Sleep Mode Control Register + 0x15 + + + SE + Sleep Enable + [0:0] + + + SM + Sleep Mode Select bits + [3:1] + + true + + + + IDLE + Idle + 0 + + + ADC + ADC Noise Reduction (If Available) + 1 + + + PDOWN + Power Down + 2 + + + PSAVE + Power Save + 3 + + + VAL_0x04 + Reserved + 4 + + + VAL_0x05 + Reserved + 5 + + + STDBY + Standby + 6 + + + ESTDBY + Extended Standby + 7 + + + + + + + + + EEPROM + EEPROM + 0x3F + + + EEAR + EEPROM Address Register Low Bytes + 0x2 + 16 + + + 0 + 65535 + + + + + EECR + EEPROM Control Register + 0x0 + + + EERE + EEPROM Read Enable + [0:0] + + + EEPE + EEPROM Write Enable + [1:1] + + + EEMPE + EEPROM Master Write Enable + [2:2] + + + EERIE + EEPROM Ready Interrupt Enable + [3:3] + + + EEPM + EEPROM Programming Mode Bits + [5:4] + + true + + + + VAL_0x00 + Erase and Write in one operation + 0 + + + VAL_0x01 + Erase Only + 1 + + + VAL_0x02 + Write Only + 2 + + + + + + + EEDR + EEPROM Data Register + 0x1 + + + 0 + 255 + + + + + + + EXINT + External Interrupts + 0x3B + + + EICRA + External Interrupt Control Register A + 0x2E + + + ISC0 + External Interrupt Sense Control Bit + [1:0] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC1 + External Interrupt Sense Control Bit + [3:2] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC2 + External Interrupt Sense Control Bit + [5:4] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC3 + External Interrupt Sense Control Bit + [7:6] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + + + EICRB + External Interrupt Control Register B + 0x2F + + + ISC4 + External Interrupt 7-4 Sense Control Bit + [1:0] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC5 + External Interrupt 7-4 Sense Control Bit + [3:2] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC6 + External Interrupt 7-4 Sense Control Bit + [5:4] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC7 + External Interrupt 7-4 Sense Control Bit + [7:6] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + + + EIFR + External Interrupt Flag Register + 0x1 + read-only + + + INTF + External Interrupt Flags + [7:0] + + + 0 + 255 + + + + + + + EIMSK + External Interrupt Mask Register + 0x2 + + + INT + External Interrupt Request 7 Enable + [7:0] + + + 0 + 255 + + + + + + + PCICR + Pin Change Interrupt Control Register + 0x2D + + + PCIE0 + Pin Change Interrupt Enable 0 + [0:0] + + + + + PCIFR + Pin Change Interrupt Flag Register + 0x0 + read-only + + + PCIF0 + Pin Change Interrupt Flag 0 + [0:0] + + + + + PCMSK0 + Pin Change Mask Register 0 + 0x30 + + + 0 + 255 + + + + + + + FUSE + Fuses + 0x0 + + + EXTENDED + <TBD> + 0x2 + + + BODLEVEL + Brown-out Detector trigger level + [2:0] + + true + + + + 4V3 + Brown-out detection at VCC=4.3 V + 0 + + + 3V5 + Brown-out detection at VCC=3.5 V + 1 + + + 3V4 + Brown-out detection at VCC=3.4 V + 2 + + + 2V6 + Brown-out detection at VCC=2.6 V + 3 + + + 2V4 + Brown-out detection at VCC=2.4 V + 4 + + + 2V2 + Brown-out detection at VCC=2.2 V + 5 + + + 2V0 + Brown-out detection at VCC=2.0 V + 6 + + + DISABLED + Brown-out detection disabled; [BODLEVEL=111] + 7 + + + + + HWBE + Hardware Boot Enable + [3:3] + + + + + HIGH + <TBD> + 0x1 + + + BOOTRST + Boot Reset vector Enabled + [0:0] + + + BOOTSZ + Select Boot Size + [2:1] + + true + + + + 2048W_3800 + Boot Flash size=2048 words start address=$3800 + 0 + + + 1024W_3C00 + Boot Flash size=1024 words start address=$3C00 + 1 + + + 512W_3E00 + Boot Flash size=512 words start address=$3E00 + 2 + + + 256W_3F00 + Boot Flash size=256 words start address=$3F00 + 3 + + + + + EESAVE + Preserve EEPROM through the Chip Erase cycle + [3:3] + + + WDTON + Watchdog timer always on + [4:4] + + + SPIEN + Serial program downloading (SPI) enabled + [5:5] + + + JTAGEN + JTAG Interface Enabled + [6:6] + + + OCDEN + On-Chip Debug Enabled + [7:7] + + + + + LOW + <TBD> + 0x0 + + + SUT_CKSEL + Select Clock Source + [5:0] + + true + + + + EXTCLK_6CK_0MS + Ext. Clock; Start-up time: 6 CK + 0 ms + 0 + + + INTRCOSC_6CK_0MS + Int. RC Osc.; Start-up time: 6 CK + 0 ms + 2 + + + EXTLOFXTAL_1KCK_0MS + Ext. Low-Freq. Crystal; Start-up time: 1K CK + 0 ms + 4 + + + EXTLOFXTAL_32KCK_0MS + Ext. Low-Freq. Crystal; Start-up time: 32K CK + 0 ms + 5 + + + EXTLOFXTAL_1KCK_0MS_INTCAP + Ext. Low-Freq. Crystal; Start-up time: 1K CK + 0 ms; Int. Cap. + 6 + + + EXTLOFXTAL_32KCK_0MS_INTCAP + Ext. Low-Freq. Crystal; Start-up time: 32K CK + 0 ms; Int. Cap. + 7 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 258 CK + 4.1 ms + 8 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 65 ms + 9 + + + EXTXOSC_0MHZ9_3MHZ_258CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 258 CK + 4.1 ms + 10 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 65 ms + 11 + + + EXTXOSC_3MHZ_8MHZ_258CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 258 CK + 4.1 ms + 12 + + + EXTXOSC_3MHZ_8MHZ_1KCK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 65 ms + 13 + + + EXTXOSC_8MHZ_XX_258CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time: 258 CK + 4.1 ms + 14 + + + EXTXOSC_8MHZ_XX_1KCK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 65 ms + 15 + + + EXTCLK_6CK_4MS1 + Ext. Clock; Start-up time: 6 CK + 4.1 ms + 16 + + + INTRCOSC_6CK_4MS1 + Int. RC Osc.; Start-up time: 6 CK + 4.1 ms + 18 + + + EXTLOFXTAL_1KCK_4MS1 + Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4.1 ms + 20 + + + EXTLOFXTAL_32KCK_4MS1 + Ext. Low-Freq. Crystal; Start-up time: 32K CK + 4.1 ms + 21 + + + EXTLOFXTAL_1KCK_4MS1_INTCAP + Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4.1 ms; Int. Cap. + 22 + + + EXTLOFXTAL_32KCK_4MS1_INTCAP + Ext. Low-Freq. Crystal; Start-up time: 32K CK + 4.1 ms; Int. Cap. + 23 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 258 CK + 65 ms + 24 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 0 ms + 25 + + + EXTXOSC_0MHZ9_3MHZ_258CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 258 CK + 65 ms + 26 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 0 ms + 27 + + + EXTXOSC_3MHZ_8MHZ_258CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 258 CK + 65 ms + 28 + + + EXTXOSC_3MHZ_8MHZ_16KCK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 0 ms + 29 + + + EXTXOSC_8MHZ_XX_258CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 258 CK + 65 ms + 30 + + + EXTXOSC_8MHZ_XX_16KCK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 0 ms + 31 + + + EXTCLK_6CK_65MS + Ext. Clock; Start-up time: 6 CK + 65 ms + 32 + + + INTRCOSC_6CK_65MS + Int. RC Osc.; Start-up time: 6 CK + 65 ms + 34 + + + EXTLOFXTAL_1KCK_65MS + Ext. Low-Freq. Crystal; Start-up time: 1K CK + 65 ms + 36 + + + EXTLOFXTAL_32KCK_65MS + Ext. Low-Freq. Crystal; Start-up time: 32K CK + 65 ms + 37 + + + EXTLOFXTAL_1KCK_65MS_INTCAP + Ext. Low-Freq. Crystal; Start-up time: 1K CK + 65 ms; Int. Cap. + 38 + + + EXTLOFXTAL_32KCK_65MS_INTCAP + Ext. Low-Freq. Crystal; Start-up time: 32K CK + 65 ms; Int. Cap. + 39 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 0 ms + 40 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 4.1 ms + 41 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 0 ms + 42 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 4.1 ms + 43 + + + EXTXOSC_3MHZ_8MHZ_1KCK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 0 ms + 44 + + + EXTXOSC_3MHZ_8MHZ_16KCK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 4.1 ms + 45 + + + EXTXOSC_8MHZ_XX_1KCK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 0 ms + 46 + + + EXTXOSC_8MHZ_XX_16KCK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 4.1 ms + 47 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 4.1 ms + 56 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 65 ms + 57 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 4.1 ms + 58 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 65 ms + 59 + + + EXTXOSC_3MHZ_8MHZ_1KCK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 4.1 ms + 60 + + + EXTXOSC_3MHZ_8MHZ_16KCK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 65 ms + 61 + + + EXTXOSC_8MHZ_XX_1KCK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 4.1 ms + 62 + + + EXTXOSC_8MHZ_XX_16KCK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 65 ms + 63 + + + + + CKOUT + Clock output on PORTC7 + [6:6] + + + CKDIV8 + Divide clock by 8 internally + [7:7] + + + + + + + JTAG + JTAG Interface + 0x51 + + + MCUCR + MCU Control Register + 0x4 + + + JTD + JTAG Interface Disable + [7:7] + + + + + MCUSR + MCU Status Register + 0x3 + read-only + + + JTRF + JTAG Reset Flag + [4:4] + + + + + OCDR + On-Chip Debug Related Register in I/O Memory + 0x0 + + + 0 + 255 + + + + + + + LOCKBIT + Lockbits + 0x0 + + + LOCKBIT + <TBD> + 0x0 + + + LB + Memory Lock + [1:0] + + true + + + + PROG_VER_DISABLED + Further programming and verification disabled + 0 + + + PROG_DISABLED + Further programming disabled + 2 + + + NO_LOCK + No memory lock features enabled + 3 + + + + + BLB0 + Boot Loader Protection Mode + [3:2] + + true + + + + LPM_SPM_DISABLE + LPM and SPM prohibited in Application Section + 0 + + + LPM_DISABLE + LPM prohibited in Application Section + 1 + + + SPM_DISABLE + SPM prohibited in Application Section + 2 + + + NO_LOCK + No lock on SPM and LPM in Application Section + 3 + + + + + BLB1 + Boot Loader Protection Mode + [5:4] + + true + + + + LPM_SPM_DISABLE + LPM and SPM prohibited in Boot Section + 0 + + + LPM_DISABLE + LPM prohibited in Boot Section + 1 + + + SPM_DISABLE + SPM prohibited in Boot Section + 2 + + + NO_LOCK + No lock on SPM and LPM in Boot Section + 3 + + + + + + + + + PLL + Phase Locked Loop + 0x49 + + + PLLCSR + PLL Status and Control register + 0x0 + + + PLOCK + PLL Lock Status Bit + [0:0] + read-only + + PLLE + PLL Enable Bit + [1:1] + + + PINDIV + PLL prescaler Bit 2 + [4:4] + + + + + PLLFRQ + PLL Frequency Control Register + 0x9 + + + PDIV + PLL Lock Frequency + [3:0] + PDIVread-writeMHZ4040 MHz3MHZ4848 MHz4MHZ5656 MHz5MHZ7272 MHz7MHZ8080 MHz8MHZ8888 MHz9MHZ9696 MHz10 + + + PLLTM + PLL Postscaler for High Speed Timer + [5:4] + + true + PLLTMread-writeDISCONNECTED0 (Disconnected)0FACTOR_111FACTOR_151.52FACTOR_223 + + + PLLUSB + PLL Postscaler for USB Peripheral + [6:6] + + + PINMUX + PLL Input Multiplexer + [7:7] + + + + + + + PORTB + I/O Port + 0x23 + + + DDRB + Port B Data Direction Register + 0x1 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PINB + Port B Input Pins + 0x0 + read-write + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PORTB + Port B Data Register + 0x2 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + + + PORTC + I/O Port + 0x26 + + + DDRC + Port C Data Direction Register + 0x1 + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + PINC + Port C Input Pins + 0x0 + read-write + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + PORTC + Port C Data Register + 0x2 + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + + + PORTD + I/O Port + 0x29 + + + DDRD + Port D Data Direction Register + 0x1 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PIND + Port D Input Pins + 0x0 + read-write + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PORTD + Port D Data Register + 0x2 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + + + PORTE + I/O Port + 0x2C + + + DDRE + Data Direction Register, Port E + 0x1 + + + PE2 + Pin E2 + [2:2] + + + PE6 + Pin E6 + [6:6] + + + + + PINE + Input Pins, Port E + 0x0 + read-write + + + PE2 + Pin E2 + [2:2] + + + PE6 + Pin E6 + [6:6] + + + + + PORTE + Data Register, Port E + 0x2 + + + PE2 + Pin E2 + [2:2] + + + PE6 + Pin E6 + [6:6] + + + + + + + PORTF + I/O Port + 0x2F + + + DDRF + Data Direction Register, Port F + 0x1 + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + + + PINF + Input Pins, Port F + 0x0 + read-write + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + + + PORTF + Data Register, Port F + 0x2 + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + + + + + SPI + Serial Peripheral Interface + 0x4C + + + SPCR + SPI Control Register + 0x0 + + + SPR + SPI Clock Rate Selects + [1:0] + + true + + SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 + + + CPHA + Clock Phase + [2:2] + + + CPOL + Clock polarity + [3:3] + + + MSTR + Master/Slave Select + [4:4] + + + DORD + Data Order + [5:5] + + + SPE + SPI Enable + [6:6] + + + SPIE + SPI Interrupt Enable + [7:7] + + + + + SPDR + SPI Data Register + 0x2 + + + 0 + 255 + + + + + SPSR + SPI Status Register + 0x1 + read-write + + + SPI2X + Double SPI Speed Bit + [0:0] + read-write + + WCOL + Write Collision Flag + [6:6] + read-only + + SPIF + SPI Interrupt Flag + [7:7] + read-only + + + + + + TC0 + Timer/Counter, 8-bit + 0x35 + + + GTCCR + General Timer/Counter Control Register + 0xE + + + PSRSYNC + Prescaler Reset Timer/Counter1 and Timer/Counter0 + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + OCR0A + Timer/Counter0 Output Compare Register + 0x12 + + + 0 + 255 + + + + + OCR0B + Timer/Counter0 Output Compare Register + 0x13 + + + 0 + 255 + + + + + TCCR0A + Timer/Counter Control Register A + 0xF + + + WGM0 + Waveform Generation Mode + [1:0] + + true + WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 + + + COM0B + Compare Output B Mode + [5:4] + + true + COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 + + + COM0A + Compare Output A Mode + [7:6] + + true + + + + + + TCCR0B + Timer/Counter Control Register B + 0x10 + + + CS0 + Clock Select + [2:0] + + true + + CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM02 + Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) + [3:3] + + + FOC0B + Force Output Compare B + [6:6] + write-only + + FOC0A + Force Output Compare A + [7:7] + write-only + + + + TCNT0 + Timer/Counter0 + 0x11 + + + 0 + 255 + + + + + TIFR0 + Timer/Counter0 Interrupt Flag register + 0x0 + read-write + + + TOV0 + Timer/Counter0 Overflow Flag + [0:0] + + + OCF0A + Timer/Counter0 Output Compare Flag 0A + [1:1] + + + OCF0B + Timer/Counter0 Output Compare Flag 0B + [2:2] + + + + + TIMSK0 + Timer/Counter0 Interrupt Mask Register + 0x39 + + + TOIE0 + Timer/Counter0 Overflow Interrupt Enable + [0:0] + + + OCIE0A + Timer/Counter0 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE0B + Timer/Counter0 Output Compare Match B Interrupt Enable + [2:2] + + + + + + + TC1 + Timer/Counter, 16-bit + 0x36 + + + ICR1 + Timer/Counter1 Input Capture Register Bytes + 0x50 + 16 + + + 0 + 65535 + + + + + OCR1A + Timer/Counter1 Output Compare Register A Bytes + 0x52 + 16 + + + 0 + 65535 + + + + + OCR1B + Timer/Counter1 Output Compare Register B Bytes + 0x54 + 16 + + + 0 + 65535 + + + + + OCR1C + Timer/Counter1 Output Compare Register C Bytes + 0x56 + 16 + + + 0 + 65535 + + + + + TCCR1A + Timer/Counter1 Control Register A + 0x4A + + + WGM1 + Waveform Generation Mode + [1:0] + + + 0 + 3 + + + + + COM1C + Compare Output Mode 1C, bits + [3:2] + + true + COM1Cread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM1B + Compare Output Mode 1B, bits + [5:4] + + true + + + + COM1A + Compare Output Mode 1A, bits + [7:6] + + true + + + + + + TCCR1B + Timer/Counter1 Control Register B + 0x4B + + + CS1 + Prescaler source of Timer/Counter 1 + [2:0] + + true + CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM1 + Waveform Generation Mode + [4:3] + + + 0 + 3 + + + + + ICES1 + Input Capture 1 Edge Select + [6:6] + + + ICNC1 + Input Capture 1 Noise Canceler + [7:7] + + + + + TCCR1C + Timer/Counter 1 Control Register C + 0x4C + + + FOC1C + Force Output Compare 1C + [5:5] + write-only + + FOC1B + Force Output Compare 1B + [6:6] + write-only + + FOC1A + Force Output Compare 1A + [7:7] + write-only + + + + TCNT1 + Timer/Counter1 Bytes + 0x4E + 16 + + + 0 + 65535 + + + + + TIFR1 + Timer/Counter1 Interrupt Flag register + 0x0 + read-write + + + TOV1 + Timer/Counter1 Overflow Flag + [0:0] + + + OCF1A + Output Compare Flag 1A + [1:1] + + + OCF1B + Output Compare Flag 1B + [2:2] + + + OCF1C + Output Compare Flag 1C + [3:3] + + + ICF1 + Input Capture Flag 1 + [5:5] + + + + + TIMSK1 + Timer/Counter1 Interrupt Mask Register + 0x39 + + + TOIE1 + Timer/Counter1 Overflow Interrupt Enable + [0:0] + + + OCIE1A + Timer/Counter1 Output Compare A Match Interrupt Enable + [1:1] + + + OCIE1B + Timer/Counter1 Output Compare B Match Interrupt Enable + [2:2] + + + OCIE1C + Timer/Counter1 Output Compare C Match Interrupt Enable + [3:3] + + + ICIE1 + Timer/Counter1 Input Capture Interrupt Enable + [5:5] + + + + + + + TC3 + Timer/Counter, 16-bit + 0x38 + + + ICR3 + Timer/Counter3 Input Capture Register Bytes + 0x5E + 16 + + + 0 + 65535 + + + + + OCR3A + Timer/Counter3 Output Compare Register A Bytes + 0x60 + 16 + + + 0 + 65535 + + + + + OCR3B + Timer/Counter3 Output Compare Register B Bytes + 0x62 + 16 + + + 0 + 65535 + + + + + OCR3C + Timer/Counter3 Output Compare Register B Bytes + 0x64 + 16 + + + 0 + 65535 + + + + + TCCR3A + Timer/Counter3 Control Register A + 0x58 + + + WGM3 + Waveform Generation Mode + [1:0] + + + 0 + 3 + + + + + COM3C + Compare Output Mode 3C, bits + [3:2] + + true + COM3Cread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM3B + Compare Output Mode 3B, bits + [5:4] + + true + + + + COM3A + Compare Output Mode 1A, bits + [7:6] + + true + + + + + + TCCR3B + Timer/Counter3 Control Register B + 0x59 + + + CS3 + Prescaler source of Timer/Counter 3 + [2:0] + + true + CS3read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM3 + Waveform Generation Mode + [4:3] + + + 0 + 3 + + + + + ICES3 + Input Capture 3 Edge Select + [6:6] + + + ICNC3 + Input Capture 3 Noise Canceler + [7:7] + + + + + TCCR3C + Timer/Counter 3 Control Register C + 0x5A + + + FOC3C + Force Output Compare 3C + [5:5] + write-only + + FOC3B + Force Output Compare 3B + [6:6] + write-only + + FOC3A + Force Output Compare 3A + [7:7] + write-only + + + + TCNT3 + Timer/Counter3 Bytes + 0x5C + 16 + + + 0 + 65535 + + + + + TIFR3 + Timer/Counter3 Interrupt Flag register + 0x0 + read-write + + + TOV3 + Timer/Counter3 Overflow Flag + [0:0] + + + OCF3A + Output Compare Flag 3A + [1:1] + + + OCF3B + Output Compare Flag 3B + [2:2] + + + OCF3C + Output Compare Flag 3C + [3:3] + + + ICF3 + Input Capture Flag 3 + [5:5] + + + + + TIMSK3 + Timer/Counter3 Interrupt Mask Register + 0x39 + + + TOIE3 + Timer/Counter3 Overflow Interrupt Enable + [0:0] + + + OCIE3A + Timer/Counter3 Output Compare A Match Interrupt Enable + [1:1] + + + OCIE3B + Timer/Counter3 Output Compare B Match Interrupt Enable + [2:2] + + + OCIE3C + Timer/Counter3 Output Compare C Match Interrupt Enable + [3:3] + + + ICIE3 + Timer/Counter3 Input Capture Interrupt Enable + [5:5] + + + + + + + TC4 + Timer/Counter, 10-bit + 0x39 + + + DT4 + Timer/Counter 4 Dead Time Value + 0x9B + + + DT4L + Timer/Counter 4 Dead Time Value Bits + [7:0] + + + 0 + 255 + + + + + + + OCR4A + Timer/Counter4 Output Compare Register A + 0x96 + + + 0 + 255 + + + + + OCR4B + Timer/Counter4 Output Compare Register B + 0x97 + + + 0 + 255 + + + + + OCR4C + Timer/Counter4 Output Compare Register C + 0x98 + + + 0 + 255 + + + + + OCR4D + Timer/Counter4 Output Compare Register D + 0x99 + + + 0 + 255 + + + + + TC4H + Timer/Counter High Bits + 0x86 + + + 0 + 255 + + + + + TCCR4A + Timer/Counter4 Control Register A + 0x87 + + + PWM4B + <TBD> + [0:0] + + + PWM4A + <TBD> + [1:1] + + + FOC4B + Force Output Compare Match 4B + [2:2] + write-only + + FOC4A + Force Output Compare Match 4A + [3:3] + write-only + + COM4B + Compare Output Mode 4B, bits + [5:4] + + true + COM4Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 + + + COM4A + Compare Output Mode 1A, bits + [7:6] + + true + + + + + + TCCR4B + Timer/Counter4 Control Register B + 0x88 + + + CS4 + Clock Select Bits + [3:0] + + true + CS4read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_2Running, CLK/22PRESCALE_4Running, CLK/43PRESCALE_8Running, CLK/84PRESCALE_16Running, CLK/165PRESCALE_32Running, CLK/326PRESCALE_64Running, CLK/647PRESCALE_128Running, CLK/1288PRESCALE_256Running, CLK/2569PRESCALE_512Running, CLK/51210PRESCALE_1024Running, CLK/102411PRESCALE_2048Running, CLK/204812PRESCALE_4096Running, CLK/409613PRESCALE_8192Running, CLK/819214PRESCALE_16384Running, CLK/1638415 + + + DTPS4 + Dead Time Prescaler Bits + [5:4] + + + 0 + 3 + + + DTPS4read-writeX11x (no division)0X22x1X44x2X88x3 + + + PSR4 + Prescaler Reset Timer/Counter 4 + [6:6] + + + PWM4X + PWM Inversion Mode + [7:7] + + + + + TCCR4C + Timer/Counter 4 Control Register C + 0x89 + + + PWM4D + Pulse Width Modulator D Enable + [0:0] + + + FOC4D + Force Output Compare Match 4D + [1:1] + write-only + + COM4D + Comparator D Output Mode + [3:2] + + true + COM4Dread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 + + + COM4B0S + Comparator B Output Mode + [4:4] + + + COM4B1S + Comparator B Output Mode + [5:5] + + + COM4A0S + Comparator A Output Mode + [6:6] + + + COM4A1S + Comparator A Output Mode + [7:7] + + + + + TCCR4D + Timer/Counter 4 Control Register D + 0x8A + + + WGM4 + Waveform Generation Mode bits + [1:0] + + true + WGM4read-writePWM_FASTFast PWM, Update: *TOP*, Flag: *TOP*0PWM_CORRECTPhase and Frequency Correct PWM, Update: *BOTTOM*, Flag: *BOTTOM*1PWM_SINGLE_SLOPEPWM6 / Single-slope, Update: *TOP*, Flag: *TOP*2PWM_DUAL_SLOPEPWM6 / Dual-slope, Update: *BOTTOM*, Flag: *BOTTOM*3 + + + FPF4 + Fault Protection Interrupt Flag + [2:2] + + + FPAC4 + Fault Protection Analog Comparator Enable + [3:3] + + + FPES4 + Fault Protection Edge Select + [4:4] + + + FPNC4 + Fault Protection Noise Canceler + [5:5] + + + FPEN4 + Fault Protection Mode Enable + [6:6] + + + FPIE4 + Fault Protection Interrupt Enable + [7:7] + + + + + TCCR4E + Timer/Counter 4 Control Register E + 0x8B + + + OC4OE + Output Compare Override Enable bit + [5:0] + + + 0 + 63 + + + + + ENHC4 + Enhanced Compare/PWM Mode + [6:6] + + + TLOCK4 + Register Update Lock + [7:7] + + + + + TCNT4 + Timer/Counter4 Low Bytes + 0x85 + + + 0 + 255 + + + + + TIFR4 + Timer/Counter4 Interrupt Flag register + 0x0 + read-only + + + TOV4 + Timer/Counter4 Overflow Flag + [2:2] + + + OCF4B + Output Compare Flag 4B + [5:5] + + + OCF4A + Output Compare Flag 4A + [6:6] + + + OCF4D + Output Compare Flag 4D + [7:7] + + + + + TIMSK4 + Timer/Counter4 Interrupt Mask Register + 0x39 + + + TOIE4 + Timer/Counter4 Overflow Interrupt Enable + [2:2] + + + OCIE4B + Timer/Counter4 Output Compare B Match Interrupt Enable + [5:5] + + + OCIE4A + Timer/Counter4 Output Compare A Match Interrupt Enable + [6:6] + + + OCIE4D + Timer/Counter4 Output Compare D Match Interrupt Enable + [7:7] + + + + + + + TWI + Two Wire Serial Interface + 0xB8 + + + TWAMR + TWI (Slave) Address Mask Register + 0x5 + + + TWAM + TWI (Slave) Address Mask Bits + [7:1] + + + 0 + 127 + + + + + + + TWAR + TWI (Slave) Address register + 0x2 + + + TWGCE + TWI General Call Recognition Enable Bit + [0:0] + + + TWA + TWI (Slave) Address register Bits + [7:1] + + + 0 + 127 + + + + + + + TWBR + TWI Bit Rate register + 0x0 + + + 0 + 255 + + + + + TWCR + TWI Control Register + 0x4 + read-write + + + TWIE + TWI Interrupt Enable + [0:0] + + + TWEN + TWI Enable Bit + [2:2] + + + TWWC + TWI Write Collition Flag + [3:3] + read-only + + TWSTO + TWI Stop Condition Bit + [4:4] + + + TWSTA + TWI Start Condition Bit + [5:5] + + + TWEA + TWI Enable Acknowledge Bit + [6:6] + + + TWINT + TWI Interrupt Flag + [7:7] + + + + + TWDR + TWI Data register + 0x3 + + + 0 + 255 + + + + + TWSR + TWI Status Register + 0x1 + + + TWPS + TWI Prescaler + [1:0] + + true + + TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 + + + TWS + TWI Status + [7:3] + read-only + + 0 + 31 + + + + + + + + + USART1 + USART + 0xC8 + + + UBRR1 + USART Baud Rate Register Bytes + 0x4 + 16 + + + 0 + 65535 + + + + + UCSR1A + USART Control and Status Register A + 0x0 + read-write + + + MPCM1 + Multi-processor Communication Mode + [0:0] + + + U2X1 + Double the USART transmission speed + [1:1] + + + UPE1 + Parity Error + [2:2] + read-only + + DOR1 + Data overRun + [3:3] + read-only + + FE1 + Framing Error + [4:4] + read-only + + UDRE1 + USART Data Register Empty + [5:5] + read-only + + TXC1 + USART Transmit Complete + [6:6] + + + RXC1 + USART Receive Complete + [7:7] + read-only + + + + UCSR1B + USART Control and Status Register B + 0x1 + + + TXB81 + Transmit Data Bit 8 + [0:0] + + + RXB81 + Receive Data Bit 8 + [1:1] + read-only + + UCSZ12 + Character Size + [2:2] + + + TXEN1 + Transmitter Enable + [3:3] + + + RXEN1 + Receiver Enable + [4:4] + + + UDRIE1 + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE1 + TX Complete Interrupt Enable + [6:6] + + + RXCIE1 + RX Complete Interrupt Enable + [7:7] + + + + + UCSR1C + USART Control and Status Register C + 0x2 + + + UCPOL1 + Clock Polarity + [0:0] + UCPOL1read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 + + + UCSZ1 + Character Size + [2:1] + + + 0 + 3 + + + UCSZ1read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 + + + USBS1 + Stop Bit Select + [3:3] + + true + + USBS1read-writeSTOP11-bit0STOP22-bit1 + + + UPM1 + Parity Mode Bits + [5:4] + + true + + UPM1read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 + + + UMSEL1 + USART Mode Select + [7:6] + + true + + UMSEL1read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 + + + + + UCSR1D + USART Control and Status Register D + 0x3 + + + RTSEN + RTS Enable + [0:0] + + + CTSEN + CTS Enable + [1:1] + + + + + UDR1 + USART I/O Data Register + 0x6 + + + 0 + 255 + + + + + + + USB_DEVICE + USB Device Registers + 0xD7 + + + UDADDR + <TBD> + 0xC + + + UADD + <TBD> + [6:0] + + + 0 + 127 + + + + + ADDEN + <TBD> + [7:7] + + + + + UDCON + <TBD> + 0x9 + + + DETACH + <TBD> + [0:0] + + + RMWKUP + <TBD> + [1:1] + + + LSM + USB low speed mode + [2:2] + + + RSTCPU + <TBD> + [3:3] + + + + + UDFNUM + <TBD> + 0xD + 16 + + + 0 + 65535 + + + + + UDIEN + <TBD> + 0xB + + + SUSPE + <TBD> + [0:0] + + + SOFE + <TBD> + [2:2] + + + EORSTE + <TBD> + [3:3] + + + WAKEUPE + <TBD> + [4:4] + + + EORSME + <TBD> + [5:5] + + + UPRSME + <TBD> + [6:6] + + + + + UDINT + <TBD> + 0xA + + + SUSPI + <TBD> + [0:0] + + + SOFI + <TBD> + [2:2] + + + EORSTI + <TBD> + [3:3] + + + WAKEUPI + <TBD> + [4:4] + + + EORSMI + <TBD> + [5:5] + + + UPRSMI + <TBD> + [6:6] + + + + + UDMFN + <TBD> + 0xF + read-only + + + FNCERR + <TBD> + [4:4] + + + + + UEBCHX + <TBD> + 0x1C + read-only + + + 0 + 255 + + + + + UEBCLX + <TBD> + 0x1B + read-only + + + 0 + 255 + + + + + UECFG0X + <TBD> + 0x15 + + + EPDIR + <TBD> + [0:0] + + + EPTYPE + <TBD> + [7:6] + + + 0 + 3 + + + + + + + UECFG1X + <TBD> + 0x16 + + + ALLOC + <TBD> + [1:1] + + + EPBK + <TBD> + [3:2] + + + 0 + 3 + + + + + EPSIZE + <TBD> + [6:4] + + + 0 + 7 + + + + + + + UECONX + <TBD> + 0x14 + + + EPEN + <TBD> + [0:0] + + + RSTDT + <TBD> + [3:3] + + + STALLRQC + <TBD> + [4:4] + + + STALLRQ + <TBD> + [5:5] + + + + + UEDATX + <TBD> + 0x1A + + + DAT + <TBD> + [7:0] + + + 0 + 255 + + + + + + + UEIENX + <TBD> + 0x19 + + + TXINE + <TBD> + [0:0] + + + STALLEDE + <TBD> + [1:1] + + + RXOUTE + <TBD> + [2:2] + + + RXSTPE + <TBD> + [3:3] + + + NAKOUTE + <TBD> + [4:4] + + + NAKINE + <TBD> + [6:6] + + + FLERRE + <TBD> + [7:7] + + + + + UEINT + <TBD> + 0x1D + + + 0 + 255 + + + + + UEINTX + <TBD> + 0x11 + + + TXINI + <TBD> + [0:0] + + + STALLEDI + <TBD> + [1:1] + + + RXOUTI + <TBD> + [2:2] + + + RXSTPI + <TBD> + [3:3] + + + NAKOUTI + <TBD> + [4:4] + + + RWAL + <TBD> + [5:5] + + + NAKINI + <TBD> + [6:6] + + + FIFOCON + <TBD> + [7:7] + + + + + UENUM + <TBD> + 0x12 + + + 0 + 255 + + + + + UERST + <TBD> + 0x13 + + + EPRST + <TBD> + [6:0] + + + 0 + 127 + + + + + + + UESTA0X + <TBD> + 0x17 + + + NBUSYBK + <TBD> + [1:0] + + + 0 + 3 + + + + + DTSEQ + <TBD> + [3:2] + + + 0 + 3 + + + + + UNDERFI + <TBD> + [5:5] + + + OVERFI + <TBD> + [6:6] + + + CFGOK + <TBD> + [7:7] + + + + + UESTA1X + <TBD> + 0x18 + read-only + + + CURRBK + <TBD> + [1:0] + + + 0 + 3 + + + + + CTRLDIR + <TBD> + [2:2] + + + + + UHWCON + <TBD> + 0x0 + + + UVREGE + <TBD> + [0:0] + + + + + USBCON + USB General Control Register + 0x1 + + + VBUSTE + <TBD> + [0:0] + + + OTGPADE + <TBD> + [4:4] + + + FRZCLK + <TBD> + [5:5] + + + USBE + <TBD> + [7:7] + + + + + USBINT + <TBD> + 0x3 + + + VBUSTI + <TBD> + [0:0] + + + + + USBSTA + <TBD> + 0x2 + read-only + + + VBUS + <TBD> + [0:0] + + + SPEED + <TBD> + [3:3] + + + + + + + WDT + Watchdog Timer + 0x60 + + + WDTCSR + Watchdog Timer Control Register + 0x0 + read-write + + + WDE + Watch Dog Enable + [3:3] + + + WDCE + Watchdog Change Enable + [4:4] + + + WDIE + Watchdog Timeout Interrupt Enable + [6:6] + + + WDIF + Watchdog Timeout Interrupt Flag + [7:7] + + WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 + + WDPHWatchdog Timer Prescaler - High Bit[5:5] + + + + + + \ No newline at end of file diff --git a/misc/svd/atmega4809.svd b/misc/svd/atmega4809.svd new file mode 100644 index 0000000..cfba676 --- /dev/null +++ b/misc/svd/atmega4809.svd @@ -0,0 +1,18369 @@ + + Atmel + ATmega4809 + 8 + 8 + read-write + 0 + 0xff + + + AC0 + Analog Comparator + 0x680 + + + CTRLA + Control A + 0x0 + + + ENABLE + Enable + [0:0] + + + HYSMODE + Hysteresis Mode + [2:1] + + true + + + + OFF + No hysteresis + 0 + + + 10mV + 10mV hysteresis + 1 + + + 25mV + 25mV hysteresis + 2 + + + 50mV + 50mV hysteresis + 3 + + + + + LPMODE + Low Power Mode + [3:3] + + true + + + + DIS + Low power mode disabled + 0 + + + EN + Low power mode enabled + 1 + + + + + INTMODE + Interrupt Mode + [5:4] + + true + + + + BOTHEDGE + Any Edge + 0 + + + NEGEDGE + Negative Edge + 2 + + + POSEDGE + Positive Edge + 3 + + + + + OUTEN + Output Buffer Enable + [6:6] + + + RUNSTDBY + Run in Standby Mode + [7:7] + + + + + DACREF + Referance scale control + 0x4 + + + DATA + DAC voltage reference + [7:0] + + + 0 + 255 + + + + + + + INTCTRL + Interrupt Control + 0x6 + + + CMP + Analog Comparator 0 Interrupt Enable + [0:0] + + + + + MUXCTRLA + Mux Control A + 0x2 + + + MUXNEG + Negative Input MUX Selection + [1:0] + + true + + + + PIN0 + Negative Pin 0 + 0 + + + PIN1 + Negative Pin 1 + 1 + + + PIN2 + Negative Pin 2 + 2 + + + DACREF + DAC Voltage Reference + 3 + + + + + MUXPOS + Positive Input MUX Selection + [4:3] + + true + + + + PIN0 + Positive Pin 0 + 0 + + + PIN1 + Positive Pin 1 + 1 + + + PIN2 + Positive Pin 2 + 2 + + + PIN3 + Positive Pin 3 + 3 + + + + + INVERT + Invert AC Output + [7:7] + + + + + STATUS + Status + 0x7 + + + CMP + Analog Comparator Interrupt Flag + [0:0] + + + STATE + Analog Comparator State + [4:4] + read-only + + + + + + + ADC0 + Analog to Digital Converter + 0x600 + + + CALIB + Calibration + 0x16 + + + DUTYCYC + Duty Cycle + [0:0] + + true + + + + DUTY50 + 50% Duty cycle + 0 + + + DUTY25 + 25% Duty cycle + 1 + + + + + + + COMMAND + Command + 0x8 + + + STCONV + Start Conversion Operation + [0:0] + + + + + CTRLA + Control A + 0x0 + + + ENABLE + ADC Enable + [0:0] + + + FREERUN + ADC Freerun mode + [1:1] + + + RESSEL + ADC Resolution + [2:2] + + true + + + + 10BIT + 10-bit mode + 0 + + + 8BIT + 8-bit mode + 1 + + + + + RUNSTBY + Run standby mode + [7:7] + + + + + CTRLB + Control B + 0x1 + + + SAMPNUM + Accumulation Samples + [2:0] + + true + + + + ACC1 + 1 ADC sample + 0 + + + ACC2 + Accumulate 2 samples + 1 + + + ACC4 + Accumulate 4 samples + 2 + + + ACC8 + Accumulate 8 samples + 3 + + + ACC16 + Accumulate 16 samples + 4 + + + ACC32 + Accumulate 32 samples + 5 + + + ACC64 + Accumulate 64 samples + 6 + + + + + + + CTRLC + Control C + 0x2 + + + PRESC + Clock Pre-scaler + [2:0] + + true + + + + DIV2 + CLK_PER divided by 2 + 0 + + + DIV4 + CLK_PER divided by 4 + 1 + + + DIV8 + CLK_PER divided by 8 + 2 + + + DIV16 + CLK_PER divided by 16 + 3 + + + DIV32 + CLK_PER divided by 32 + 4 + + + DIV64 + CLK_PER divided by 64 + 5 + + + DIV128 + CLK_PER divided by 128 + 6 + + + DIV256 + CLK_PER divided by 256 + 7 + + + + + REFSEL + Reference Selection + [5:4] + + true + + + + INTREF + Internal reference + 0 + + + VDDREF + VDD + 1 + + + VREFA + External reference + 2 + + + + + SAMPCAP + Sample Capacitance Selection + [6:6] + + + + + CTRLD + Control D + 0x3 + + + SAMPDLY + Sampling Delay Selection + [3:0] + + + 0 + 15 + + + + + ASDV + Automatic Sampling Delay Variation + [4:4] + + true + + + + ASVOFF + The Automatic Sampling Delay Variation is disabled + 0 + + + ASVON + The Automatic Sampling Delay Variation is enabled + 1 + + + + + INITDLY + Initial Delay Selection + [7:5] + + true + + + + DLY0 + Delay 0 CLK_ADC cycles + 0 + + + DLY16 + Delay 16 CLK_ADC cycles + 1 + + + DLY32 + Delay 32 CLK_ADC cycles + 2 + + + DLY64 + Delay 64 CLK_ADC cycles + 3 + + + DLY128 + Delay 128 CLK_ADC cycles + 4 + + + DLY256 + Delay 256 CLK_ADC cycles + 5 + + + + + + + CTRLE + Control E + 0x4 + + + WINCM + Window Comparator Mode + [2:0] + + true + + + + NONE + No Window Comparison + 0 + + + BELOW + Below Window + 1 + + + ABOVE + Above Window + 2 + + + INSIDE + Inside Window + 3 + + + OUTSIDE + Outside Window + 4 + + + + + + + DBGCTRL + Debug Control + 0xC + + + DBGRUN + Debug run + [0:0] + + + + + EVCTRL + Event Control + 0x9 + + + STARTEI + Start Event Input Enable + [0:0] + + + + + INTCTRL + Interrupt Control + 0xA + + + RESRDY + Result Ready Interrupt Enable + [0:0] + + + WCMP + Window Comparator Interrupt Enable + [1:1] + + + + + INTFLAGS + Interrupt Flags + 0xB + + + RESRDY + Result Ready Flag + [0:0] + + + WCMP + Window Comparator Flag + [1:1] + + + + + MUXPOS + Positive mux input + 0x6 + + + MUXPOS + Analog Channel Selection Bits + [4:0] + + true + + + + AIN0 + ADC input pin 0 + 0 + + + AIN1 + ADC input pin 1 + 1 + + + AIN2 + ADC input pin 2 + 2 + + + AIN3 + ADC input pin 3 + 3 + + + AIN4 + ADC input pin 4 + 4 + + + AIN5 + ADC input pin 5 + 5 + + + AIN6 + ADC input pin 6 + 6 + + + AIN7 + ADC input pin 7 + 7 + + + AIN8 + ADC input pin 8 + 8 + + + AIN9 + ADC input pin 9 + 9 + + + AIN10 + ADC input pin 10 + 10 + + + AIN11 + ADC input pin 11 + 11 + + + AIN12 + ADC input pin 12 + 12 + + + AIN13 + ADC input pin 13 + 13 + + + AIN14 + ADC input pin 14 + 14 + + + AIN15 + ADC input pin 15 + 15 + + + DACREF + AC DAC Reference + 28 + + + TEMPSENSE + Temperature sensor + 30 + + + GND + 0V (GND) + 31 + + + + + + + RES + ADC Accumulator Result + 0x10 + 16 + + + 0 + 65535 + + + + + SAMPCTRL + Sample Control + 0x5 + + + SAMPLEN + Sample lenght + [4:0] + + + 0 + 31 + + + + + + + TEMP + Temporary Data + 0xD + + + TEMP + Temporary + [7:0] + + + 0 + 255 + + + + + + + WINHT + Window comparator high threshold + 0x14 + 16 + + + 0 + 65535 + + + + + WINLT + Window comparator low threshold + 0x12 + 16 + + + 0 + 65535 + + + + + + + BOD + Bod interface + 0x80 + + + CTRLA + Control A + 0x0 + + + SLEEP + Operation in sleep mode + [1:0] + + true + + + + DIS + Disabled + 0 + + + ENABLED + Enabled + 1 + + + SAMPLED + Sampled + 2 + + + + + ACTIVE + Operation in active mode + [3:2] + read-only + + true + + + + DIS + Disabled + 0 + + + ENABLED + Enabled + 1 + + + SAMPLED + Sampled + 2 + + + ENWAKE + Enabled with wake-up halted until BOD is ready + 3 + + + + + SAMPFREQ + Sample frequency + [4:4] + read-only + + true + + + + 1KHZ + 1kHz sampling frequency + 0 + + + 125HZ + 125Hz sampling frequency + 1 + + + + + + + CTRLB + Control B + 0x1 + + + LVL + Bod level + [2:0] + read-only + + true + + + + BODLEVEL0 + 1.8 V + 0 + + + BODLEVEL2 + 2.6 V + 2 + + + BODLEVEL7 + 4.2 V + 7 + + + + + + + INTCTRL + Voltage level monitor interrupt Control + 0x9 + + + VLMIE + voltage level monitor interrrupt enable + [0:0] + + + VLMCFG + Configuration + [2:1] + + true + + + + BELOW + Interrupt when supply goes below VLM level + 0 + + + ABOVE + Interrupt when supply goes above VLM level + 1 + + + CROSS + Interrupt when supply crosses VLM level + 2 + + + + + + + INTFLAGS + Voltage level monitor interrupt Flags + 0xA + + + VLMIF + Voltage level monitor interrupt flag + [0:0] + + + + + STATUS + Voltage level monitor status + 0xB + + + VLMS + Voltage level monitor status + [0:0] + read-only + + + + + VLMCTRLA + Voltage level monitor Control + 0x8 + + + VLMLVL + voltage level monitor level + [1:0] + + true + + + + 5ABOVE + VLM threshold 5% above BOD level + 0 + + + 15ABOVE + VLM threshold 15% above BOD level + 1 + + + 25ABOVE + VLM threshold 25% above BOD level + 2 + + + + + + + + + CCL + Configurable Custom Logic + 0x1C0 + + + CTRLA + Control Register A + 0x0 + + + ENABLE + Enable + [0:0] + + + RUNSTDBY + Run in Standby + [6:6] + + + + + INTCTRL0 + Interrupt Control 0 + 0x5 + + + INTMODE0 + Interrupt Mode for LUT0 + [1:0] + + true + + + + INTDISABLE + Interrupt disabled + 0 + + + RISING + Sense rising edge + 1 + + + FALLING + Sense falling edge + 2 + + + BOTH + Sense both edges + 3 + + + + + INTMODE1 + Interrupt Mode for LUT1 + [3:2] + + true + + + + INTDISABLE + Interrupt disabled + 0 + + + RISING + Sense rising edge + 1 + + + FALLING + Sense falling edge + 2 + + + BOTH + Sense both edges + 3 + + + + + INTMODE2 + Interrupt Mode for LUT2 + [5:4] + + true + + + + INTDISABLE + Interrupt disabled + 0 + + + RISING + Sense rising edge + 1 + + + FALLING + Sense falling edge + 2 + + + BOTH + Sense both edges + 3 + + + + + INTMODE3 + Interrupt Mode for LUT3 + [7:6] + + true + + + + INTDISABLE + Interrupt disabled + 0 + + + RISING + Sense rising edge + 1 + + + FALLING + Sense falling edge + 2 + + + BOTH + Sense both edges + 3 + + + + + + + INTFLAGS + Interrupt Flags + 0x7 + + + INT + Interrupt Flags + [3:0] + + + 0 + 15 + + + + + + + LUT0CTRLA + LUT Control 0 A + 0x8 + + + ENABLE + LUT Enable + [0:0] + + + CLKSRC + Clock Source Selection + [3:1] + + true + + + + CLKPER + CLK_PER is clocking the LUT + 0 + + + IN2 + IN[2] is clocking the LUT + 1 + + + OSC20M + 20MHz oscillator before prescaler is clocking the LUT + 4 + + + OSCULP32K + 32kHz oscillator is clocking the LUT + 5 + + + OSCULP1K + 32kHz oscillator after DIV32 is clocking the LUT + 6 + + + + + FILTSEL + Filter Selection + [5:4] + + true + + + + DISABLE + Filter disabled + 0 + + + SYNCH + Synchronizer enabled + 1 + + + FILTER + Filter enabled + 2 + + + + + OUTEN + Output Enable + [6:6] + + + EDGEDET + Edge Detection Enable + [7:7] + + true + + + + DIS + Edge detector is disabled + 0 + + + EN + Edge detector is enabled + 1 + + + + + + + LUT0CTRLB + LUT Control 0 B + 0x9 + + + INSEL0 + LUT Input 0 Source Selection + [3:0] + + true + + + + MASK + Masked input + 0 + + + FEEDBACK + Feedback input source + 1 + + + LINK + Linked LUT input source + 2 + + + EVENTA + Event input source A + 3 + + + EVENTB + Event input source B + 4 + + + IO + IO pin LUTn-IN0 input source + 5 + + + AC0 + AC0 OUT input source + 6 + + + USART0 + USART0 TXD input source + 8 + + + SPI0 + SPI0 MOSI input source + 9 + + + TCA0 + TCA0 WO0 input source + 10 + + + TCB0 + TCB0 WO input source + 12 + + + + + INSEL1 + LUT Input 1 Source Selection + [7:4] + + true + + + + MASK + Masked input + 0 + + + FEEDBACK + Feedback input source + 1 + + + LINK + Linked LUT input source + 2 + + + EVENTA + Event input source A + 3 + + + EVENTB + Event input source B + 4 + + + IO + IO pin LUTn-N1 input source + 5 + + + AC0 + AC0 OUT input source + 6 + + + USART1 + USART1 TXD input source + 8 + + + SPI0 + SPI0 MOSI input source + 9 + + + TCA0 + TCA0 WO1 input source + 10 + + + TCB1 + TCB1 WO input source + 12 + + + + + + + LUT0CTRLC + LUT Control 0 C + 0xA + + + INSEL2 + LUT Input 2 Source Selection + [3:0] + + true + + + + MASK + Masked input + 0 + + + FEEDBACK + Feedback input source + 1 + + + LINK + Linked LUT input source + 2 + + + EVENTA + Event input source A + 3 + + + EVENTB + Event input source B + 4 + + + IO + IO pin LUTn-IN2 input source + 5 + + + AC0 + AC0 OUT input source + 6 + + + USART2 + USART2 TXD input source + 8 + + + SPI0 + SPI0 SCK input source + 9 + + + TCA0 + TCA0 WO2 input source + 10 + + + TCB2 + TCB2 WO input source + 12 + + + + + + + LUT1CTRLA + LUT Control 1 A + 0xC + + + ENABLE + LUT Enable + [0:0] + + + CLKSRC + Clock Source Selection + [3:1] + + true + + + + CLKPER + CLK_PER is clocking the LUT + 0 + + + IN2 + IN[2] is clocking the LUT + 1 + + + OSC20M + 20MHz oscillator before prescaler is clocking the LUT + 4 + + + OSCULP32K + 32kHz oscillator is clocking the LUT + 5 + + + OSCULP1K + 32kHz oscillator after DIV32 is clocking the LUT + 6 + + + + + FILTSEL + Filter Selection + [5:4] + + true + + + + DISABLE + Filter disabled + 0 + + + SYNCH + Synchronizer enabled + 1 + + + FILTER + Filter enabled + 2 + + + + + OUTEN + Output Enable + [6:6] + + + EDGEDET + Edge Detection Enable + [7:7] + + true + + + + DIS + Edge detector is disabled + 0 + + + EN + Edge detector is enabled + 1 + + + + + + + LUT1CTRLB + LUT Control 1 B + 0xD + + + INSEL0 + LUT Input 0 Source Selection + [3:0] + + true + + + + MASK + Masked input + 0 + + + FEEDBACK + Feedback input source + 1 + + + LINK + Linked LUT input source + 2 + + + EVENTA + Event input source A + 3 + + + EVENTB + Event input source B + 4 + + + IO + IO pin LUTn-IN0 input source + 5 + + + AC0 + AC0 OUT input source + 6 + + + USART0 + USART0 TXD input source + 8 + + + SPI0 + SPI0 MOSI input source + 9 + + + TCA0 + TCA0 WO0 input source + 10 + + + TCB0 + TCB0 WO input source + 12 + + + + + INSEL1 + LUT Input 1 Source Selection + [7:4] + + true + + + + MASK + Masked input + 0 + + + FEEDBACK + Feedback input source + 1 + + + LINK + Linked LUT input source + 2 + + + EVENTA + Event input source A + 3 + + + EVENTB + Event input source B + 4 + + + IO + IO pin LUTn-N1 input source + 5 + + + AC0 + AC0 OUT input source + 6 + + + USART1 + USART1 TXD input source + 8 + + + SPI0 + SPI0 MOSI input source + 9 + + + TCA0 + TCA0 WO1 input source + 10 + + + TCB1 + TCB1 WO input source + 12 + + + + + + + LUT1CTRLC + LUT Control 1 C + 0xE + + + INSEL2 + LUT Input 2 Source Selection + [3:0] + + true + + + + MASK + Masked input + 0 + + + FEEDBACK + Feedback input source + 1 + + + LINK + Linked LUT input source + 2 + + + EVENTA + Event input source A + 3 + + + EVENTB + Event input source B + 4 + + + IO + IO pin LUTn-IN2 input source + 5 + + + AC0 + AC0 OUT input source + 6 + + + USART2 + USART2 TXD input source + 8 + + + SPI0 + SPI0 SCK input source + 9 + + + TCA0 + TCA0 WO2 input source + 10 + + + TCB2 + TCB2 WO input source + 12 + + + + + + + LUT2CTRLA + LUT Control 2 A + 0x10 + + + ENABLE + LUT Enable + [0:0] + + + CLKSRC + Clock Source Selection + [3:1] + + true + + + + CLKPER + CLK_PER is clocking the LUT + 0 + + + IN2 + IN[2] is clocking the LUT + 1 + + + OSC20M + 20MHz oscillator before prescaler is clocking the LUT + 4 + + + OSCULP32K + 32kHz oscillator is clocking the LUT + 5 + + + OSCULP1K + 32kHz oscillator after DIV32 is clocking the LUT + 6 + + + + + FILTSEL + Filter Selection + [5:4] + + true + + + + DISABLE + Filter disabled + 0 + + + SYNCH + Synchronizer enabled + 1 + + + FILTER + Filter enabled + 2 + + + + + OUTEN + Output Enable + [6:6] + + + EDGEDET + Edge Detection Enable + [7:7] + + true + + + + DIS + Edge detector is disabled + 0 + + + EN + Edge detector is enabled + 1 + + + + + + + LUT2CTRLB + LUT Control 2 B + 0x11 + + + INSEL0 + LUT Input 0 Source Selection + [3:0] + + true + + + + MASK + Masked input + 0 + + + FEEDBACK + Feedback input source + 1 + + + LINK + Linked LUT input source + 2 + + + EVENTA + Event input source A + 3 + + + EVENTB + Event input source B + 4 + + + IO + IO pin LUTn-IN0 input source + 5 + + + AC0 + AC0 OUT input source + 6 + + + USART0 + USART0 TXD input source + 8 + + + SPI0 + SPI0 MOSI input source + 9 + + + TCA0 + TCA0 WO0 input source + 10 + + + TCB0 + TCB0 WO input source + 12 + + + + + INSEL1 + LUT Input 1 Source Selection + [7:4] + + true + + + + MASK + Masked input + 0 + + + FEEDBACK + Feedback input source + 1 + + + LINK + Linked LUT input source + 2 + + + EVENTA + Event input source A + 3 + + + EVENTB + Event input source B + 4 + + + IO + IO pin LUTn-N1 input source + 5 + + + AC0 + AC0 OUT input source + 6 + + + USART1 + USART1 TXD input source + 8 + + + SPI0 + SPI0 MOSI input source + 9 + + + TCA0 + TCA0 WO1 input source + 10 + + + TCB1 + TCB1 WO input source + 12 + + + + + + + LUT2CTRLC + LUT Control 2 C + 0x12 + + + INSEL2 + LUT Input 2 Source Selection + [3:0] + + true + + + + MASK + Masked input + 0 + + + FEEDBACK + Feedback input source + 1 + + + LINK + Linked LUT input source + 2 + + + EVENTA + Event input source A + 3 + + + EVENTB + Event input source B + 4 + + + IO + IO pin LUTn-IN2 input source + 5 + + + AC0 + AC0 OUT input source + 6 + + + USART2 + USART2 TXD input source + 8 + + + SPI0 + SPI0 SCK input source + 9 + + + TCA0 + TCA0 WO2 input source + 10 + + + TCB2 + TCB2 WO input source + 12 + + + + + + + LUT3CTRLA + LUT Control 3 A + 0x14 + + + ENABLE + LUT Enable + [0:0] + + + CLKSRC + Clock Source Selection + [3:1] + + true + + + + CLKPER + CLK_PER is clocking the LUT + 0 + + + IN2 + IN[2] is clocking the LUT + 1 + + + OSC20M + 20MHz oscillator before prescaler is clocking the LUT + 4 + + + OSCULP32K + 32kHz oscillator is clocking the LUT + 5 + + + OSCULP1K + 32kHz oscillator after DIV32 is clocking the LUT + 6 + + + + + FILTSEL + Filter Selection + [5:4] + + true + + + + DISABLE + Filter disabled + 0 + + + SYNCH + Synchronizer enabled + 1 + + + FILTER + Filter enabled + 2 + + + + + OUTEN + Output Enable + [6:6] + + + EDGEDET + Edge Detection Enable + [7:7] + + true + + + + DIS + Edge detector is disabled + 0 + + + EN + Edge detector is enabled + 1 + + + + + + + LUT3CTRLB + LUT Control 3 B + 0x15 + + + INSEL0 + LUT Input 0 Source Selection + [3:0] + + true + + + + MASK + Masked input + 0 + + + FEEDBACK + Feedback input source + 1 + + + LINK + Linked LUT input source + 2 + + + EVENTA + Event input source A + 3 + + + EVENTB + Event input source B + 4 + + + IO + IO pin LUTn-IN0 input source + 5 + + + AC0 + AC0 OUT input source + 6 + + + USART0 + USART0 TXD input source + 8 + + + SPI0 + SPI0 MOSI input source + 9 + + + TCA0 + TCA0 WO0 input source + 10 + + + TCB0 + TCB0 WO input source + 12 + + + + + INSEL1 + LUT Input 1 Source Selection + [7:4] + + true + + + + MASK + Masked input + 0 + + + FEEDBACK + Feedback input source + 1 + + + LINK + Linked LUT input source + 2 + + + EVENTA + Event input source A + 3 + + + EVENTB + Event input source B + 4 + + + IO + IO pin LUTn-N1 input source + 5 + + + AC0 + AC0 OUT input source + 6 + + + USART1 + USART1 TXD input source + 8 + + + SPI0 + SPI0 MOSI input source + 9 + + + TCA0 + TCA0 WO1 input source + 10 + + + TCB1 + TCB1 WO input source + 12 + + + + + + + LUT3CTRLC + LUT Control 3 C + 0x16 + + + INSEL2 + LUT Input 2 Source Selection + [3:0] + + true + + + + MASK + Masked input + 0 + + + FEEDBACK + Feedback input source + 1 + + + LINK + Linked LUT input source + 2 + + + EVENTA + Event input source A + 3 + + + EVENTB + Event input source B + 4 + + + IO + IO pin LUTn-IN2 input source + 5 + + + AC0 + AC0 OUT input source + 6 + + + USART2 + USART2 TXD input source + 8 + + + SPI0 + SPI0 SCK input source + 9 + + + TCA0 + TCA0 WO2 input source + 10 + + + TCB2 + TCB2 WO input source + 12 + + + + + + + SEQCTRL0 + Sequential Control 0 + 0x1 + + + SEQSEL0 + Sequential Selection + [2:0] + + true + + + + DISABLE + Sequential logic disabled + 0 + + + DFF + D FlipFlop + 1 + + + JK + JK FlipFlop + 2 + + + LATCH + D Latch + 3 + + + RS + RS Latch + 4 + + + + + + + SEQCTRL1 + Sequential Control 1 + 0x2 + + + SEQSEL1 + Sequential Selection + [2:0] + + true + + + + DISABLE + Sequential logic disabled + 0 + + + DFF + D FlipFlop + 1 + + + JK + JK FlipFlop + 2 + + + LATCH + D Latch + 3 + + + RS + RS Latch + 4 + + + + + + + TRUTH0 + Truth 0 + 0xB + + + 0 + 255 + + + + + TRUTH1 + Truth 1 + 0xF + + + 0 + 255 + + + + + TRUTH2 + Truth 2 + 0x13 + + + 0 + 255 + + + + + TRUTH3 + Truth 3 + 0x17 + + + 0 + 255 + + + + + + + CLKCTRL + Clock controller + 0x60 + + + MCLKCTRLA + MCLK Control A + 0x0 + + + CLKSEL + clock select + [1:0] + + true + + + + OSC20M + 20MHz oscillator + 0 + + + OSCULP32K + 32KHz oscillator + 1 + + + XOSC32K + 32.768kHz crystal oscillator + 2 + + + EXTCLK + External clock + 3 + + + + + CLKOUT + System clock out + [7:7] + + + + + MCLKCTRLB + MCLK Control B + 0x1 + + + PEN + Prescaler enable + [0:0] + + + PDIV + Prescaler division + [4:1] + + true + + + + 2X + 2X + 0 + + + 4X + 4X + 1 + + + 8X + 8X + 2 + + + 16X + 16X + 3 + + + 32X + 32X + 4 + + + 64X + 64X + 5 + + + 6X + 6X + 8 + + + 10X + 10X + 9 + + + 12X + 12X + 10 + + + 24X + 24X + 11 + + + 48X + 48X + 12 + + + + + + + MCLKLOCK + MCLK Lock + 0x2 + + + LOCKEN + lock ebable + [0:0] + + + + + MCLKSTATUS + MCLK Status + 0x3 + + + SOSC + System Oscillator changing + [0:0] + read-only + + + OSC20MS + 20MHz oscillator status + [4:4] + read-only + + + OSC32KS + 32KHz oscillator status + [5:5] + read-only + + + XOSC32KS + 32.768 kHz Crystal Oscillator status + [6:6] + read-only + + + EXTS + External Clock status + [7:7] + read-only + + + + + OSC20MCALIBA + OSC20M Calibration A + 0x11 + + + CAL20M + Calibration + [6:0] + + + 0 + 127 + + + + + + + OSC20MCALIBB + OSC20M Calibration B + 0x12 + + + TEMPCAL20M + Oscillator temperature coefficient + [3:0] + + + 0 + 15 + + + + + LOCK + Lock + [7:7] + + + + + OSC20MCTRLA + OSC20M Control A + 0x10 + + + RUNSTDBY + Run standby + [1:1] + + + + + OSC32KCTRLA + OSC32K Control A + 0x18 + + + RUNSTDBY + Run standby + [1:1] + + + + + XOSC32KCTRLA + XOSC32K Control A + 0x1C + + + ENABLE + Enable + [0:0] + + + RUNSTDBY + Run standby + [1:1] + + + SEL + Select + [2:2] + + + CSUT + Crystal startup time + [5:4] + + true + + + + 1K + 1k cycles + 0 + + + 16K + 16k cycles + 1 + + + 32K + 32k cycles + 2 + + + 64K + 64k cycles + 3 + + + + + + + + + CPU + CPU + 0x34 + + CRCSCAN_NMI + <TBD> + 1 + + + BOD_VLM + <TBD> + 2 + + + RTC_CNT + <TBD> + 3 + + + RTC_PIT + <TBD> + 4 + + + CCL_CCL + <TBD> + 5 + + + PORTA_PORT + <TBD> + 6 + + + TCA0_LUNF_OVF + <TBD> + 7 + + + TCA0_HUNF + <TBD> + 8 + + + TCA0_CMP0_LCMP0 + <TBD> + 9 + + + TCA0_CMP1_LCMP1 + <TBD> + 10 + + + TCA0_CMP2_LCMP2 + <TBD> + 11 + + + TCB0_INT + <TBD> + 12 + + + TCB1_INT + <TBD> + 13 + + + TWI0_TWIS + <TBD> + 14 + + + TWI0_TWIM + <TBD> + 15 + + + SPI0_INT + <TBD> + 16 + + + USART0_RXC + <TBD> + 17 + + + USART0_DRE + <TBD> + 18 + + + USART0_TXC + <TBD> + 19 + + + PORTD_PORT + <TBD> + 20 + + + AC0_AC + <TBD> + 21 + + + ADC0_RESRDY + <TBD> + 22 + + + ADC0_WCOMP + <TBD> + 23 + + + PORTC_PORT + <TBD> + 24 + + + TCB2_INT + <TBD> + 25 + + + USART1_RXC + <TBD> + 26 + + + USART1_DRE + <TBD> + 27 + + + USART1_TXC + <TBD> + 28 + + + PORTF_PORT + <TBD> + 29 + + + NVMCTRL_EE + <TBD> + 30 + + + USART2_RXC + <TBD> + 31 + + + USART2_DRE + <TBD> + 32 + + + USART2_TXC + <TBD> + 33 + + + PORTB_PORT + <TBD> + 34 + + + PORTE_PORT + <TBD> + 35 + + + TCB3_INT + <TBD> + 36 + + + USART3_RXC + <TBD> + 37 + + + USART3_DRE + <TBD> + 38 + + + USART3_TXC + <TBD> + 39 + + + + CCP + Configuration Change Protection + 0x0 + + + CCP + CCP signature + [7:0] + + true + + + + SPM + SPM Instruction Protection + 157 + + + IOREG + IO Register Protection + 216 + + + + + + + SPH + Stack Pointer High + 0xA + + + 0 + 255 + + + + + SPL + Stack Pointer Low + 0x9 + + + 0 + 255 + + + + + + + CPUINT + Interrupt Controller + 0x110 + + + CTRLA + Control A + 0x0 + + + LVL0RR + Round-robin Scheduling Enable + [0:0] + + + CVT + Compact Vector Table + [5:5] + + + IVSEL + Interrupt Vector Select + [6:6] + + + + + LVL0PRI + Interrupt Level 0 Priority + 0x2 + + + LVL0PRI + Interrupt Level Priority + [7:0] + + + 0 + 255 + + + + + + + LVL1VEC + Interrupt Level 1 Priority Vector + 0x3 + + + LVL1VEC + Interrupt Vector with High Priority + [7:0] + + + 0 + 255 + + + + + + + STATUS + Status + 0x1 + + + LVL0EX + Level 0 Interrupt Executing + [0:0] + read-only + + + LVL1EX + Level 1 Interrupt Executing + [1:1] + read-only + + + NMIEX + Non-maskable Interrupt Executing + [7:7] + read-only + + + + + + + CRCSCAN + CRCSCAN + 0x120 + + + CTRLA + Control A + 0x0 + + + ENABLE + Enable CRC scan + [0:0] + + + NMIEN + Enable NMI Trigger + [1:1] + + + RESET + Reset CRC scan + [7:7] + + + + + CTRLB + Control B + 0x1 + + + SRC + CRC Source + [1:0] + + true + + + + FLASH + CRC on entire flash + 0 + + + APPLICATION + CRC on boot and appl section of flash + 1 + + + BOOT + CRC on boot section of flash + 2 + + + + + + + STATUS + Status + 0x2 + + + BUSY + CRC Busy + [0:0] + read-only + + + OK + CRC Ok + [1:1] + read-only + + + + + + + EVSYS + Event System + 0x180 + + + CHANNEL0 + Multiplexer Channel 0 + 0x10 + + + GENERATOR + Generator selector + [7:0] + + true + + + + OFF + Off + 0 + + + UPDI + Unified Program and Debug Interface + 1 + + + RTC_OVF + Real Time Counter overflow + 6 + + + RTC_CMP + Real Time Counter compare + 7 + + + RTC_PIT0 + Periodic Interrupt Timer output 0 + 8 + + + RTC_PIT1 + Periodic Interrupt Timer output 1 + 9 + + + RTC_PIT2 + Periodic Interrupt Timer output 2 + 10 + + + RTC_PIT3 + Periodic Interrupt Timer output 3 + 11 + + + CCL_LUT0 + Configurable Custom Logic LUT0 + 16 + + + CCL_LUT1 + Configurable Custom Logic LUT1 + 17 + + + CCL_LUT2 + Configurable Custom Logic LUT2 + 18 + + + CCL_LUT3 + Configurable Custom Logic LUT3 + 19 + + + AC0_OUT + Analog Comparator 0 out + 32 + + + ADC0_RESRDY + ADC 0 Result Ready Event + 36 + + + PORT0_PIN0 + Port 0 Pin 0 + 64 + + + PORT0_PIN1 + Port 0 Pin 1 + 65 + + + PORT0_PIN2 + Port 0 Pin 2 + 66 + + + PORT0_PIN3 + Port 0 Pin 3 + 67 + + + PORT0_PIN4 + Port 0 Pin 4 + 68 + + + PORT0_PIN5 + Port 0 Pin 5 + 69 + + + PORT0_PIN6 + Port 0 Pin 6 + 70 + + + PORT0_PIN7 + Port 0 Pin 7 + 71 + + + PORT1_PIN0 + Port 1 Pin 0 + 72 + + + PORT1_PIN1 + Port 1 Pin 1 + 73 + + + PORT1_PIN2 + Port 1 Pin 2 + 74 + + + PORT1_PIN3 + Port 1 Pin 3 + 75 + + + PORT1_PIN4 + Port 1 Pin 4 + 76 + + + PORT1_PIN5 + Port 1 Pin 5 + 77 + + + PORT1_PIN6 + Port 1 Pin 6 + 78 + + + PORT1_PIN7 + Port 1 Pin 7 + 79 + + + USART0_XCK + USART 0 Xclock + 96 + + + USART1_XCK + USART 1 Xclock + 97 + + + USART2_XCK + USART 2 Xclock + 98 + + + USART3_XCK + USART 3 Xclock + 99 + + + SPI0_SCK + SPI 0 Sclock + 104 + + + TCA0_OVF_LUNF + Timer/Counter A0 overflow / low byte underflow + 128 + + + TCA0_HUNF + Timer/Counter A0 high byte underflow (split mode) + 129 + + + TCA0_CMP0 + Timer/Counter A0 compare 0 + 132 + + + TCA0_CMP1 + Timer/Counter A0 compare 1 + 133 + + + TCA0_CMP2 + Timer/Counter A0 compare 2 + 134 + + + TCB0_CAPT + Timer/Counter B0 capture + 160 + + + TCB1_CAPT + Timer/Counter B1 capture + 162 + + + TCB2_CAPT + Timer/Counter B2 capture + 164 + + + TCB3_CAPT + Timer/Counter B3 capture + 166 + + + + + + + CHANNEL1 + Multiplexer Channel 1 + 0x11 + + + GENERATOR + Generator selector + [7:0] + + true + + + + OFF + Off + 0 + + + UPDI + Unified Program and Debug Interface + 1 + + + RTC_OVF + Real Time Counter overflow + 6 + + + RTC_CMP + Real Time Counter compare + 7 + + + RTC_PIT0 + Periodic Interrupt Timer output 0 + 8 + + + RTC_PIT1 + Periodic Interrupt Timer output 1 + 9 + + + RTC_PIT2 + Periodic Interrupt Timer output 2 + 10 + + + RTC_PIT3 + Periodic Interrupt Timer output 3 + 11 + + + CCL_LUT0 + Configurable Custom Logic LUT0 + 16 + + + CCL_LUT1 + Configurable Custom Logic LUT1 + 17 + + + CCL_LUT2 + Configurable Custom Logic LUT2 + 18 + + + CCL_LUT3 + Configurable Custom Logic LUT3 + 19 + + + AC0_OUT + Analog Comparator 0 out + 32 + + + ADC0_RESRDY + ADC 0 Result Ready Event + 36 + + + PORT0_PIN0 + Port 0 Pin 0 + 64 + + + PORT0_PIN1 + Port 0 Pin 1 + 65 + + + PORT0_PIN2 + Port 0 Pin 2 + 66 + + + PORT0_PIN3 + Port 0 Pin 3 + 67 + + + PORT0_PIN4 + Port 0 Pin 4 + 68 + + + PORT0_PIN5 + Port 0 Pin 5 + 69 + + + PORT0_PIN6 + Port 0 Pin 6 + 70 + + + PORT0_PIN7 + Port 0 Pin 7 + 71 + + + PORT1_PIN0 + Port 1 Pin 0 + 72 + + + PORT1_PIN1 + Port 1 Pin 1 + 73 + + + PORT1_PIN2 + Port 1 Pin 2 + 74 + + + PORT1_PIN3 + Port 1 Pin 3 + 75 + + + PORT1_PIN4 + Port 1 Pin 4 + 76 + + + PORT1_PIN5 + Port 1 Pin 5 + 77 + + + PORT1_PIN6 + Port 1 Pin 6 + 78 + + + PORT1_PIN7 + Port 1 Pin 7 + 79 + + + USART0_XCK + USART 0 Xclock + 96 + + + USART1_XCK + USART 1 Xclock + 97 + + + USART2_XCK + USART 2 Xclock + 98 + + + USART3_XCK + USART 3 Xclock + 99 + + + SPI0_SCK + SPI 0 Sclock + 104 + + + TCA0_OVF_LUNF + Timer/Counter A0 overflow / low byte underflow + 128 + + + TCA0_HUNF + Timer/Counter A0 high byte underflow (split mode) + 129 + + + TCA0_CMP0 + Timer/Counter A0 compare 0 + 132 + + + TCA0_CMP1 + Timer/Counter A0 compare 1 + 133 + + + TCA0_CMP2 + Timer/Counter A0 compare 2 + 134 + + + TCB0_CAPT + Timer/Counter B0 capture + 160 + + + TCB1_CAPT + Timer/Counter B1 capture + 162 + + + TCB2_CAPT + Timer/Counter B2 capture + 164 + + + TCB3_CAPT + Timer/Counter B3 capture + 166 + + + + + + + CHANNEL2 + Multiplexer Channel 2 + 0x12 + + + GENERATOR + Generator selector + [7:0] + + true + + + + OFF + Off + 0 + + + UPDI + Unified Program and Debug Interface + 1 + + + RTC_OVF + Real Time Counter overflow + 6 + + + RTC_CMP + Real Time Counter compare + 7 + + + RTC_PIT0 + Periodic Interrupt Timer output 0 + 8 + + + RTC_PIT1 + Periodic Interrupt Timer output 1 + 9 + + + RTC_PIT2 + Periodic Interrupt Timer output 2 + 10 + + + RTC_PIT3 + Periodic Interrupt Timer output 3 + 11 + + + CCL_LUT0 + Configurable Custom Logic LUT0 + 16 + + + CCL_LUT1 + Configurable Custom Logic LUT1 + 17 + + + CCL_LUT2 + Configurable Custom Logic LUT2 + 18 + + + CCL_LUT3 + Configurable Custom Logic LUT3 + 19 + + + AC0_OUT + Analog Comparator 0 out + 32 + + + ADC0_RESRDY + ADC 0 Result Ready Event + 36 + + + PORT0_PIN0 + Port 0 Pin 0 + 64 + + + PORT0_PIN1 + Port 0 Pin 1 + 65 + + + PORT0_PIN2 + Port 0 Pin 2 + 66 + + + PORT0_PIN3 + Port 0 Pin 3 + 67 + + + PORT0_PIN4 + Port 0 Pin 4 + 68 + + + PORT0_PIN5 + Port 0 Pin 5 + 69 + + + PORT0_PIN6 + Port 0 Pin 6 + 70 + + + PORT0_PIN7 + Port 0 Pin 7 + 71 + + + PORT1_PIN0 + Port 1 Pin 0 + 72 + + + PORT1_PIN1 + Port 1 Pin 1 + 73 + + + PORT1_PIN2 + Port 1 Pin 2 + 74 + + + PORT1_PIN3 + Port 1 Pin 3 + 75 + + + PORT1_PIN4 + Port 1 Pin 4 + 76 + + + PORT1_PIN5 + Port 1 Pin 5 + 77 + + + PORT1_PIN6 + Port 1 Pin 6 + 78 + + + PORT1_PIN7 + Port 1 Pin 7 + 79 + + + USART0_XCK + USART 0 Xclock + 96 + + + USART1_XCK + USART 1 Xclock + 97 + + + USART2_XCK + USART 2 Xclock + 98 + + + USART3_XCK + USART 3 Xclock + 99 + + + SPI0_SCK + SPI 0 Sclock + 104 + + + TCA0_OVF_LUNF + Timer/Counter A0 overflow / low byte underflow + 128 + + + TCA0_HUNF + Timer/Counter A0 high byte underflow (split mode) + 129 + + + TCA0_CMP0 + Timer/Counter A0 compare 0 + 132 + + + TCA0_CMP1 + Timer/Counter A0 compare 1 + 133 + + + TCA0_CMP2 + Timer/Counter A0 compare 2 + 134 + + + TCB0_CAPT + Timer/Counter B0 capture + 160 + + + TCB1_CAPT + Timer/Counter B1 capture + 162 + + + TCB2_CAPT + Timer/Counter B2 capture + 164 + + + TCB3_CAPT + Timer/Counter B3 capture + 166 + + + + + + + CHANNEL3 + Multiplexer Channel 3 + 0x13 + + + GENERATOR + Generator selector + [7:0] + + true + + + + OFF + Off + 0 + + + UPDI + Unified Program and Debug Interface + 1 + + + RTC_OVF + Real Time Counter overflow + 6 + + + RTC_CMP + Real Time Counter compare + 7 + + + RTC_PIT0 + Periodic Interrupt Timer output 0 + 8 + + + RTC_PIT1 + Periodic Interrupt Timer output 1 + 9 + + + RTC_PIT2 + Periodic Interrupt Timer output 2 + 10 + + + RTC_PIT3 + Periodic Interrupt Timer output 3 + 11 + + + CCL_LUT0 + Configurable Custom Logic LUT0 + 16 + + + CCL_LUT1 + Configurable Custom Logic LUT1 + 17 + + + CCL_LUT2 + Configurable Custom Logic LUT2 + 18 + + + CCL_LUT3 + Configurable Custom Logic LUT3 + 19 + + + AC0_OUT + Analog Comparator 0 out + 32 + + + ADC0_RESRDY + ADC 0 Result Ready Event + 36 + + + PORT0_PIN0 + Port 0 Pin 0 + 64 + + + PORT0_PIN1 + Port 0 Pin 1 + 65 + + + PORT0_PIN2 + Port 0 Pin 2 + 66 + + + PORT0_PIN3 + Port 0 Pin 3 + 67 + + + PORT0_PIN4 + Port 0 Pin 4 + 68 + + + PORT0_PIN5 + Port 0 Pin 5 + 69 + + + PORT0_PIN6 + Port 0 Pin 6 + 70 + + + PORT0_PIN7 + Port 0 Pin 7 + 71 + + + PORT1_PIN0 + Port 1 Pin 0 + 72 + + + PORT1_PIN1 + Port 1 Pin 1 + 73 + + + PORT1_PIN2 + Port 1 Pin 2 + 74 + + + PORT1_PIN3 + Port 1 Pin 3 + 75 + + + PORT1_PIN4 + Port 1 Pin 4 + 76 + + + PORT1_PIN5 + Port 1 Pin 5 + 77 + + + PORT1_PIN6 + Port 1 Pin 6 + 78 + + + PORT1_PIN7 + Port 1 Pin 7 + 79 + + + USART0_XCK + USART 0 Xclock + 96 + + + USART1_XCK + USART 1 Xclock + 97 + + + USART2_XCK + USART 2 Xclock + 98 + + + USART3_XCK + USART 3 Xclock + 99 + + + SPI0_SCK + SPI 0 Sclock + 104 + + + TCA0_OVF_LUNF + Timer/Counter A0 overflow / low byte underflow + 128 + + + TCA0_HUNF + Timer/Counter A0 high byte underflow (split mode) + 129 + + + TCA0_CMP0 + Timer/Counter A0 compare 0 + 132 + + + TCA0_CMP1 + Timer/Counter A0 compare 1 + 133 + + + TCA0_CMP2 + Timer/Counter A0 compare 2 + 134 + + + TCB0_CAPT + Timer/Counter B0 capture + 160 + + + TCB1_CAPT + Timer/Counter B1 capture + 162 + + + TCB2_CAPT + Timer/Counter B2 capture + 164 + + + TCB3_CAPT + Timer/Counter B3 capture + 166 + + + + + + + CHANNEL4 + Multiplexer Channel 4 + 0x14 + + + GENERATOR + Generator selector + [7:0] + + true + + + + OFF + Off + 0 + + + UPDI + Unified Program and Debug Interface + 1 + + + RTC_OVF + Real Time Counter overflow + 6 + + + RTC_CMP + Real Time Counter compare + 7 + + + RTC_PIT0 + Periodic Interrupt Timer output 0 + 8 + + + RTC_PIT1 + Periodic Interrupt Timer output 1 + 9 + + + RTC_PIT2 + Periodic Interrupt Timer output 2 + 10 + + + RTC_PIT3 + Periodic Interrupt Timer output 3 + 11 + + + CCL_LUT0 + Configurable Custom Logic LUT0 + 16 + + + CCL_LUT1 + Configurable Custom Logic LUT1 + 17 + + + CCL_LUT2 + Configurable Custom Logic LUT2 + 18 + + + CCL_LUT3 + Configurable Custom Logic LUT3 + 19 + + + AC0_OUT + Analog Comparator 0 out + 32 + + + ADC0_RESRDY + ADC 0 Result Ready Event + 36 + + + PORT0_PIN0 + Port 0 Pin 0 + 64 + + + PORT0_PIN1 + Port 0 Pin 1 + 65 + + + PORT0_PIN2 + Port 0 Pin 2 + 66 + + + PORT0_PIN3 + Port 0 Pin 3 + 67 + + + PORT0_PIN4 + Port 0 Pin 4 + 68 + + + PORT0_PIN5 + Port 0 Pin 5 + 69 + + + PORT0_PIN6 + Port 0 Pin 6 + 70 + + + PORT0_PIN7 + Port 0 Pin 7 + 71 + + + PORT1_PIN0 + Port 1 Pin 0 + 72 + + + PORT1_PIN1 + Port 1 Pin 1 + 73 + + + PORT1_PIN2 + Port 1 Pin 2 + 74 + + + PORT1_PIN3 + Port 1 Pin 3 + 75 + + + PORT1_PIN4 + Port 1 Pin 4 + 76 + + + PORT1_PIN5 + Port 1 Pin 5 + 77 + + + PORT1_PIN6 + Port 1 Pin 6 + 78 + + + PORT1_PIN7 + Port 1 Pin 7 + 79 + + + USART0_XCK + USART 0 Xclock + 96 + + + USART1_XCK + USART 1 Xclock + 97 + + + USART2_XCK + USART 2 Xclock + 98 + + + USART3_XCK + USART 3 Xclock + 99 + + + SPI0_SCK + SPI 0 Sclock + 104 + + + TCA0_OVF_LUNF + Timer/Counter A0 overflow / low byte underflow + 128 + + + TCA0_HUNF + Timer/Counter A0 high byte underflow (split mode) + 129 + + + TCA0_CMP0 + Timer/Counter A0 compare 0 + 132 + + + TCA0_CMP1 + Timer/Counter A0 compare 1 + 133 + + + TCA0_CMP2 + Timer/Counter A0 compare 2 + 134 + + + TCB0_CAPT + Timer/Counter B0 capture + 160 + + + TCB1_CAPT + Timer/Counter B1 capture + 162 + + + TCB2_CAPT + Timer/Counter B2 capture + 164 + + + TCB3_CAPT + Timer/Counter B3 capture + 166 + + + + + + + CHANNEL5 + Multiplexer Channel 5 + 0x15 + + + GENERATOR + Generator selector + [7:0] + + true + + + + OFF + Off + 0 + + + UPDI + Unified Program and Debug Interface + 1 + + + RTC_OVF + Real Time Counter overflow + 6 + + + RTC_CMP + Real Time Counter compare + 7 + + + RTC_PIT0 + Periodic Interrupt Timer output 0 + 8 + + + RTC_PIT1 + Periodic Interrupt Timer output 1 + 9 + + + RTC_PIT2 + Periodic Interrupt Timer output 2 + 10 + + + RTC_PIT3 + Periodic Interrupt Timer output 3 + 11 + + + CCL_LUT0 + Configurable Custom Logic LUT0 + 16 + + + CCL_LUT1 + Configurable Custom Logic LUT1 + 17 + + + CCL_LUT2 + Configurable Custom Logic LUT2 + 18 + + + CCL_LUT3 + Configurable Custom Logic LUT3 + 19 + + + AC0_OUT + Analog Comparator 0 out + 32 + + + ADC0_RESRDY + ADC 0 Result Ready Event + 36 + + + PORT0_PIN0 + Port 0 Pin 0 + 64 + + + PORT0_PIN1 + Port 0 Pin 1 + 65 + + + PORT0_PIN2 + Port 0 Pin 2 + 66 + + + PORT0_PIN3 + Port 0 Pin 3 + 67 + + + PORT0_PIN4 + Port 0 Pin 4 + 68 + + + PORT0_PIN5 + Port 0 Pin 5 + 69 + + + PORT0_PIN6 + Port 0 Pin 6 + 70 + + + PORT0_PIN7 + Port 0 Pin 7 + 71 + + + PORT1_PIN0 + Port 1 Pin 0 + 72 + + + PORT1_PIN1 + Port 1 Pin 1 + 73 + + + PORT1_PIN2 + Port 1 Pin 2 + 74 + + + PORT1_PIN3 + Port 1 Pin 3 + 75 + + + PORT1_PIN4 + Port 1 Pin 4 + 76 + + + PORT1_PIN5 + Port 1 Pin 5 + 77 + + + PORT1_PIN6 + Port 1 Pin 6 + 78 + + + PORT1_PIN7 + Port 1 Pin 7 + 79 + + + USART0_XCK + USART 0 Xclock + 96 + + + USART1_XCK + USART 1 Xclock + 97 + + + USART2_XCK + USART 2 Xclock + 98 + + + USART3_XCK + USART 3 Xclock + 99 + + + SPI0_SCK + SPI 0 Sclock + 104 + + + TCA0_OVF_LUNF + Timer/Counter A0 overflow / low byte underflow + 128 + + + TCA0_HUNF + Timer/Counter A0 high byte underflow (split mode) + 129 + + + TCA0_CMP0 + Timer/Counter A0 compare 0 + 132 + + + TCA0_CMP1 + Timer/Counter A0 compare 1 + 133 + + + TCA0_CMP2 + Timer/Counter A0 compare 2 + 134 + + + TCB0_CAPT + Timer/Counter B0 capture + 160 + + + TCB1_CAPT + Timer/Counter B1 capture + 162 + + + TCB2_CAPT + Timer/Counter B2 capture + 164 + + + TCB3_CAPT + Timer/Counter B3 capture + 166 + + + + + + + CHANNEL6 + Multiplexer Channel 6 + 0x16 + + + GENERATOR + Generator selector + [7:0] + + true + + + + OFF + Off + 0 + + + UPDI + Unified Program and Debug Interface + 1 + + + RTC_OVF + Real Time Counter overflow + 6 + + + RTC_CMP + Real Time Counter compare + 7 + + + RTC_PIT0 + Periodic Interrupt Timer output 0 + 8 + + + RTC_PIT1 + Periodic Interrupt Timer output 1 + 9 + + + RTC_PIT2 + Periodic Interrupt Timer output 2 + 10 + + + RTC_PIT3 + Periodic Interrupt Timer output 3 + 11 + + + CCL_LUT0 + Configurable Custom Logic LUT0 + 16 + + + CCL_LUT1 + Configurable Custom Logic LUT1 + 17 + + + CCL_LUT2 + Configurable Custom Logic LUT2 + 18 + + + CCL_LUT3 + Configurable Custom Logic LUT3 + 19 + + + AC0_OUT + Analog Comparator 0 out + 32 + + + ADC0_RESRDY + ADC 0 Result Ready Event + 36 + + + PORT0_PIN0 + Port 0 Pin 0 + 64 + + + PORT0_PIN1 + Port 0 Pin 1 + 65 + + + PORT0_PIN2 + Port 0 Pin 2 + 66 + + + PORT0_PIN3 + Port 0 Pin 3 + 67 + + + PORT0_PIN4 + Port 0 Pin 4 + 68 + + + PORT0_PIN5 + Port 0 Pin 5 + 69 + + + PORT0_PIN6 + Port 0 Pin 6 + 70 + + + PORT0_PIN7 + Port 0 Pin 7 + 71 + + + PORT1_PIN0 + Port 1 Pin 0 + 72 + + + PORT1_PIN1 + Port 1 Pin 1 + 73 + + + PORT1_PIN2 + Port 1 Pin 2 + 74 + + + PORT1_PIN3 + Port 1 Pin 3 + 75 + + + PORT1_PIN4 + Port 1 Pin 4 + 76 + + + PORT1_PIN5 + Port 1 Pin 5 + 77 + + + PORT1_PIN6 + Port 1 Pin 6 + 78 + + + PORT1_PIN7 + Port 1 Pin 7 + 79 + + + USART0_XCK + USART 0 Xclock + 96 + + + USART1_XCK + USART 1 Xclock + 97 + + + USART2_XCK + USART 2 Xclock + 98 + + + USART3_XCK + USART 3 Xclock + 99 + + + SPI0_SCK + SPI 0 Sclock + 104 + + + TCA0_OVF_LUNF + Timer/Counter A0 overflow / low byte underflow + 128 + + + TCA0_HUNF + Timer/Counter A0 high byte underflow (split mode) + 129 + + + TCA0_CMP0 + Timer/Counter A0 compare 0 + 132 + + + TCA0_CMP1 + Timer/Counter A0 compare 1 + 133 + + + TCA0_CMP2 + Timer/Counter A0 compare 2 + 134 + + + TCB0_CAPT + Timer/Counter B0 capture + 160 + + + TCB1_CAPT + Timer/Counter B1 capture + 162 + + + TCB2_CAPT + Timer/Counter B2 capture + 164 + + + TCB3_CAPT + Timer/Counter B3 capture + 166 + + + + + + + CHANNEL7 + Multiplexer Channel 7 + 0x17 + + + GENERATOR + Generator selector + [7:0] + + true + + + + OFF + Off + 0 + + + UPDI + Unified Program and Debug Interface + 1 + + + RTC_OVF + Real Time Counter overflow + 6 + + + RTC_CMP + Real Time Counter compare + 7 + + + RTC_PIT0 + Periodic Interrupt Timer output 0 + 8 + + + RTC_PIT1 + Periodic Interrupt Timer output 1 + 9 + + + RTC_PIT2 + Periodic Interrupt Timer output 2 + 10 + + + RTC_PIT3 + Periodic Interrupt Timer output 3 + 11 + + + CCL_LUT0 + Configurable Custom Logic LUT0 + 16 + + + CCL_LUT1 + Configurable Custom Logic LUT1 + 17 + + + CCL_LUT2 + Configurable Custom Logic LUT2 + 18 + + + CCL_LUT3 + Configurable Custom Logic LUT3 + 19 + + + AC0_OUT + Analog Comparator 0 out + 32 + + + ADC0_RESRDY + ADC 0 Result Ready Event + 36 + + + PORT0_PIN0 + Port 0 Pin 0 + 64 + + + PORT0_PIN1 + Port 0 Pin 1 + 65 + + + PORT0_PIN2 + Port 0 Pin 2 + 66 + + + PORT0_PIN3 + Port 0 Pin 3 + 67 + + + PORT0_PIN4 + Port 0 Pin 4 + 68 + + + PORT0_PIN5 + Port 0 Pin 5 + 69 + + + PORT0_PIN6 + Port 0 Pin 6 + 70 + + + PORT0_PIN7 + Port 0 Pin 7 + 71 + + + PORT1_PIN0 + Port 1 Pin 0 + 72 + + + PORT1_PIN1 + Port 1 Pin 1 + 73 + + + PORT1_PIN2 + Port 1 Pin 2 + 74 + + + PORT1_PIN3 + Port 1 Pin 3 + 75 + + + PORT1_PIN4 + Port 1 Pin 4 + 76 + + + PORT1_PIN5 + Port 1 Pin 5 + 77 + + + PORT1_PIN6 + Port 1 Pin 6 + 78 + + + PORT1_PIN7 + Port 1 Pin 7 + 79 + + + USART0_XCK + USART 0 Xclock + 96 + + + USART1_XCK + USART 1 Xclock + 97 + + + USART2_XCK + USART 2 Xclock + 98 + + + USART3_XCK + USART 3 Xclock + 99 + + + SPI0_SCK + SPI 0 Sclock + 104 + + + TCA0_OVF_LUNF + Timer/Counter A0 overflow / low byte underflow + 128 + + + TCA0_HUNF + Timer/Counter A0 high byte underflow (split mode) + 129 + + + TCA0_CMP0 + Timer/Counter A0 compare 0 + 132 + + + TCA0_CMP1 + Timer/Counter A0 compare 1 + 133 + + + TCA0_CMP2 + Timer/Counter A0 compare 2 + 134 + + + TCB0_CAPT + Timer/Counter B0 capture + 160 + + + TCB1_CAPT + Timer/Counter B1 capture + 162 + + + TCB2_CAPT + Timer/Counter B2 capture + 164 + + + TCB3_CAPT + Timer/Counter B3 capture + 166 + + + + + + + STROBE + Channel Strobe + 0x0 + + + STROBE0 + Software event on channels + [7:0] + write-only + + true + + + + EV_STROBE_CH0 + <TBD> + 1 + + + EV_STROBE_CH1 + <TBD> + 2 + + + EV_STROBE_CH2 + <TBD> + 4 + + + EV_STROBE_CH3 + <TBD> + 8 + + + EV_STROBE_CH4 + <TBD> + 16 + + + EV_STROBE_CH5 + <TBD> + 32 + + + EV_STROBE_CH6 + <TBD> + 64 + + + EV_STROBE_CH7 + <TBD> + 128 + + + + + + + USERADC0 + User ADC0 + 0x28 + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USERCCLLUT0A + User CCL LUT0 Event A + 0x20 + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USERCCLLUT0B + User CCL LUT0 Event B + 0x21 + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USERCCLLUT1A + User CCL LUT1 Event A + 0x22 + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USERCCLLUT1B + User CCL LUT1 Event B + 0x23 + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USERCCLLUT2A + User CCL LUT2 Event A + 0x24 + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USERCCLLUT2B + User CCL LUT2 Event B + 0x25 + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USERCCLLUT3A + User CCL LUT3 Event A + 0x26 + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USERCCLLUT3B + User CCL LUT3 Event B + 0x27 + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USEREVOUTA + User EVOUT Port A + 0x29 + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USEREVOUTB + User EVOUT Port B + 0x2A + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USEREVOUTC + User EVOUT Port C + 0x2B + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USEREVOUTD + User EVOUT Port D + 0x2C + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USEREVOUTE + User EVOUT Port E + 0x2D + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USEREVOUTF + User EVOUT Port F + 0x2E + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USERTCA0 + User TCA0 + 0x33 + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USERTCB0 + User TCB0 + 0x34 + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USERTCB1 + User TCB1 + 0x35 + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USERTCB2 + User TCB2 + 0x36 + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USERTCB3 + User TCB3 + 0x37 + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USERUSART0 + User USART0 + 0x2F + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USERUSART1 + User USART1 + 0x30 + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USERUSART2 + User USART2 + 0x31 + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + USERUSART3 + User USART3 + 0x32 + + + CHANNEL + Channel selector + [7:0] + + true + + + + OFF + Off + 0 + + + CHANNEL0 + Connect user to event channel 0 + 1 + + + CHANNEL1 + Connect user to event channel 1 + 2 + + + CHANNEL2 + Connect user to event channel 2 + 3 + + + CHANNEL3 + Connect user to event channel 3 + 4 + + + CHANNEL4 + Connect user to event channel 4 + 5 + + + CHANNEL5 + Connect user to event channel 5 + 6 + + + CHANNEL6 + Connect user to event channel 6 + 7 + + + CHANNEL7 + Connect user to event channel 7 + 8 + + + + + + + + + FUSE + Fuses + 0x1280 + + + APPEND + Application Code Section End + 0x7 + + + 0 + 255 + + + + + BODCFG + BOD Configuration + 0x1 + + + SLEEP + BOD Operation in Sleep Mode + [1:0] + + true + + + + DIS + Disabled + 0 + + + ENABLED + Enabled + 1 + + + SAMPLED + Sampled + 2 + + + + + ACTIVE + BOD Operation in Active Mode + [3:2] + + true + + + + DIS + Disabled + 0 + + + ENABLED + Enabled + 1 + + + SAMPLED + Sampled + 2 + + + ENWAKE + Enabled with wake-up halted until BOD is ready + 3 + + + + + SAMPFREQ + BOD Sample Frequency + [4:4] + + true + + + + 1KHZ + 1kHz sampling frequency + 0 + + + 125HZ + 125Hz sampling frequency + 1 + + + + + LVL + BOD Level + [7:5] + + true + + + + BODLEVEL0 + 1.8 V + 0 + + + BODLEVEL2 + 2.6 V + 2 + + + BODLEVEL7 + 4.2 V + 7 + + + + + + + BOOTEND + Boot Section End + 0x8 + + + 0 + 255 + + + + + OSCCFG + Oscillator Configuration + 0x2 + + + FREQSEL + Frequency Select + [1:0] + + true + + + + 16MHZ + 16 MHz + 1 + + + 20MHZ + 20 MHz + 2 + + + + + OSCLOCK + Oscillator Lock + [7:7] + + + + + SYSCFG0 + System Configuration 0 + 0x5 + + + EESAVE + EEPROM Save + [0:0] + + + RSTPINCFG + Reset Pin Configuration + [3:3] + + true + + + + GPIO + GPIO mode + 0 + + + RST + Reset mode + 1 + + + + + CRCSRC + CRC Source + [7:6] + + true + + + + FLASH + The CRC is performed on the entire Flash (boot, application code and application data section). + 0 + + + BOOT + The CRC is performed on the boot section of Flash + 1 + + + BOOTAPP + The CRC is performed on the boot and application code section of Flash + 2 + + + NOCRC + Disable CRC. + 3 + + + + + + + SYSCFG1 + System Configuration 1 + 0x6 + + + SUT + Startup Time + [2:0] + + true + + + + 0MS + 0 ms + 0 + + + 1MS + 1 ms + 1 + + + 2MS + 2 ms + 2 + + + 4MS + 4 ms + 3 + + + 8MS + 8 ms + 4 + + + 16MS + 16 ms + 5 + + + 32MS + 32 ms + 6 + + + 64MS + 64 ms + 7 + + + + + + + WDTCFG + Watchdog Configuration + 0x0 + + + PERIOD + Watchdog Timeout Period + [3:0] + + true + + + + OFF + Off + 0 + + + 8CLK + 8 cycles (8ms) + 1 + + + 16CLK + 16 cycles (16ms) + 2 + + + 32CLK + 32 cycles (32ms) + 3 + + + 64CLK + 64 cycles (64ms) + 4 + + + 128CLK + 128 cycles (0.128s) + 5 + + + 256CLK + 256 cycles (0.256s) + 6 + + + 512CLK + 512 cycles (0.512s) + 7 + + + 1KCLK + 1K cycles (1.0s) + 8 + + + 2KCLK + 2K cycles (2.0s) + 9 + + + 4KCLK + 4K cycles (4.1s) + 10 + + + 8KCLK + 8K cycles (8.2s) + 11 + + + + + WINDOW + Watchdog Window Timeout Period + [7:4] + + true + + + + OFF + Off + 0 + + + 8CLK + 8 cycles (8ms) + 1 + + + 16CLK + 16 cycles (16ms) + 2 + + + 32CLK + 32 cycles (32ms) + 3 + + + 64CLK + 64 cycles (64ms) + 4 + + + 128CLK + 128 cycles (0.128s) + 5 + + + 256CLK + 256 cycles (0.256s) + 6 + + + 512CLK + 512 cycles (0.512s) + 7 + + + 1KCLK + 1K cycles (1.0s) + 8 + + + 2KCLK + 2K cycles (2.0s) + 9 + + + 4KCLK + 4K cycles (4.1s) + 10 + + + 8KCLK + 8K cycles (8.2s) + 11 + + + + + + + + + GPIO + General Purpose IO + 0x1C + + + GPIOR0 + General Purpose IO Register 0 + 0x0 + + + 0 + 255 + + + + + GPIOR1 + General Purpose IO Register 1 + 0x1 + + + 0 + 255 + + + + + GPIOR2 + General Purpose IO Register 2 + 0x2 + + + 0 + 255 + + + + + GPIOR3 + General Purpose IO Register 3 + 0x3 + + + 0 + 255 + + + + + + + LOCKBIT + Lockbit + 0x128A + + + LOCKBIT + Lock Bits + 0x0 + + + LB + Lock Bits + [7:0] + + true + + + + RWLOCK + Read and write lock + 58 + + + NOLOCK + No locks + 197 + + + + + + + + + NVMCTRL + Non-volatile Memory Controller + 0x1000 + + + ADDR + Address + 0x8 + 16 + + + 0 + 65535 + + + + + CTRLA + Control A + 0x0 + + + CMD + Command + [2:0] + + true + + + + NONE + No Command + 0 + + + PAGEWRITE + Write page + 1 + + + PAGEERASE + Erase page + 2 + + + PAGEERASEWRITE + Erase and write page + 3 + + + PAGEBUFCLR + Page buffer clear + 4 + + + CHIPERASE + Chip erase + 5 + + + EEERASE + EEPROM erase + 6 + + + FUSEWRITE + Write fuse (PDI only) + 7 + + + + + + + CTRLB + Control B + 0x1 + + + APCWP + Application code write protect + [0:0] + + + BOOTLOCK + Boot Lock + [1:1] + + + + + DATA + Data + 0x6 + 16 + + + 0 + 65535 + + + + + INTCTRL + Interrupt Control + 0x3 + + + EEREADY + EEPROM Ready + [0:0] + + + + + INTFLAGS + Interrupt Flags + 0x4 + + + EEREADY + EEPROM Ready + [0:0] + + + + + STATUS + Status + 0x2 + + + FBUSY + Flash busy + [0:0] + read-only + + + EEBUSY + EEPROM busy + [1:1] + read-only + + + WRERROR + Write error + [2:2] + read-only + + + + + + + PORTA + I/O Ports + 0x400 + + + DIR + Data Direction + 0x0 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + DIRCLR + Data Direction Clear + 0x2 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + DIRSET + Data Direction Set + 0x1 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + DIRTGL + Data Direction Toggle + 0x3 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + IN + Input Value + 0x8 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + INTFLAGS + Interrupt Flags + 0x9 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + OUT + Output Value + 0x4 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + OUTCLR + Output Value Clear + 0x6 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + OUTSET + Output Value Set + 0x5 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + OUTTGL + Output Value Toggle + 0x7 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + PIN0CTRL + Pin 0 Control + 0x10 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN1CTRL + Pin 1 Control + 0x11 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN2CTRL + Pin 2 Control + 0x12 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN3CTRL + Pin 3 Control + 0x13 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN4CTRL + Pin 4 Control + 0x14 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN5CTRL + Pin 5 Control + 0x15 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN6CTRL + Pin 6 Control + 0x16 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN7CTRL + Pin 7 Control + 0x17 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PORTCTRL + Port Control + 0xA + + + SRL + Slew Rate Limit Enable + [0:0] + + + + + + + PORTB + I/O Ports + 0x420 + + + DIR + Data Direction + 0x0 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + + + DIRCLR + Data Direction Clear + 0x2 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + + + DIRSET + Data Direction Set + 0x1 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + + + DIRTGL + Data Direction Toggle + 0x3 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + + + IN + Input Value + 0x8 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + + + INTFLAGS + Interrupt Flags + 0x9 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + + + OUT + Output Value + 0x4 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + + + OUTCLR + Output Value Clear + 0x6 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + + + OUTSET + Output Value Set + 0x5 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + + + OUTTGL + Output Value Toggle + 0x7 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + + + PIN0CTRL + Pin 0 Control + 0x10 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN1CTRL + Pin 1 Control + 0x11 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN2CTRL + Pin 2 Control + 0x12 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN3CTRL + Pin 3 Control + 0x13 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN4CTRL + Pin 4 Control + 0x14 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN5CTRL + Pin 5 Control + 0x15 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN6CTRL + Pin 6 Control + 0x16 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN7CTRL + Pin 7 Control + 0x17 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PORTCTRL + Port Control + 0xA + + + SRL + Slew Rate Limit Enable + [0:0] + + + + + + + PORTC + I/O Ports + 0x440 + + + DIR + Data Direction + 0x0 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + DIRCLR + Data Direction Clear + 0x2 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + DIRSET + Data Direction Set + 0x1 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + DIRTGL + Data Direction Toggle + 0x3 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + IN + Input Value + 0x8 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + INTFLAGS + Interrupt Flags + 0x9 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + OUT + Output Value + 0x4 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + OUTCLR + Output Value Clear + 0x6 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + OUTSET + Output Value Set + 0x5 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + OUTTGL + Output Value Toggle + 0x7 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + PIN0CTRL + Pin 0 Control + 0x10 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN1CTRL + Pin 1 Control + 0x11 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN2CTRL + Pin 2 Control + 0x12 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN3CTRL + Pin 3 Control + 0x13 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN4CTRL + Pin 4 Control + 0x14 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN5CTRL + Pin 5 Control + 0x15 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN6CTRL + Pin 6 Control + 0x16 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN7CTRL + Pin 7 Control + 0x17 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PORTCTRL + Port Control + 0xA + + + SRL + Slew Rate Limit Enable + [0:0] + + + + + + + PORTD + I/O Ports + 0x460 + + + DIR + Data Direction + 0x0 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + DIRCLR + Data Direction Clear + 0x2 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + DIRSET + Data Direction Set + 0x1 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + DIRTGL + Data Direction Toggle + 0x3 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + IN + Input Value + 0x8 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + INTFLAGS + Interrupt Flags + 0x9 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + OUT + Output Value + 0x4 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + OUTCLR + Output Value Clear + 0x6 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + OUTSET + Output Value Set + 0x5 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + OUTTGL + Output Value Toggle + 0x7 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PIN0CTRL + Pin 0 Control + 0x10 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN1CTRL + Pin 1 Control + 0x11 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN2CTRL + Pin 2 Control + 0x12 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN3CTRL + Pin 3 Control + 0x13 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN4CTRL + Pin 4 Control + 0x14 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN5CTRL + Pin 5 Control + 0x15 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN6CTRL + Pin 6 Control + 0x16 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN7CTRL + Pin 7 Control + 0x17 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PORTCTRL + Port Control + 0xA + + + SRL + Slew Rate Limit Enable + [0:0] + + + + + + + PORTE + I/O Ports + 0x480 + + + DIR + Data Direction + 0x0 + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + + + DIRCLR + Data Direction Clear + 0x2 + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + + + DIRSET + Data Direction Set + 0x1 + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + + + DIRTGL + Data Direction Toggle + 0x3 + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + + + IN + Input Value + 0x8 + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + + + INTFLAGS + Interrupt Flags + 0x9 + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + + + OUT + Output Value + 0x4 + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + + + OUTCLR + Output Value Clear + 0x6 + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + + + OUTSET + Output Value Set + 0x5 + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + + + OUTTGL + Output Value Toggle + 0x7 + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + + + PIN0CTRL + Pin 0 Control + 0x10 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN1CTRL + Pin 1 Control + 0x11 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN2CTRL + Pin 2 Control + 0x12 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN3CTRL + Pin 3 Control + 0x13 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN4CTRL + Pin 4 Control + 0x14 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN5CTRL + Pin 5 Control + 0x15 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN6CTRL + Pin 6 Control + 0x16 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN7CTRL + Pin 7 Control + 0x17 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PORTCTRL + Port Control + 0xA + + + SRL + Slew Rate Limit Enable + [0:0] + + + + + + + PORTF + I/O Ports + 0x4A0 + + + DIR + Data Direction + 0x0 + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF2 + Pin F2 + [2:2] + + + PF3 + Pin F3 + [3:3] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + + + DIRCLR + Data Direction Clear + 0x2 + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF2 + Pin F2 + [2:2] + + + PF3 + Pin F3 + [3:3] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + + + DIRSET + Data Direction Set + 0x1 + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF2 + Pin F2 + [2:2] + + + PF3 + Pin F3 + [3:3] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + + + DIRTGL + Data Direction Toggle + 0x3 + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF2 + Pin F2 + [2:2] + + + PF3 + Pin F3 + [3:3] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + + + IN + Input Value + 0x8 + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF2 + Pin F2 + [2:2] + + + PF3 + Pin F3 + [3:3] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + + + INTFLAGS + Interrupt Flags + 0x9 + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF2 + Pin F2 + [2:2] + + + PF3 + Pin F3 + [3:3] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + + + OUT + Output Value + 0x4 + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF2 + Pin F2 + [2:2] + + + PF3 + Pin F3 + [3:3] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + + + OUTCLR + Output Value Clear + 0x6 + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF2 + Pin F2 + [2:2] + + + PF3 + Pin F3 + [3:3] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + + + OUTSET + Output Value Set + 0x5 + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF2 + Pin F2 + [2:2] + + + PF3 + Pin F3 + [3:3] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + + + OUTTGL + Output Value Toggle + 0x7 + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF2 + Pin F2 + [2:2] + + + PF3 + Pin F3 + [3:3] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + + + PIN0CTRL + Pin 0 Control + 0x10 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN1CTRL + Pin 1 Control + 0x11 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN2CTRL + Pin 2 Control + 0x12 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN3CTRL + Pin 3 Control + 0x13 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN4CTRL + Pin 4 Control + 0x14 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN5CTRL + Pin 5 Control + 0x15 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN6CTRL + Pin 6 Control + 0x16 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PIN7CTRL + Pin 7 Control + 0x17 + + + ISC + Input/Sense Configuration + [2:0] + + true + + + + INTDISABLE + Interrupt disabled but input buffer enabled + 0 + + + BOTHEDGES + Sense Both Edges + 1 + + + RISING + Sense Rising Edge + 2 + + + FALLING + Sense Falling Edge + 3 + + + INPUT_DISABLE + Digital Input Buffer disabled + 4 + + + LEVEL + Sense low Level + 5 + + + + + PULLUPEN + Pullup enable + [3:3] + + + INVEN + Inverted I/O Enable + [7:7] + + + + + PORTCTRL + Port Control + 0xA + + + SRL + Slew Rate Limit Enable + [0:0] + + + + + + + PORTMUX + Port Multiplexer + 0x5E0 + + + CCLROUTEA + Port Multiplexer CCL + 0x1 + + + LUT0 + CCL LUT0 + [0:0] + + + LUT1 + CCL LUT1 + [1:1] + + + LUT2 + CCL LUT2 + [2:2] + + + LUT3 + CCL LUT3 + [3:3] + + + + + EVSYSROUTEA + Port Multiplexer EVSYS + 0x0 + + + EVOUT0 + Event Output 0 + [0:0] + + + EVOUT1 + Event Output 1 + [1:1] + + + EVOUT2 + Event Output 2 + [2:2] + + + EVOUT3 + Event Output 3 + [3:3] + + + EVOUT4 + Event Output 4 + [4:4] + + + EVOUT5 + Event Output 5 + [5:5] + + + + + TCAROUTEA + Port Multiplexer TCA + 0x4 + + + TCA0 + Port Multiplexer TCA0 + [2:0] + + true + + + + PORTA + TCA0 pins on PA[5:0] + 0 + + + PORTB + TCA0 pins on PB[5:0] + 1 + + + PORTC + TCA0 pins on PC[5:0] + 2 + + + PORTD + TCA0 pins on PD[5:0] + 3 + + + PORTE + TCA0 pins on PE[5:0] + 4 + + + PORTF + TCA0 pins on PF[5:0] + 5 + + + + + + + TCBROUTEA + Port Multiplexer TCB + 0x5 + + + TCB0 + Port Multiplexer TCB0 + [0:0] + + + TCB1 + Port Multiplexer TCB1 + [1:1] + + + TCB2 + Port Multiplexer TCB2 + [2:2] + + + TCB3 + Port Multiplexer TCB3 + [3:3] + + + + + TWISPIROUTEA + Port Multiplexer TWI and SPI + 0x3 + + + SPI0 + Port Multiplexer SPI0 + [1:0] + + true + + + + DEFAULT + SPI0 on PA[7:4] + 0 + + + ALT1 + SPI0 on PC[3:0] + 1 + + + ALT2 + SPI0 on PE[3:0] + 2 + + + NONE + Not connected to any pins + 3 + + + + + TWI0 + Port Multiplexer TWI0 + [5:4] + + true + + + + DEFAULT + SCL/SDA on PA[3:2], Slave mode on PC[3:2] in dual TWI mode + 0 + + + ALT1 + SCL/SDA on PA[3:2], Slave mode on PF[3:2] in dual TWI mode + 1 + + + ALT2 + SCL/SDA on PC[3:2], Slave mode on PF[3:2] in dual TWI mode + 2 + + + NONE + Not connected to any pins + 3 + + + + + + + USARTROUTEA + Port Multiplexer USART register A + 0x2 + + + USART0 + Port Multiplexer USART0 + [1:0] + + true + + + + DEFAULT + USART0 on PA[3:0] + 0 + + + ALT1 + USART0 on PA[7:4] + 1 + + + NONE + Not connected to any pins + 3 + + + + + USART1 + Port Multiplexer USART1 + [3:2] + + true + + + + DEFAULT + USART1 on PC[3:0] + 0 + + + ALT1 + USART1 on PC[7:4] + 1 + + + NONE + Not connected to any pins + 3 + + + + + USART2 + Port Multiplexer USART2 + [5:4] + + true + + + + DEFAULT + USART2 on PF[3:0] + 0 + + + ALT1 + USART2 on PF[6:4] + 1 + + + NONE + Not connected to any pins + 3 + + + + + USART3 + Port Multiplexer USART3 + [7:6] + + true + + + + DEFAULT + USART3 on PB[3:0] + 0 + + + ALT1 + USART3 on PB[5:4] + 1 + + + NONE + Not connected to any pins + 3 + + + + + + + + + RSTCTRL + Reset controller + 0x40 + + + RSTFR + Reset Flags + 0x0 + + + PORF + Power on Reset flag + [0:0] + + + BORF + Brown out detector Reset flag + [1:1] + + + EXTRF + External Reset flag + [2:2] + + + WDRF + Watch dog Reset flag + [3:3] + + + SWRF + Software Reset flag + [4:4] + + + UPDIRF + UPDI Reset flag + [5:5] + + + + + SWRR + Software Reset + 0x1 + + + SWRE + Software reset enable + [0:0] + + + + + + + RTC + Real-Time Counter + 0x140 + + + CALIB + Calibration + 0x6 + + + ERROR + Error Correction Value + [6:0] + + + 0 + 127 + + + + + SIGN + Error Correction Sign Bit + [7:7] + + + + + CLKSEL + Clock Select + 0x7 + + + CLKSEL + Clock Select + [1:0] + + true + + + + INT32K + Internal 32kHz OSC + 0 + + + INT1K + Internal 1kHz OSC + 1 + + + TOSC32K + 32KHz Crystal OSC + 2 + + + EXTCLK + External Clock + 3 + + + + + + + CMP + Compare + 0xC + 16 + + + 0 + 65535 + + + + + CNT + Counter + 0x8 + 16 + + + 0 + 65535 + + + + + CTRLA + Control A + 0x0 + + + RTCEN + Enable + [0:0] + + + CORREN + Correction enable + [2:2] + + + PRESCALER + Prescaling Factor + [6:3] + + true + + + + DIV1 + RTC Clock / 1 + 0 + + + DIV2 + RTC Clock / 2 + 1 + + + DIV4 + RTC Clock / 4 + 2 + + + DIV8 + RTC Clock / 8 + 3 + + + DIV16 + RTC Clock / 16 + 4 + + + DIV32 + RTC Clock / 32 + 5 + + + DIV64 + RTC Clock / 64 + 6 + + + DIV128 + RTC Clock / 128 + 7 + + + DIV256 + RTC Clock / 256 + 8 + + + DIV512 + RTC Clock / 512 + 9 + + + DIV1024 + RTC Clock / 1024 + 10 + + + DIV2048 + RTC Clock / 2048 + 11 + + + DIV4096 + RTC Clock / 4096 + 12 + + + DIV8192 + RTC Clock / 8192 + 13 + + + DIV16384 + RTC Clock / 16384 + 14 + + + DIV32768 + RTC Clock / 32768 + 15 + + + + + RUNSTDBY + Run In Standby + [7:7] + + + + + DBGCTRL + Debug control + 0x5 + + + DBGRUN + Run in debug + [0:0] + + + + + INTCTRL + Interrupt Control + 0x2 + + + OVF + Overflow Interrupt enable + [0:0] + + + CMP + Compare Match Interrupt enable + [1:1] + + + + + INTFLAGS + Interrupt Flags + 0x3 + + + OVF + Overflow Interrupt Flag + [0:0] + + + CMP + Compare Match Interrupt + [1:1] + + + + + PER + Period + 0xA + 16 + + + 0 + 65535 + + + + + PITCTRLA + PIT Control A + 0x10 + + + PITEN + Enable + [0:0] + + + PERIOD + Period + [6:3] + + true + + + + OFF + Off + 0 + + + CYC4 + RTC Clock Cycles 4 + 1 + + + CYC8 + RTC Clock Cycles 8 + 2 + + + CYC16 + RTC Clock Cycles 16 + 3 + + + CYC32 + RTC Clock Cycles 32 + 4 + + + CYC64 + RTC Clock Cycles 64 + 5 + + + CYC128 + RTC Clock Cycles 128 + 6 + + + CYC256 + RTC Clock Cycles 256 + 7 + + + CYC512 + RTC Clock Cycles 512 + 8 + + + CYC1024 + RTC Clock Cycles 1024 + 9 + + + CYC2048 + RTC Clock Cycles 2048 + 10 + + + CYC4096 + RTC Clock Cycles 4096 + 11 + + + CYC8192 + RTC Clock Cycles 8192 + 12 + + + CYC16384 + RTC Clock Cycles 16384 + 13 + + + CYC32768 + RTC Clock Cycles 32768 + 14 + + + + + + + PITDBGCTRL + PIT Debug control + 0x15 + + + DBGRUN + Run in debug + [0:0] + + + + + PITINTCTRL + PIT Interrupt Control + 0x12 + + + PI + Periodic Interrupt + [0:0] + + + + + PITINTFLAGS + PIT Interrupt Flags + 0x13 + + + PI + Periodic Interrupt + [0:0] + + + + + PITSTATUS + PIT Status + 0x11 + + + CTRLBUSY + CTRLA Synchronization Busy Flag + [0:0] + read-only + + + + + STATUS + Status + 0x1 + + + CTRLABUSY + CTRLA Synchronization Busy Flag + [0:0] + read-only + + + CNTBUSY + Count Synchronization Busy Flag + [1:1] + read-only + + + PERBUSY + Period Synchronization Busy Flag + [2:2] + read-only + + + CMPBUSY + Comparator Synchronization Busy Flag + [3:3] + read-only + + + + + TEMP + Temporary + 0x4 + + + 0 + 255 + + + + + + + SIGROW + Signature row + 0x1100 + + + CHECKSUM1 + CRC Checksum Byte 1 + 0x2F + + + 0 + 255 + + + + + DEVICEID0 + Device ID Byte 0 + 0x0 + + + 0 + 255 + + + + + DEVICEID1 + Device ID Byte 1 + 0x1 + + + 0 + 255 + + + + + DEVICEID2 + Device ID Byte 2 + 0x2 + + + 0 + 255 + + + + + OSC16ERR3V + OSC16 error at 3V + 0x22 + + + 0 + 255 + + + + + OSC16ERR5V + OSC16 error at 5V + 0x23 + + + 0 + 255 + + + + + OSC20ERR3V + OSC20 error at 3V + 0x24 + + + 0 + 255 + + + + + OSC20ERR5V + OSC20 error at 5V + 0x25 + + + 0 + 255 + + + + + OSCCAL16M0 + Oscillator Calibration 16 MHz Byte 0 + 0x18 + + + 0 + 255 + + + + + OSCCAL16M1 + Oscillator Calibration 16 MHz Byte 1 + 0x19 + + + 0 + 255 + + + + + OSCCAL20M0 + Oscillator Calibration 20 MHz Byte 0 + 0x1A + + + 0 + 255 + + + + + OSCCAL20M1 + Oscillator Calibration 20 MHz Byte 1 + 0x1B + + + 0 + 255 + + + + + OSCCAL32K + Oscillator Calibration for 32kHz ULP + 0x14 + + + 0 + 255 + + + + + SERNUM0 + Serial Number Byte 0 + 0x3 + + + 0 + 255 + + + + + SERNUM1 + Serial Number Byte 1 + 0x4 + + + 0 + 255 + + + + + SERNUM2 + Serial Number Byte 2 + 0x5 + + + 0 + 255 + + + + + SERNUM3 + Serial Number Byte 3 + 0x6 + + + 0 + 255 + + + + + SERNUM4 + Serial Number Byte 4 + 0x7 + + + 0 + 255 + + + + + SERNUM5 + Serial Number Byte 5 + 0x8 + + + 0 + 255 + + + + + SERNUM6 + Serial Number Byte 6 + 0x9 + + + 0 + 255 + + + + + SERNUM7 + Serial Number Byte 7 + 0xA + + + 0 + 255 + + + + + SERNUM8 + Serial Number Byte 8 + 0xB + + + 0 + 255 + + + + + SERNUM9 + Serial Number Byte 9 + 0xC + + + 0 + 255 + + + + + TEMPSENSE0 + Temperature Sensor Calibration Byte 0 + 0x20 + + + 0 + 255 + + + + + TEMPSENSE1 + Temperature Sensor Calibration Byte 1 + 0x21 + + + 0 + 255 + + + + + + + SLPCTRL + Sleep Controller + 0x50 + + + CTRLA + Control + 0x0 + + + SEN + Sleep enable + [0:0] + + + SMODE + Sleep mode + [2:1] + + true + + + + IDLE + Idle mode + 0 + + + STDBY + Standby Mode + 1 + + + PDOWN + Power-down Mode + 2 + + + + + + + + + SPI0 + Serial Peripheral Interface + 0x8C0 + + + CTRLA + Control A + 0x0 + + + ENABLE + Enable Module + [0:0] + + + PRESC + Prescaler + [2:1] + + true + + + + DIV4 + System Clock / 4 + 0 + + + DIV16 + System Clock / 16 + 1 + + + DIV64 + System Clock / 64 + 2 + + + DIV128 + System Clock / 128 + 3 + + + + + CLK2X + Enable Double Speed + [4:4] + + + MASTER + Master Operation Enable + [5:5] + + + DORD + Data Order Setting + [6:6] + + + + + CTRLB + Control B + 0x1 + + + MODE + SPI Mode + [1:0] + + true + + + + 0 + SPI Mode 0 + 0 + + + 1 + SPI Mode 1 + 1 + + + 2 + SPI Mode 2 + 2 + + + 3 + SPI Mode 3 + 3 + + + + + SSD + Slave Select Disable + [2:2] + + + BUFWR + Buffer Write Mode + [6:6] + + + BUFEN + Buffer Mode Enable + [7:7] + + + + + DATA + Data + 0x4 + + + 0 + 255 + + + + + INTCTRL + Interrupt Control + 0x2 + + + IE + Interrupt Enable + [0:0] + + + SSIE + Slave Select Trigger Interrupt Enable + [4:4] + + + DREIE + Data Register Empty Interrupt Enable + [5:5] + + + TXCIE + Transfer Complete Interrupt Enable + [6:6] + + + RXCIE + Receive Complete Interrupt Enable + [7:7] + + + + + INTFLAGS + Interrupt Flags + 0x3 + + + 0 + 255 + + + + + + + SYSCFG + System Configuration Registers + 0xF01 + + + EXTBRK + External Break + 0x1 + + + ENEXTBRK + External break enable + [0:0] + + + + + OCDM + OCD Message Register + 0x17 + + + 0 + 255 + + + + + OCDMS + OCD Message Status + 0x18 + + + OCDMR + OCD Message Read + [0:0] + + + + + REVID + Revision ID + 0x0 + + + 0 + 255 + + + + + + + TCB0 + 16-bit Timer Type B + 0xA80 + + + CCMP + Compare or Capture + 0xC + 16 + + + 0 + 65535 + + + + + CNT + Count + 0xA + 16 + + + 0 + 65535 + + + + + CTRLA + Control A + 0x0 + + + ENABLE + Enable + [0:0] + + + CLKSEL + Clock Select + [2:1] + + true + + + + CLKDIV1 + CLK_PER (No Prescaling) + 0 + + + CLKDIV2 + CLK_PER/2 (From Prescaler) + 1 + + + CLKTCA + Use Clock from TCA + 2 + + + + + SYNCUPD + Synchronize Update + [4:4] + + + RUNSTDBY + Run Standby + [6:6] + + + + + CTRLB + Control Register B + 0x1 + + + CNTMODE + Timer Mode + [2:0] + + true + + + + INT + Periodic Interrupt + 0 + + + TIMEOUT + Periodic Timeout + 1 + + + CAPT + Input Capture Event + 2 + + + FRQ + Input Capture Frequency measurement + 3 + + + PW + Input Capture Pulse-Width measurement + 4 + + + FRQPW + Input Capture Frequency and Pulse-Width measurement + 5 + + + SINGLE + Single Shot + 6 + + + PWM8 + 8-bit PWM + 7 + + + + + CCMPEN + Pin Output Enable + [4:4] + + + CCMPINIT + Pin Initial State + [5:5] + + + ASYNC + Asynchronous Enable + [6:6] + + + + + DBGCTRL + Debug Control + 0x8 + + + DBGRUN + Debug Run + [0:0] + + + + + EVCTRL + Event Control + 0x4 + + + CAPTEI + Event Input Enable + [0:0] + + + EDGE + Event Edge + [4:4] + + + FILTER + Input Capture Noise Cancellation Filter + [6:6] + + + + + INTCTRL + Interrupt Control + 0x5 + + + CAPT + Capture or Timeout + [0:0] + + + + + INTFLAGS + Interrupt Flags + 0x6 + + + CAPT + Capture or Timeout + [0:0] + + + + + STATUS + Status + 0x7 + + + RUN + Run + [0:0] + read-only + + + + + TEMP + Temporary Value + 0x9 + + + 0 + 255 + + + + + + + TCB1 + 16-bit Timer Type B + 0xA90 + + + CCMP + Compare or Capture + 0xC + 16 + + + 0 + 65535 + + + + + CNT + Count + 0xA + 16 + + + 0 + 65535 + + + + + CTRLA + Control A + 0x0 + + + ENABLE + Enable + [0:0] + + + CLKSEL + Clock Select + [2:1] + + true + + + + CLKDIV1 + CLK_PER (No Prescaling) + 0 + + + CLKDIV2 + CLK_PER/2 (From Prescaler) + 1 + + + CLKTCA + Use Clock from TCA + 2 + + + + + SYNCUPD + Synchronize Update + [4:4] + + + RUNSTDBY + Run Standby + [6:6] + + + + + CTRLB + Control Register B + 0x1 + + + CNTMODE + Timer Mode + [2:0] + + true + + + + INT + Periodic Interrupt + 0 + + + TIMEOUT + Periodic Timeout + 1 + + + CAPT + Input Capture Event + 2 + + + FRQ + Input Capture Frequency measurement + 3 + + + PW + Input Capture Pulse-Width measurement + 4 + + + FRQPW + Input Capture Frequency and Pulse-Width measurement + 5 + + + SINGLE + Single Shot + 6 + + + PWM8 + 8-bit PWM + 7 + + + + + CCMPEN + Pin Output Enable + [4:4] + + + CCMPINIT + Pin Initial State + [5:5] + + + ASYNC + Asynchronous Enable + [6:6] + + + + + DBGCTRL + Debug Control + 0x8 + + + DBGRUN + Debug Run + [0:0] + + + + + EVCTRL + Event Control + 0x4 + + + CAPTEI + Event Input Enable + [0:0] + + + EDGE + Event Edge + [4:4] + + + FILTER + Input Capture Noise Cancellation Filter + [6:6] + + + + + INTCTRL + Interrupt Control + 0x5 + + + CAPT + Capture or Timeout + [0:0] + + + + + INTFLAGS + Interrupt Flags + 0x6 + + + CAPT + Capture or Timeout + [0:0] + + + + + STATUS + Status + 0x7 + + + RUN + Run + [0:0] + read-only + + + + + TEMP + Temporary Value + 0x9 + + + 0 + 255 + + + + + + + TCB2 + 16-bit Timer Type B + 0xAA0 + + + CCMP + Compare or Capture + 0xC + 16 + + + 0 + 65535 + + + + + CNT + Count + 0xA + 16 + + + 0 + 65535 + + + + + CTRLA + Control A + 0x0 + + + ENABLE + Enable + [0:0] + + + CLKSEL + Clock Select + [2:1] + + true + + + + CLKDIV1 + CLK_PER (No Prescaling) + 0 + + + CLKDIV2 + CLK_PER/2 (From Prescaler) + 1 + + + CLKTCA + Use Clock from TCA + 2 + + + + + SYNCUPD + Synchronize Update + [4:4] + + + RUNSTDBY + Run Standby + [6:6] + + + + + CTRLB + Control Register B + 0x1 + + + CNTMODE + Timer Mode + [2:0] + + true + + + + INT + Periodic Interrupt + 0 + + + TIMEOUT + Periodic Timeout + 1 + + + CAPT + Input Capture Event + 2 + + + FRQ + Input Capture Frequency measurement + 3 + + + PW + Input Capture Pulse-Width measurement + 4 + + + FRQPW + Input Capture Frequency and Pulse-Width measurement + 5 + + + SINGLE + Single Shot + 6 + + + PWM8 + 8-bit PWM + 7 + + + + + CCMPEN + Pin Output Enable + [4:4] + + + CCMPINIT + Pin Initial State + [5:5] + + + ASYNC + Asynchronous Enable + [6:6] + + + + + DBGCTRL + Debug Control + 0x8 + + + DBGRUN + Debug Run + [0:0] + + + + + EVCTRL + Event Control + 0x4 + + + CAPTEI + Event Input Enable + [0:0] + + + EDGE + Event Edge + [4:4] + + + FILTER + Input Capture Noise Cancellation Filter + [6:6] + + + + + INTCTRL + Interrupt Control + 0x5 + + + CAPT + Capture or Timeout + [0:0] + + + + + INTFLAGS + Interrupt Flags + 0x6 + + + CAPT + Capture or Timeout + [0:0] + + + + + STATUS + Status + 0x7 + + + RUN + Run + [0:0] + read-only + + + + + TEMP + Temporary Value + 0x9 + + + 0 + 255 + + + + + + + TCB3 + 16-bit Timer Type B + 0xAB0 + + + CCMP + Compare or Capture + 0xC + 16 + + + 0 + 65535 + + + + + CNT + Count + 0xA + 16 + + + 0 + 65535 + + + + + CTRLA + Control A + 0x0 + + + ENABLE + Enable + [0:0] + + + CLKSEL + Clock Select + [2:1] + + true + + + + CLKDIV1 + CLK_PER (No Prescaling) + 0 + + + CLKDIV2 + CLK_PER/2 (From Prescaler) + 1 + + + CLKTCA + Use Clock from TCA + 2 + + + + + SYNCUPD + Synchronize Update + [4:4] + + + RUNSTDBY + Run Standby + [6:6] + + + + + CTRLB + Control Register B + 0x1 + + + CNTMODE + Timer Mode + [2:0] + + true + + + + INT + Periodic Interrupt + 0 + + + TIMEOUT + Periodic Timeout + 1 + + + CAPT + Input Capture Event + 2 + + + FRQ + Input Capture Frequency measurement + 3 + + + PW + Input Capture Pulse-Width measurement + 4 + + + FRQPW + Input Capture Frequency and Pulse-Width measurement + 5 + + + SINGLE + Single Shot + 6 + + + PWM8 + 8-bit PWM + 7 + + + + + CCMPEN + Pin Output Enable + [4:4] + + + CCMPINIT + Pin Initial State + [5:5] + + + ASYNC + Asynchronous Enable + [6:6] + + + + + DBGCTRL + Debug Control + 0x8 + + + DBGRUN + Debug Run + [0:0] + + + + + EVCTRL + Event Control + 0x4 + + + CAPTEI + Event Input Enable + [0:0] + + + EDGE + Event Edge + [4:4] + + + FILTER + Input Capture Noise Cancellation Filter + [6:6] + + + + + INTCTRL + Interrupt Control + 0x5 + + + CAPT + Capture or Timeout + [0:0] + + + + + INTFLAGS + Interrupt Flags + 0x6 + + + CAPT + Capture or Timeout + [0:0] + + + + + STATUS + Status + 0x7 + + + RUN + Run + [0:0] + read-only + + + + + TEMP + Temporary Value + 0x9 + + + 0 + 255 + + + + + + + TWI0 + Two-Wire Interface + 0x8A0 + + + CTRLA + Control A + 0x0 + + + 0 + 255 + + + + + DBGCTRL + Debug Control Register + 0x2 + + + 0 + 255 + + + + + DUALCTRL + Dual Control + 0x1 + + + 0 + 255 + + + + + MADDR + Master Address + 0x7 + + + 0 + 255 + + + + + MBAUD + Master Baurd Rate Control + 0x6 + + + 0 + 255 + + + + + MCTRLA + Master Control A + 0x3 + + + ENABLE + Enable TWI Master + [0:0] + + + SMEN + Smart Mode Enable + [1:1] + + + TIMEOUT + Inactive Bus Timeout + [3:2] + + true + + + + DISABLED + Bus Timeout Disabled + 0 + + + 50US + 50 Microseconds + 1 + + + 100US + 100 Microseconds + 2 + + + 200US + 200 Microseconds + 3 + + + + + QCEN + Quick Command Enable + [4:4] + + + WIEN + Write Interrupt Enable + [6:6] + + + RIEN + Read Interrupt Enable + [7:7] + + + + + MCTRLB + Master Control B + 0x4 + + + MCMD + Command + [1:0] + + true + + + + NOACT + No Action + 0 + + + REPSTART + Issue Repeated Start Condition + 1 + + + RECVTRANS + Receive or Transmit Data, depending on DIR + 2 + + + STOP + Issue Stop Condition + 3 + + + + + ACKACT + Acknowledge Action + [2:2] + + true + + + + ACK + Send ACK + 0 + + + NACK + Send NACK + 1 + + + + + FLUSH + Flush + [3:3] + + + + + MDATA + Master Data + 0x8 + + + 0 + 255 + + + + + MSTATUS + Master Status + 0x5 + + + BUSSTATE + Bus State + [1:0] + + true + + + + UNKNOWN + Unknown Bus State + 0 + + + IDLE + Bus is Idle + 1 + + + OWNER + This Module Controls The Bus + 2 + + + BUSY + The Bus is Busy + 3 + + + + + BUSERR + Bus Error + [2:2] + + + ARBLOST + Arbitration Lost + [3:3] + + + RXACK + Received Acknowledge + [4:4] + read-only + + + CLKHOLD + Clock Hold + [5:5] + + + WIF + Write Interrupt Flag + [6:6] + + + RIF + Read Interrupt Flag + [7:7] + + + + + SADDR + Slave Address + 0xC + + + 0 + 255 + + + + + SADDRMASK + Slave Address Mask + 0xE + + + ADDREN + Address Enable + [0:0] + + + ADDRMASK + Address Mask + [7:1] + + + 0 + 127 + + + + + + + SCTRLA + Slave Control A + 0x9 + + + ENABLE + Enable TWI Slave + [0:0] + + + SMEN + Smart Mode Enable + [1:1] + + + PMEN + Promiscuous Mode Enable + [2:2] + + + PIEN + Stop Interrupt Enable + [5:5] + + + APIEN + Address/Stop Interrupt Enable + [6:6] + + + DIEN + Data Interrupt Enable + [7:7] + + + + + SCTRLB + Slave Control B + 0xA + + + SCMD + Command + [1:0] + + true + + + + NOACT + No Action + 0 + + + COMPTRANS + Used To Complete a Transaction + 2 + + + RESPONSE + Used in Response to Address/Data Interrupt + 3 + + + + + ACKACT + Acknowledge Action + [2:2] + + true + + + + ACK + Send ACK + 0 + + + NACK + Send NACK + 1 + + + + + + + SDATA + Slave Data + 0xD + + + 0 + 255 + + + + + SSTATUS + Slave Status + 0xB + + + AP + Slave Address or Stop + [0:0] + read-only + + true + + + + STOP + Stop condition generated APIF + 0 + + + ADR + Address detection generated APIF + 1 + + + + + DIR + Read/Write Direction + [1:1] + read-only + + + BUSERR + Bus Error + [2:2] + + + COLL + Collision + [3:3] + + + RXACK + Received Acknowledge + [4:4] + read-only + + + CLKHOLD + Clock Hold + [5:5] + read-only + + + APIF + Address/Stop Interrupt Flag + [6:6] + + + DIF + Data Interrupt Flag + [7:7] + + + + + + + USART0 + Universal Synchronous and Asynchronous Receiver and Transmitter + 0x800 + + + BAUD + Baud Rate + 0x8 + 16 + + + 0 + 65535 + + + + + CTRLA + Control A + 0x5 + + + RS485 + RS485 Mode internal transmitter + [1:0] + + true + + + + OFF + RS485 Mode disabled + 0 + + + EXT + RS485 Mode External drive + 1 + + + INT + RS485 Mode Internal drive + 2 + + + + + ABEIE + Auto-baud Error Interrupt Enable + [2:2] + + + LBME + Loop-back Mode Enable + [3:3] + + + RXSIE + Receiver Start Frame Interrupt Enable + [4:4] + + + DREIE + Data Register Empty Interrupt Enable + [5:5] + + + TXCIE + Transmit Complete Interrupt Enable + [6:6] + + + RXCIE + Receive Complete Interrupt Enable + [7:7] + + + + + CTRLB + Control B + 0x6 + + + MPCM + Multi-processor Communication Mode + [0:0] + + + RXMODE + Receiver Mode + [2:1] + + true + + + + NORMAL + Normal mode + 0 + + + CLK2X + CLK2x mode + 1 + + + GENAUTO + Generic autobaud mode + 2 + + + LINAUTO + LIN constrained autobaud mode + 3 + + + + + ODME + Open Drain Mode Enable + [3:3] + + + SFDEN + Start Frame Detection Enable + [4:4] + + + TXEN + Transmitter Enable + [6:6] + + + RXEN + Reciever enable + [7:7] + + + + + CTRLC + Control C + 0x7 + + + 0 + 255 + + + + + CTRLD + Control D + 0xA + + + ABW + Auto Baud Window + [7:6] + + true + + + + WDW0 + 18% tolerance + 0 + + + WDW1 + 15% tolerance + 1 + + + WDW2 + 21% tolerance + 2 + + + WDW3 + 25% tolerance + 3 + + + + + + + DBGCTRL + Debug Control + 0xB + + + DBGRUN + Debug Run + [0:0] + + + ABMBP + Autobaud majority voter bypass + [7:7] + + + + + EVCTRL + Event Control + 0xC + + + IREI + IrDA Event Input Enable + [0:0] + + + + + RXDATAH + Receive Data High Byte + 0x1 + + + DATA8 + Receiver Data Register + [0:0] + read-only + + + PERR + Parity Error + [1:1] + read-only + + + FERR + Frame Error + [2:2] + read-only + + + BUFOVF + Buffer Overflow + [6:6] + read-only + + + RXCIF + Receive Complete Interrupt Flag + [7:7] + read-only + + + + + RXDATAL + Receive Data Low Byte + 0x0 + + + DATA + RX Data + [7:0] + read-only + + + 0 + 255 + + + + + + + RXPLCTRL + IRCOM Receiver Pulse Length Control + 0xE + + + RXPL + Receiver Pulse Lenght + [6:0] + + + 0 + 127 + + + + + + + STATUS + Status + 0x4 + + + WFB + Wait For Break + [0:0] + + + BDF + Break Detected Flag + [1:1] + + + ISFIF + Inconsistent Sync Field Interrupt Flag + [3:3] + + + RXSIF + Receive Start Interrupt + [4:4] + read-only + + + DREIF + Data Register Empty Flag + [5:5] + read-only + + + TXCIF + Transmit Interrupt Flag + [6:6] + + + RXCIF + Receive Complete Interrupt Flag + [7:7] + read-only + + + + + TXDATAH + Transmit Data High Byte + 0x3 + + + DATA8 + Transmit Data Register (CHSIZE=9bit) + [0:0] + + + + + TXDATAL + Transmit Data Low Byte + 0x2 + + + DATA + Transmit Data Register + [7:0] + + + 0 + 255 + + + + + + + TXPLCTRL + IRCOM Transmitter Pulse Length Control + 0xD + + + TXPL + Transmit pulse length + [7:0] + + + 0 + 255 + + + + + + + + + USART1 + Universal Synchronous and Asynchronous Receiver and Transmitter + 0x820 + + + BAUD + Baud Rate + 0x8 + 16 + + + 0 + 65535 + + + + + CTRLA + Control A + 0x5 + + + RS485 + RS485 Mode internal transmitter + [1:0] + + true + + + + OFF + RS485 Mode disabled + 0 + + + EXT + RS485 Mode External drive + 1 + + + INT + RS485 Mode Internal drive + 2 + + + + + ABEIE + Auto-baud Error Interrupt Enable + [2:2] + + + LBME + Loop-back Mode Enable + [3:3] + + + RXSIE + Receiver Start Frame Interrupt Enable + [4:4] + + + DREIE + Data Register Empty Interrupt Enable + [5:5] + + + TXCIE + Transmit Complete Interrupt Enable + [6:6] + + + RXCIE + Receive Complete Interrupt Enable + [7:7] + + + + + CTRLB + Control B + 0x6 + + + MPCM + Multi-processor Communication Mode + [0:0] + + + RXMODE + Receiver Mode + [2:1] + + true + + + + NORMAL + Normal mode + 0 + + + CLK2X + CLK2x mode + 1 + + + GENAUTO + Generic autobaud mode + 2 + + + LINAUTO + LIN constrained autobaud mode + 3 + + + + + ODME + Open Drain Mode Enable + [3:3] + + + SFDEN + Start Frame Detection Enable + [4:4] + + + TXEN + Transmitter Enable + [6:6] + + + RXEN + Reciever enable + [7:7] + + + + + CTRLC + Control C + 0x7 + + + 0 + 255 + + + + + CTRLD + Control D + 0xA + + + ABW + Auto Baud Window + [7:6] + + true + + + + WDW0 + 18% tolerance + 0 + + + WDW1 + 15% tolerance + 1 + + + WDW2 + 21% tolerance + 2 + + + WDW3 + 25% tolerance + 3 + + + + + + + DBGCTRL + Debug Control + 0xB + + + DBGRUN + Debug Run + [0:0] + + + ABMBP + Autobaud majority voter bypass + [7:7] + + + + + EVCTRL + Event Control + 0xC + + + IREI + IrDA Event Input Enable + [0:0] + + + + + RXDATAH + Receive Data High Byte + 0x1 + + + DATA8 + Receiver Data Register + [0:0] + read-only + + + PERR + Parity Error + [1:1] + read-only + + + FERR + Frame Error + [2:2] + read-only + + + BUFOVF + Buffer Overflow + [6:6] + read-only + + + RXCIF + Receive Complete Interrupt Flag + [7:7] + read-only + + + + + RXDATAL + Receive Data Low Byte + 0x0 + + + DATA + RX Data + [7:0] + read-only + + + 0 + 255 + + + + + + + RXPLCTRL + IRCOM Receiver Pulse Length Control + 0xE + + + RXPL + Receiver Pulse Lenght + [6:0] + + + 0 + 127 + + + + + + + STATUS + Status + 0x4 + + + WFB + Wait For Break + [0:0] + + + BDF + Break Detected Flag + [1:1] + + + ISFIF + Inconsistent Sync Field Interrupt Flag + [3:3] + + + RXSIF + Receive Start Interrupt + [4:4] + read-only + + + DREIF + Data Register Empty Flag + [5:5] + read-only + + + TXCIF + Transmit Interrupt Flag + [6:6] + + + RXCIF + Receive Complete Interrupt Flag + [7:7] + read-only + + + + + TXDATAH + Transmit Data High Byte + 0x3 + + + DATA8 + Transmit Data Register (CHSIZE=9bit) + [0:0] + + + + + TXDATAL + Transmit Data Low Byte + 0x2 + + + DATA + Transmit Data Register + [7:0] + + + 0 + 255 + + + + + + + TXPLCTRL + IRCOM Transmitter Pulse Length Control + 0xD + + + TXPL + Transmit pulse length + [7:0] + + + 0 + 255 + + + + + + + + + USART2 + Universal Synchronous and Asynchronous Receiver and Transmitter + 0x840 + + + BAUD + Baud Rate + 0x8 + 16 + + + 0 + 65535 + + + + + CTRLA + Control A + 0x5 + + + RS485 + RS485 Mode internal transmitter + [1:0] + + true + + + + OFF + RS485 Mode disabled + 0 + + + EXT + RS485 Mode External drive + 1 + + + INT + RS485 Mode Internal drive + 2 + + + + + ABEIE + Auto-baud Error Interrupt Enable + [2:2] + + + LBME + Loop-back Mode Enable + [3:3] + + + RXSIE + Receiver Start Frame Interrupt Enable + [4:4] + + + DREIE + Data Register Empty Interrupt Enable + [5:5] + + + TXCIE + Transmit Complete Interrupt Enable + [6:6] + + + RXCIE + Receive Complete Interrupt Enable + [7:7] + + + + + CTRLB + Control B + 0x6 + + + MPCM + Multi-processor Communication Mode + [0:0] + + + RXMODE + Receiver Mode + [2:1] + + true + + + + NORMAL + Normal mode + 0 + + + CLK2X + CLK2x mode + 1 + + + GENAUTO + Generic autobaud mode + 2 + + + LINAUTO + LIN constrained autobaud mode + 3 + + + + + ODME + Open Drain Mode Enable + [3:3] + + + SFDEN + Start Frame Detection Enable + [4:4] + + + TXEN + Transmitter Enable + [6:6] + + + RXEN + Reciever enable + [7:7] + + + + + CTRLC + Control C + 0x7 + + + 0 + 255 + + + + + CTRLD + Control D + 0xA + + + ABW + Auto Baud Window + [7:6] + + true + + + + WDW0 + 18% tolerance + 0 + + + WDW1 + 15% tolerance + 1 + + + WDW2 + 21% tolerance + 2 + + + WDW3 + 25% tolerance + 3 + + + + + + + DBGCTRL + Debug Control + 0xB + + + DBGRUN + Debug Run + [0:0] + + + ABMBP + Autobaud majority voter bypass + [7:7] + + + + + EVCTRL + Event Control + 0xC + + + IREI + IrDA Event Input Enable + [0:0] + + + + + RXDATAH + Receive Data High Byte + 0x1 + + + DATA8 + Receiver Data Register + [0:0] + read-only + + + PERR + Parity Error + [1:1] + read-only + + + FERR + Frame Error + [2:2] + read-only + + + BUFOVF + Buffer Overflow + [6:6] + read-only + + + RXCIF + Receive Complete Interrupt Flag + [7:7] + read-only + + + + + RXDATAL + Receive Data Low Byte + 0x0 + + + DATA + RX Data + [7:0] + read-only + + + 0 + 255 + + + + + + + RXPLCTRL + IRCOM Receiver Pulse Length Control + 0xE + + + RXPL + Receiver Pulse Lenght + [6:0] + + + 0 + 127 + + + + + + + STATUS + Status + 0x4 + + + WFB + Wait For Break + [0:0] + + + BDF + Break Detected Flag + [1:1] + + + ISFIF + Inconsistent Sync Field Interrupt Flag + [3:3] + + + RXSIF + Receive Start Interrupt + [4:4] + read-only + + + DREIF + Data Register Empty Flag + [5:5] + read-only + + + TXCIF + Transmit Interrupt Flag + [6:6] + + + RXCIF + Receive Complete Interrupt Flag + [7:7] + read-only + + + + + TXDATAH + Transmit Data High Byte + 0x3 + + + DATA8 + Transmit Data Register (CHSIZE=9bit) + [0:0] + + + + + TXDATAL + Transmit Data Low Byte + 0x2 + + + DATA + Transmit Data Register + [7:0] + + + 0 + 255 + + + + + + + TXPLCTRL + IRCOM Transmitter Pulse Length Control + 0xD + + + TXPL + Transmit pulse length + [7:0] + + + 0 + 255 + + + + + + + + + USART3 + Universal Synchronous and Asynchronous Receiver and Transmitter + 0x860 + + + BAUD + Baud Rate + 0x8 + 16 + + + 0 + 65535 + + + + + CTRLA + Control A + 0x5 + + + RS485 + RS485 Mode internal transmitter + [1:0] + + true + + + + OFF + RS485 Mode disabled + 0 + + + EXT + RS485 Mode External drive + 1 + + + INT + RS485 Mode Internal drive + 2 + + + + + ABEIE + Auto-baud Error Interrupt Enable + [2:2] + + + LBME + Loop-back Mode Enable + [3:3] + + + RXSIE + Receiver Start Frame Interrupt Enable + [4:4] + + + DREIE + Data Register Empty Interrupt Enable + [5:5] + + + TXCIE + Transmit Complete Interrupt Enable + [6:6] + + + RXCIE + Receive Complete Interrupt Enable + [7:7] + + + + + CTRLB + Control B + 0x6 + + + MPCM + Multi-processor Communication Mode + [0:0] + + + RXMODE + Receiver Mode + [2:1] + + true + + + + NORMAL + Normal mode + 0 + + + CLK2X + CLK2x mode + 1 + + + GENAUTO + Generic autobaud mode + 2 + + + LINAUTO + LIN constrained autobaud mode + 3 + + + + + ODME + Open Drain Mode Enable + [3:3] + + + SFDEN + Start Frame Detection Enable + [4:4] + + + TXEN + Transmitter Enable + [6:6] + + + RXEN + Reciever enable + [7:7] + + + + + CTRLC + Control C + 0x7 + + + 0 + 255 + + + + + CTRLD + Control D + 0xA + + + ABW + Auto Baud Window + [7:6] + + true + + + + WDW0 + 18% tolerance + 0 + + + WDW1 + 15% tolerance + 1 + + + WDW2 + 21% tolerance + 2 + + + WDW3 + 25% tolerance + 3 + + + + + + + DBGCTRL + Debug Control + 0xB + + + DBGRUN + Debug Run + [0:0] + + + ABMBP + Autobaud majority voter bypass + [7:7] + + + + + EVCTRL + Event Control + 0xC + + + IREI + IrDA Event Input Enable + [0:0] + + + + + RXDATAH + Receive Data High Byte + 0x1 + + + DATA8 + Receiver Data Register + [0:0] + read-only + + + PERR + Parity Error + [1:1] + read-only + + + FERR + Frame Error + [2:2] + read-only + + + BUFOVF + Buffer Overflow + [6:6] + read-only + + + RXCIF + Receive Complete Interrupt Flag + [7:7] + read-only + + + + + RXDATAL + Receive Data Low Byte + 0x0 + + + DATA + RX Data + [7:0] + read-only + + + 0 + 255 + + + + + + + RXPLCTRL + IRCOM Receiver Pulse Length Control + 0xE + + + RXPL + Receiver Pulse Lenght + [6:0] + + + 0 + 127 + + + + + + + STATUS + Status + 0x4 + + + WFB + Wait For Break + [0:0] + + + BDF + Break Detected Flag + [1:1] + + + ISFIF + Inconsistent Sync Field Interrupt Flag + [3:3] + + + RXSIF + Receive Start Interrupt + [4:4] + read-only + + + DREIF + Data Register Empty Flag + [5:5] + read-only + + + TXCIF + Transmit Interrupt Flag + [6:6] + + + RXCIF + Receive Complete Interrupt Flag + [7:7] + read-only + + + + + TXDATAH + Transmit Data High Byte + 0x3 + + + DATA8 + Transmit Data Register (CHSIZE=9bit) + [0:0] + + + + + TXDATAL + Transmit Data Low Byte + 0x2 + + + DATA + Transmit Data Register + [7:0] + + + 0 + 255 + + + + + + + TXPLCTRL + IRCOM Transmitter Pulse Length Control + 0xD + + + TXPL + Transmit pulse length + [7:0] + + + 0 + 255 + + + + + + + + + USERROW + User Row + 0x1300 + + + USERROW0 + User Row Byte 0 + 0x0 + + + 0 + 255 + + + + + USERROW1 + User Row Byte 1 + 0x1 + + + 0 + 255 + + + + + USERROW10 + User Row Byte 10 + 0xA + + + 0 + 255 + + + + + USERROW11 + User Row Byte 11 + 0xB + + + 0 + 255 + + + + + USERROW12 + User Row Byte 12 + 0xC + + + 0 + 255 + + + + + USERROW13 + User Row Byte 13 + 0xD + + + 0 + 255 + + + + + USERROW14 + User Row Byte 14 + 0xE + + + 0 + 255 + + + + + USERROW15 + User Row Byte 15 + 0xF + + + 0 + 255 + + + + + USERROW16 + User Row Byte 16 + 0x10 + + + 0 + 255 + + + + + USERROW17 + User Row Byte 17 + 0x11 + + + 0 + 255 + + + + + USERROW18 + User Row Byte 18 + 0x12 + + + 0 + 255 + + + + + USERROW19 + User Row Byte 19 + 0x13 + + + 0 + 255 + + + + + USERROW2 + User Row Byte 2 + 0x2 + + + 0 + 255 + + + + + USERROW20 + User Row Byte 20 + 0x14 + + + 0 + 255 + + + + + USERROW21 + User Row Byte 21 + 0x15 + + + 0 + 255 + + + + + USERROW22 + User Row Byte 22 + 0x16 + + + 0 + 255 + + + + + USERROW23 + User Row Byte 23 + 0x17 + + + 0 + 255 + + + + + USERROW24 + User Row Byte 24 + 0x18 + + + 0 + 255 + + + + + USERROW25 + User Row Byte 25 + 0x19 + + + 0 + 255 + + + + + USERROW26 + User Row Byte 26 + 0x1A + + + 0 + 255 + + + + + USERROW27 + User Row Byte 27 + 0x1B + + + 0 + 255 + + + + + USERROW28 + User Row Byte 28 + 0x1C + + + 0 + 255 + + + + + USERROW29 + User Row Byte 29 + 0x1D + + + 0 + 255 + + + + + USERROW3 + User Row Byte 3 + 0x3 + + + 0 + 255 + + + + + USERROW30 + User Row Byte 30 + 0x1E + + + 0 + 255 + + + + + USERROW31 + User Row Byte 31 + 0x1F + + + 0 + 255 + + + + + USERROW32 + User Row Byte 32 + 0x20 + + + 0 + 255 + + + + + USERROW33 + User Row Byte 33 + 0x21 + + + 0 + 255 + + + + + USERROW34 + User Row Byte 34 + 0x22 + + + 0 + 255 + + + + + USERROW35 + User Row Byte 35 + 0x23 + + + 0 + 255 + + + + + USERROW36 + User Row Byte 36 + 0x24 + + + 0 + 255 + + + + + USERROW37 + User Row Byte 37 + 0x25 + + + 0 + 255 + + + + + USERROW38 + User Row Byte 38 + 0x26 + + + 0 + 255 + + + + + USERROW39 + User Row Byte 39 + 0x27 + + + 0 + 255 + + + + + USERROW4 + User Row Byte 4 + 0x4 + + + 0 + 255 + + + + + USERROW40 + User Row Byte 40 + 0x28 + + + 0 + 255 + + + + + USERROW41 + User Row Byte 41 + 0x29 + + + 0 + 255 + + + + + USERROW42 + User Row Byte 42 + 0x2A + + + 0 + 255 + + + + + USERROW43 + User Row Byte 43 + 0x2B + + + 0 + 255 + + + + + USERROW44 + User Row Byte 44 + 0x2C + + + 0 + 255 + + + + + USERROW45 + User Row Byte 45 + 0x2D + + + 0 + 255 + + + + + USERROW46 + User Row Byte 46 + 0x2E + + + 0 + 255 + + + + + USERROW47 + User Row Byte 47 + 0x2F + + + 0 + 255 + + + + + USERROW48 + User Row Byte 48 + 0x30 + + + 0 + 255 + + + + + USERROW49 + User Row Byte 49 + 0x31 + + + 0 + 255 + + + + + USERROW5 + User Row Byte 5 + 0x5 + + + 0 + 255 + + + + + USERROW50 + User Row Byte 50 + 0x32 + + + 0 + 255 + + + + + USERROW51 + User Row Byte 51 + 0x33 + + + 0 + 255 + + + + + USERROW52 + User Row Byte 52 + 0x34 + + + 0 + 255 + + + + + USERROW53 + User Row Byte 53 + 0x35 + + + 0 + 255 + + + + + USERROW54 + User Row Byte 54 + 0x36 + + + 0 + 255 + + + + + USERROW55 + User Row Byte 55 + 0x37 + + + 0 + 255 + + + + + USERROW56 + User Row Byte 56 + 0x38 + + + 0 + 255 + + + + + USERROW57 + User Row Byte 57 + 0x39 + + + 0 + 255 + + + + + USERROW58 + User Row Byte 58 + 0x3A + + + 0 + 255 + + + + + USERROW59 + User Row Byte 59 + 0x3B + + + 0 + 255 + + + + + USERROW6 + User Row Byte 6 + 0x6 + + + 0 + 255 + + + + + USERROW60 + User Row Byte 60 + 0x3C + + + 0 + 255 + + + + + USERROW61 + User Row Byte 61 + 0x3D + + + 0 + 255 + + + + + USERROW62 + User Row Byte 62 + 0x3E + + + 0 + 255 + + + + + USERROW63 + User Row Byte 63 + 0x3F + + + 0 + 255 + + + + + USERROW7 + User Row Byte 7 + 0x7 + + + 0 + 255 + + + + + USERROW8 + User Row Byte 8 + 0x8 + + + 0 + 255 + + + + + USERROW9 + User Row Byte 9 + 0x9 + + + 0 + 255 + + + + + + + VPORTA + Virtual Ports + 0x0 + + + DIR + Data Direction + 0x0 + + + 0 + 255 + + + + + IN + Input Value + 0x2 + + + 0 + 255 + + + + + INTFLAGS + Interrupt Flags + 0x3 + + + INT + Pin Interrupt + [7:0] + + + 0 + 255 + + + + + + + OUT + Output Value + 0x1 + + + 0 + 255 + + + + + + + VPORTB + Virtual Ports + 0x4 + + + DIR + Data Direction + 0x0 + + + 0 + 255 + + + + + IN + Input Value + 0x2 + + + 0 + 255 + + + + + INTFLAGS + Interrupt Flags + 0x3 + + + INT + Pin Interrupt + [7:0] + + + 0 + 255 + + + + + + + OUT + Output Value + 0x1 + + + 0 + 255 + + + + + + + VPORTC + Virtual Ports + 0x8 + + + DIR + Data Direction + 0x0 + + + 0 + 255 + + + + + IN + Input Value + 0x2 + + + 0 + 255 + + + + + INTFLAGS + Interrupt Flags + 0x3 + + + INT + Pin Interrupt + [7:0] + + + 0 + 255 + + + + + + + OUT + Output Value + 0x1 + + + 0 + 255 + + + + + + + VPORTD + Virtual Ports + 0xC + + + DIR + Data Direction + 0x0 + + + 0 + 255 + + + + + IN + Input Value + 0x2 + + + 0 + 255 + + + + + INTFLAGS + Interrupt Flags + 0x3 + + + INT + Pin Interrupt + [7:0] + + + 0 + 255 + + + + + + + OUT + Output Value + 0x1 + + + 0 + 255 + + + + + + + VPORTE + Virtual Ports + 0x10 + + + DIR + Data Direction + 0x0 + + + 0 + 255 + + + + + IN + Input Value + 0x2 + + + 0 + 255 + + + + + INTFLAGS + Interrupt Flags + 0x3 + + + INT + Pin Interrupt + [7:0] + + + 0 + 255 + + + + + + + OUT + Output Value + 0x1 + + + 0 + 255 + + + + + + + VPORTF + Virtual Ports + 0x14 + + + DIR + Data Direction + 0x0 + + + 0 + 255 + + + + + IN + Input Value + 0x2 + + + 0 + 255 + + + + + INTFLAGS + Interrupt Flags + 0x3 + + + INT + Pin Interrupt + [7:0] + + + 0 + 255 + + + + + + + OUT + Output Value + 0x1 + + + 0 + 255 + + + + + + + VREF + Voltage reference + 0xA0 + + + CTRLA + Control A + 0x0 + + + AC0REFSEL + AC0 reference select + [2:0] + + true + + + + 0V55 + Voltage reference at 0.55V + 0 + + + 1V1 + Voltage reference at 1.1V + 1 + + + 2V5 + Voltage reference at 2.5V + 2 + + + 4V34 + Voltage reference at 4.34V + 3 + + + 1V5 + Voltage reference at 1.5V + 4 + + + AVDD + AVDD + 7 + + + + + ADC0REFSEL + ADC0 reference select + [6:4] + + true + + + + 0V55 + Voltage reference at 0.55V + 0 + + + 1V1 + Voltage reference at 1.1V + 1 + + + 2V5 + Voltage reference at 2.5V + 2 + + + 4V34 + Voltage reference at 4.34V + 3 + + + 1V5 + Voltage reference at 1.5V + 4 + + + + + + + CTRLB + Control B + 0x1 + + + AC0REFEN + AC0 DACREF reference enable + [0:0] + + + ADC0REFEN + ADC0 reference enable + [1:1] + + + + + + + WDT + Watch-Dog Timer + 0x100 + + + CTRLA + Control A + 0x0 + + + PERIOD + Period + [3:0] + + true + + + + OFF + Off + 0 + + + 8CLK + 8 cycles (8ms) + 1 + + + 16CLK + 16 cycles (16ms) + 2 + + + 32CLK + 32 cycles (32ms) + 3 + + + 64CLK + 64 cycles (64ms) + 4 + + + 128CLK + 128 cycles (0.128s) + 5 + + + 256CLK + 256 cycles (0.256s) + 6 + + + 512CLK + 512 cycles (0.512s) + 7 + + + 1KCLK + 1K cycles (1.0s) + 8 + + + 2KCLK + 2K cycles (2.0s) + 9 + + + 4KCLK + 4K cycles (4.1s) + 10 + + + 8KCLK + 8K cycles (8.2s) + 11 + + + + + WINDOW + Window + [7:4] + + true + + + + OFF + Off + 0 + + + 8CLK + 8 cycles (8ms) + 1 + + + 16CLK + 16 cycles (16ms) + 2 + + + 32CLK + 32 cycles (32ms) + 3 + + + 64CLK + 64 cycles (64ms) + 4 + + + 128CLK + 128 cycles (0.128s) + 5 + + + 256CLK + 256 cycles (0.256s) + 6 + + + 512CLK + 512 cycles (0.512s) + 7 + + + 1KCLK + 1K cycles (1.0s) + 8 + + + 2KCLK + 2K cycles (2.0s) + 9 + + + 4KCLK + 4K cycles (4.1s) + 10 + + + 8KCLK + 8K cycles (8.2s) + 11 + + + + + + + STATUS + Status + 0x1 + + + SYNCBUSY + Syncronization busy + [0:0] + read-only + + + LOCK + Lock enable + [7:7] + + + + + + + \ No newline at end of file diff --git a/misc/svd/atmega48p.svd b/misc/svd/atmega48p.svd new file mode 100644 index 0000000..b2e2120 --- /dev/null +++ b/misc/svd/atmega48p.svd @@ -0,0 +1,2944 @@ + + Atmel + ATmega48P + 8 + 8 + read-write + 0 + 0xff + + + AC + Analog Comparator + 0x50 + + + ACSR + Analog Comparator Control And Status Register + 0x0 + read-write + + + ACIS + Analog Comparator Interrupt Mode Select + [1:0] + + true + + ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 + + + ACIC + Analog Comparator Input Capture Enable + [2:2] + + + ACIE + Analog Comparator Interrupt Enable + [3:3] + + + ACI + Analog Comparator Interrupt Flag + [4:4] + + + ACO + Analog Compare Output + [5:5] + read-only + + ACBG + Analog Comparator Bandgap Select + [6:6] + + + ACD + Analog Comparator Disable + [7:7] + + + + + DIDR1 + Digital Input Disable Register 1 + 0x2F + + + AIN0D + AIN0 Digital Input Disable + [0:0] + + + AIN1D + AIN1 Digital Input Disable + [1:1] + + + + + + + ADC + Analog-to-Digital Converter + 0x78 + + + ADC + ADC Data Register Bytes + 0x0 + 16 + + + 0 + 65535 + + + + + ADCSRA + The ADC Control and Status register A + 0x2 + read-write + + + ADPS + ADC Prescaler Select Bits + [2:0] + + true + + ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 + + + ADIE + ADC Interrupt Enable + [3:3] + + + ADIF + ADC Interrupt Flag + [4:4] + + + ADATE + ADC Auto Trigger Enable + [5:5] + + + ADSC + ADC Start Conversion + [6:6] + + + ADEN + ADC Enable + [7:7] + + + + + ADCSRB + The ADC Control and Status register B + 0x3 + + + ADTS + ADC Auto Trigger Source bits + [2:0] + + true + + + + VAL_0x00 + Free Running mode + 0 + + + VAL_0x01 + Analog Comparator + 1 + + + VAL_0x02 + External Interrupt Request 0 + 2 + + + VAL_0x03 + Timer/Counter0 Compare Match A + 3 + + + VAL_0x04 + Timer/Counter0 Overflow + 4 + + + VAL_0x05 + Timer/Counter1 Compare Match B + 5 + + + VAL_0x06 + Timer/Counter1 Overflow + 6 + + + VAL_0x07 + Timer/Counter1 Capture Event + 7 + + + + + ACME + <TBD> + [6:6] + + + + + ADMUX + The ADC multiplexer Selection Register + 0x4 + + + MUX + Analog Channel Selection Bits + [3:0] + + true + + + + ADC0 + ADC Single Ended Input pin 0 + 0 + + + ADC1 + ADC Single Ended Input pin 1 + 1 + + + ADC2 + ADC Single Ended Input pin 2 + 2 + + + ADC3 + ADC Single Ended Input pin 3 + 3 + + + ADC4 + ADC Single Ended Input pin 4 + 4 + + + ADC5 + ADC Single Ended Input pin 5 + 5 + + + ADC6 + ADC Single Ended Input pin 6 + 6 + + + ADC7 + ADC Single Ended Input pin 7 + 7 + + + TEMPSENS + Temperature sensor + 8 + + + ADC_VBG + Internal Reference (VBG) + 14 + + + ADC_GND + 0V (GND) + 15 + + + + + ADLAR + Left Adjust Result + [5:5] + + + REFS + Reference Selection Bits + [7:6] + + true + + REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 + + + + + DIDR0 + Digital Input Disable Register + 0x6 + + + ADC0D + <TBD> + [0:0] + + + ADC1D + <TBD> + [1:1] + + + ADC2D + <TBD> + [2:2] + + + ADC3D + <TBD> + [3:3] + + + ADC4D + <TBD> + [4:4] + + + ADC5D + <TBD> + [5:5] + + + + + + + CPU + CPU Registers + 0x3E + + RESET + External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + 0 + + + INT0 + External Interrupt Request 0 + 1 + + + INT1 + External Interrupt Request 1 + 2 + + + PCINT0 + Pin Change Interrupt Request 0 + 3 + + + PCINT1 + Pin Change Interrupt Request 0 + 4 + + + PCINT2 + Pin Change Interrupt Request 1 + 5 + + + WDT + Watchdog Time-out Interrupt + 6 + + + TIMER2_COMPA + Timer/Counter2 Compare Match A + 7 + + + TIMER2_COMPB + Timer/Counter2 Compare Match A + 8 + + + TIMER2_OVF + Timer/Counter2 Overflow + 9 + + + TIMER1_CAPT + Timer/Counter1 Capture Event + 10 + + + TIMER1_COMPA + Timer/Counter1 Compare Match A + 11 + + + TIMER1_COMPB + Timer/Counter1 Compare Match B + 12 + + + TIMER1_OVF + Timer/Counter1 Overflow + 13 + + + TIMER0_COMPA + TimerCounter0 Compare Match A + 14 + + + TIMER0_COMPB + TimerCounter0 Compare Match B + 15 + + + TIMER0_OVF + Timer/Couner0 Overflow + 16 + + + SPI_STC + SPI Serial Transfer Complete + 17 + + + USART_RX + USART Rx Complete + 18 + + + USART_UDRE + USART, Data Register Empty + 19 + + + USART_TX + USART Tx Complete + 20 + + + ADC + ADC Conversion Complete + 21 + + + EE_READY + EEPROM Ready + 22 + + + ANALOG_COMP + Analog Comparator + 23 + + + TWI + Two-wire Serial Interface + 24 + + + SPM_Ready + Store Program Memory Read + 25 + + + + CLKPR + Clock Prescale Register + 0x23 + read-only + + + CLKPS + Clock Prescaler Select Bits + [3:0] + + true + + + + VAL_0x00 + 1 + 0 + + + VAL_0x01 + 2 + 1 + + + VAL_0x02 + 4 + 2 + + + VAL_0x03 + 8 + 3 + + + VAL_0x04 + 16 + 4 + + + VAL_0x05 + 32 + 5 + + + VAL_0x06 + 64 + 6 + + + VAL_0x07 + 128 + 7 + + + VAL_0x08 + 256 + 8 + + + + + CLKPCE + Clock Prescaler Change Enable + [7:7] + + + + + GPIOR0 + General Purpose I/O Register 0 + 0x0 + + + 0 + 255 + + + + + GPIOR1 + General Purpose I/O Register 1 + 0xC + + + 0 + 255 + + + + + GPIOR2 + General Purpose I/O Register 2 + 0xD + + + 0 + 255 + + + + + MCUCR + MCU Control Register + 0x17 + + + PUD + <TBD> + [4:4] + + + BODSE + BOD Sleep Enable + [5:5] + + + BODS + BOD Sleep + [6:6] + + + + + MCUSR + MCU Status Register + 0x16 + + + PORF + Power-on reset flag + [0:0] + + + EXTRF + External Reset Flag + [1:1] + + + BORF + Brown-out Reset Flag + [2:2] + + + WDRF + Watchdog Reset Flag + [3:3] + + + + + OSCCAL + Oscillator Calibration Value + 0x28 + read-only + + + OSCCAL + Oscillator Calibration + [7:0] + + + 0 + 255 + + + + + + + PRR + Power Reduction Register + 0x26 + read-only + + + PRADC + Power Reduction ADC + [0:0] + + + PRUSART0 + Power Reduction USART + [1:1] + + + PRSPI + Power Reduction Serial Peripheral Interface + [2:2] + + + PRTIM1 + Power Reduction Timer/Counter1 + [3:3] + + + PRTIM0 + Power Reduction Timer/Counter0 + [5:5] + + + PRTIM2 + Power Reduction Timer/Counter2 + [6:6] + + + PRTWI + Power Reduction TWI + [7:7] + + + + + SMCR + Sleep Mode Control Register + 0x15 + + + SE + Sleep Enable + [0:0] + + + SM + Sleep Mode Select Bits + [3:1] + + true + + + + IDLE + Idle + 0 + + + ADC + ADC Noise Reduction (If Available) + 1 + + + PDOWN + Power Down + 2 + + + PSAVE + Power Save + 3 + + + VAL_0x04 + Reserved + 4 + + + VAL_0x05 + Reserved + 5 + + + STDBY + Standby + 6 + + + ESTDBY + Extended Standby + 7 + + + + + + + SPMCSR + Store Program Memory Control and Status Register + 0x19 + + + SELFPRGEN + Self Programming Enable + [0:0] + + + PGERS + Page Erase + [1:1] + + + PGWRT + Page Write + [2:2] + + + BLBSET + Boot Lock Bit Set + [3:3] + + + RWWSRE + Read-While-Write section read enable + [4:4] + + + RWWSB + Read-While-Write Section Busy + [6:6] + + + SPMIE + SPM Interrupt Enable + [7:7] + + + + + + + EEPROM + EEPROM + 0x3F + + + EEARL + EEPROM Address Register Low Byte + 0x2 + + + 0 + 255 + + + + + EECR + EEPROM Control Register + 0x0 + + + EERE + EEPROM Read Enable + [0:0] + + + EEPE + EEPROM Write Enable + [1:1] + + + EEMPE + EEPROM Master Write Enable + [2:2] + + + EERIE + EEPROM Ready Interrupt Enable + [3:3] + + + EEPM + EEPROM Programming Mode Bits + [5:4] + + true + + + + VAL_0x00 + Erase and Write in one operation + 0 + + + VAL_0x01 + Erase Only + 1 + + + VAL_0x02 + Write Only + 2 + + + + + + + EEDR + EEPROM Data Register + 0x1 + + + 0 + 255 + + + + + + + EXINT + External Interrupts + 0x3B + + + EICRA + External Interrupt Control Register + 0x2E + + + ISC0 + External Interrupt Sense Control 0 Bits + [1:0] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC1 + External Interrupt Sense Control 1 Bits + [3:2] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + + + EIFR + External Interrupt Flag Register + 0x1 + read-only + + + INTF + External Interrupt Flags + [1:0] + + + 0 + 3 + + + + + + + EIMSK + External Interrupt Mask Register + 0x2 + + + INT + External Interrupt Request 1 Enable + [1:0] + + + 0 + 3 + + + + + + + PCICR + Pin Change Interrupt Control Register + 0x2D + + + PCIE + Pin Change Interrupt Enables + [2:0] + + + 0 + 7 + + + + + + + PCIFR + Pin Change Interrupt Flag Register + 0x0 + read-only + + + PCIF + Pin Change Interrupt Flags + [2:0] + + + 0 + 7 + + + + + + + PCMSK0 + Pin Change Mask Register 0 + 0x30 + + + PCINT + Pin Change Enable Masks + [7:0] + + + 0 + 255 + + + + + + + PCMSK1 + Pin Change Mask Register 1 + 0x31 + + + PCINT + Pin Change Enable Masks + [6:0] + + + 0 + 127 + + + + + + + PCMSK2 + Pin Change Mask Register 2 + 0x32 + + + PCINT + Pin Change Enable Masks + [7:0] + + + 0 + 255 + + + + + + + + + FUSE + Fuses + 0x0 + + + EXTENDED + <TBD> + 0x2 + + + SELFPRGEN + Self Programming enable + [0:0] + + + + + HIGH + <TBD> + 0x1 + + + BODLEVEL + Brown-out Detector trigger level + [2:0] + + true + + + + 4V3 + Brown-out detection at VCC=4.3 V + 4 + + + 2V7 + Brown-out detection at VCC=2.7 V + 5 + + + 1V8 + Brown-out detection at VCC=1.8 V + 6 + + + DISABLED + Brown-out detection disabled + 7 + + + + + EESAVE + Preserve EEPROM through the Chip Erase cycle + [3:3] + + + WDTON + Watch-dog Timer always on + [4:4] + + + SPIEN + Serial program downloading (SPI) enabled + [5:5] + + + DWEN + Debug Wire enable + [6:6] + + + RSTDISBL + Reset Disabled (Enable PC6 as i/o pin) + [7:7] + + + + + LOW + <TBD> + 0x0 + + + SUT_CKSEL + Select Clock Source + [5:0] + + true + + + + EXTCLK_6CK_14CK_0MS + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 0 + + + INTRCOSC_8MHZ_6CK_14CK_0MS + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 2 + + + INTRCOSC_128KHZ_6CK_14CK_0MS + Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 3 + + + EXTLOFXTAL_1KCK_14CK_0MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms + 4 + + + EXTLOFXTAL_32KCK_14CK_0MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms + 5 + + + EXTFSXTAL_258CK_14CK_4MS1 + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 6 + + + EXTFSXTAL_1KCK_14CK_65MS + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 7 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 8 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 9 + + + EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 10 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 11 + + + EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 12 + + + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 13 + + + EXTXOSC_8MHZ_XX_258CK_14CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 14 + + + EXTXOSC_8MHZ_XX_1KCK_14CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 15 + + + EXTCLK_6CK_14CK_4MS1 + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + 16 + + + INTRCOSC_8MHZ_6CK_14CK_4MS1 + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + 18 + + + INTRCOSC_128KHZ_6CK_14CK_4MS1 + Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + 19 + + + EXTLOFXTAL_1KCK_14CK_4MS1 + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms + 20 + + + EXTLOFXTAL_32KCK_14CK_4MS1 + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms + 21 + + + EXTFSXTAL_258CK_14CK_65MS + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 22 + + + EXTFSXTAL_16KCK_14CK_0MS + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 23 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 24 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 25 + + + EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 26 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 27 + + + EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 28 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 29 + + + EXTXOSC_8MHZ_XX_258CK_14CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 30 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 31 + + + EXTCLK_6CK_14CK_65MS + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + 32 + + + INTRCOSC_8MHZ_6CK_14CK_65MS_DEFAULT + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; default value + 34 + + + INTRCOSC_128KHZ_6CK_14CK_65MS + Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + 35 + + + EXTLOFXTAL_1KCK_14CK_65MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms + 36 + + + EXTLOFXTAL_32KCK_14CK_65MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms + 37 + + + EXTFSXTAL_1KCK_14CK_0MS + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 38 + + + EXTFSXTAL_16KCK_14CK_4MS1 + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 39 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 40 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 41 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 42 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 43 + + + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 44 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 45 + + + EXTXOSC_8MHZ_XX_1KCK_14CK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 46 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 47 + + + EXTFSXTAL_1KCK_14CK_4MS1 + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 54 + + + EXTFSXTAL_16KCK_14CK_65MS + Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 55 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 56 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 57 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 58 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 59 + + + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 60 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 61 + + + EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 62 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 63 + + + + + CKOUT + Clock output on PORTB0 + [6:6] + + + CKDIV8 + Divide clock by 8 internally + [7:7] + + + + + + + LOCKBIT + Lockbits + 0x0 + + + LOCKBIT + <TBD> + 0x0 + + + LB + Memory Lock + [1:0] + + true + + + + PROG_VER_DISABLED + Further programming and verification disabled + 0 + + + PROG_DISABLED + Further programming disabled + 2 + + + NO_LOCK + No memory lock features enabled + 3 + + + + + + + + + PORTB + I/O Port + 0x23 + + + DDRB + Port B Data Direction Register + 0x1 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PINB + Port B Input Pins + 0x0 + read-write + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PORTB + Port B Data Register + 0x2 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + + + PORTC + I/O Port + 0x26 + + + DDRC + Port C Data Direction Register + 0x1 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + + + PINC + Port C Input Pins + 0x0 + read-write + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + + + PORTC + Port C Data Register + 0x2 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + + + + + PORTD + I/O Port + 0x29 + + + DDRD + Port D Data Direction Register + 0x1 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PIND + Port D Input Pins + 0x0 + read-write + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PORTD + Port D Data Register + 0x2 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + + + SPI + Serial Peripheral Interface + 0x4C + + + SPCR + SPI Control Register + 0x0 + + + SPR + SPI Clock Rate Selects + [1:0] + + true + + SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 + + + CPHA + Clock Phase + [2:2] + + + CPOL + Clock polarity + [3:3] + + + MSTR + Master/Slave Select + [4:4] + + + DORD + Data Order + [5:5] + + + SPE + SPI Enable + [6:6] + + + SPIE + SPI Interrupt Enable + [7:7] + + + + + SPDR + SPI Data Register + 0x2 + + + 0 + 255 + + + + + SPSR + SPI Status Register + 0x1 + read-write + + + SPI2X + Double SPI Speed Bit + [0:0] + read-write + + WCOL + Write Collision Flag + [6:6] + read-only + + SPIF + SPI Interrupt Flag + [7:7] + read-only + + + + + + TC0 + Timer/Counter, 8-bit + 0x35 + + + GTCCR + General Timer/Counter Control Register + 0xE + + + PSRSYNC + Prescaler Reset Timer/Counter1 and Timer/Counter0 + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + OCR0A + Timer/Counter0 Output Compare Register + 0x12 + + + 0 + 255 + + + + + OCR0B + Timer/Counter0 Output Compare Register + 0x13 + + + 0 + 255 + + + + + TCCR0A + Timer/Counter Control Register A + 0xF + + + WGM0 + Waveform Generation Mode + [1:0] + + true + WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 + + + COM0B + Compare Output B Mode + [5:4] + + true + COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 + + + COM0A + Compare Output A Mode + [7:6] + + true + + + + + + TCCR0B + Timer/Counter Control Register B + 0x10 + + + CS0 + Clock Select + [2:0] + + true + + CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM02 + Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) + [3:3] + + + FOC0B + Force Output Compare B + [6:6] + write-only + + FOC0A + Force Output Compare A + [7:7] + write-only + + + + TCNT0 + Timer/Counter0 + 0x11 + + + 0 + 255 + + + + + TIFR0 + Timer/Counter0 Interrupt Flag register + 0x0 + read-write + + + TOV0 + Timer/Counter0 Overflow Flag + [0:0] + + + OCF0A + Timer/Counter0 Output Compare Flag 0A + [1:1] + + + OCF0B + Timer/Counter0 Output Compare Flag 0B + [2:2] + + + + + TIMSK0 + Timer/Counter0 Interrupt Mask Register + 0x39 + + + TOIE0 + Timer/Counter0 Overflow Interrupt Enable + [0:0] + + + OCIE0A + Timer/Counter0 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE0B + Timer/Counter0 Output Compare Match B Interrupt Enable + [2:2] + + + + + + + TC1 + Timer/Counter, 16-bit + 0x36 + + + GTCCR + General Timer/Counter Control Register + 0xD + + + PSRSYNC + Prescaler Reset Timer/Counter1 and Timer/Counter0 + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + ICR1 + Timer/Counter1 Input Capture Register Bytes + 0x50 + 16 + + + 0 + 65535 + + + + + OCR1A + Timer/Counter1 Output Compare Register Bytes + 0x52 + 16 + + + 0 + 65535 + + + + + OCR1B + Timer/Counter1 Output Compare Register Bytes + 0x54 + 16 + + + 0 + 65535 + + + + + TCCR1A + Timer/Counter1 Control Register A + 0x4A + + + WGM1 + Waveform Generation Mode + [1:0] + + + 0 + 3 + + + + + COM1B + Compare Output Mode 1B, bits + [5:4] + + true + COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM1A + Compare Output Mode 1A, bits + [7:6] + + true + + + + + + TCCR1B + Timer/Counter1 Control Register B + 0x4B + + + CS1 + Prescaler source of Timer/Counter 1 + [2:0] + + true + CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM1 + Waveform Generation Mode + [4:3] + + + 0 + 3 + + + + + ICES1 + Input Capture 1 Edge Select + [6:6] + + + ICNC1 + Input Capture 1 Noise Canceler + [7:7] + + + + + TCCR1C + Timer/Counter1 Control Register C + 0x4C + + + FOC1B + <TBD> + [6:6] + write-only + + FOC1A + <TBD> + [7:7] + write-only + + + + TCNT1 + Timer/Counter1 Bytes + 0x4E + 16 + + + 0 + 65535 + + + + + TIFR1 + Timer/Counter Interrupt Flag register + 0x0 + read-write + + + TOV1 + Timer/Counter1 Overflow Flag + [0:0] + + + OCF1A + Output Compare Flag 1A + [1:1] + + + OCF1B + Output Compare Flag 1B + [2:2] + + + ICF1 + Input Capture Flag 1 + [5:5] + + + + + TIMSK1 + Timer/Counter Interrupt Mask Register + 0x39 + + + TOIE1 + Timer/Counter1 Overflow Interrupt Enable + [0:0] + + + OCIE1A + Timer/Counter1 Output CompareA Match Interrupt Enable + [1:1] + + + OCIE1B + Timer/Counter1 Output CompareB Match Interrupt Enable + [2:2] + + + ICIE1 + Timer/Counter1 Input Capture Interrupt Enable + [5:5] + + + + + + + TC2 + Timer/Counter, 8-bit Async + 0x37 + + + ASSR + Asynchronous Status Register + 0x7F + + + TCR2BUB + Timer/Counter Control Register2 Update Busy + [0:0] + + + TCR2AUB + Timer/Counter Control Register2 Update Busy + [1:1] + + + OCR2BUB + Output Compare Register 2 Update Busy + [2:2] + + + OCR2AUB + Output Compare Register2 Update Busy + [3:3] + + + TCN2UB + Timer/Counter2 Update Busy + [4:4] + + + AS2 + Asynchronous Timer/Counter2 + [5:5] + + + EXCLK + Enable External Clock Input + [6:6] + + + + + GTCCR + General Timer Counter Control register + 0xC + + + PSRASY + Prescaler Reset Timer/Counter2 + [1:1] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + OCR2A + Timer/Counter2 Output Compare Register A + 0x7C + + + 0 + 255 + + + + + OCR2B + Timer/Counter2 Output Compare Register B + 0x7D + + + 0 + 255 + + + + + TCCR2A + Timer/Counter2 Control Register A + 0x79 + + + WGM2 + Waveform Genration Mode + [1:0] + + true + WGM2read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 + + + COM2B + Compare Output B Mode + [5:4] + + true + COM2Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 + + + COM2A + Compare Output A Mode + [7:6] + + true + + + + + + TCCR2B + Timer/Counter2 Control Register B + 0x7A + + + CS2 + Clock Select bits + [2:0] + + true + + CS2read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_32Running, CLK/323PRESCALE_64Running, CLK/644PRESCALE_128Running, CLK/1285PRESCALE_256Running, CLK/2566PRESCALE_1024Running, CLK/10247 + + + WGM22 + Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) + [3:3] + + + FOC2B + Force Output Compare B + [6:6] + write-only + + FOC2A + Force Output Compare A + [7:7] + write-only + + + + TCNT2 + Timer/Counter2 + 0x7B + + + 0 + 255 + + + + + TIFR2 + Timer/Counter Interrupt Flag Register + 0x0 + read-write + + + TOV2 + Timer/Counter2 Overflow Flag + [0:0] + + + OCF2A + Output Compare Flag 2A + [1:1] + + + OCF2B + Output Compare Flag 2B + [2:2] + + + + + TIMSK2 + Timer/Counter Interrupt Mask register + 0x39 + + + TOIE2 + Timer/Counter2 Overflow Interrupt Enable + [0:0] + + + OCIE2A + Timer/Counter2 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE2B + Timer/Counter2 Output Compare Match B Interrupt Enable + [2:2] + + + + + + + TWI + Two Wire Serial Interface + 0xB8 + + + TWAMR + TWI (Slave) Address Mask Register + 0x5 + + + TWAM + TWI (Slave) Address Mask Bits + [7:1] + + + 0 + 127 + + + + + + + TWAR + TWI (Slave) Address register + 0x2 + + + TWGCE + TWI General Call Recognition Enable Bit + [0:0] + + + TWA + TWI (Slave) Address register Bits + [7:1] + + + 0 + 127 + + + + + + + TWBR + TWI Bit Rate register + 0x0 + + + 0 + 255 + + + + + TWCR + TWI Control Register + 0x4 + read-write + + + TWIE + TWI Interrupt Enable + [0:0] + + + TWEN + TWI Enable Bit + [2:2] + + + TWWC + TWI Write Collition Flag + [3:3] + read-only + + TWSTO + TWI Stop Condition Bit + [4:4] + + + TWSTA + TWI Start Condition Bit + [5:5] + + + TWEA + TWI Enable Acknowledge Bit + [6:6] + + + TWINT + TWI Interrupt Flag + [7:7] + + + + + TWDR + TWI Data register + 0x3 + + + 0 + 255 + + + + + TWSR + TWI Status Register + 0x1 + + + TWPS + TWI Prescaler + [1:0] + + true + + TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 + + + TWS + TWI Status + [7:3] + read-only + + 0 + 31 + + + + + + + + + USART0 + USART + 0xC0 + + + UBRR0 + USART Baud Rate Register Bytes + 0x4 + 16 + + + 0 + 65535 + + + + + UCSR0A + USART Control and Status Register A + 0x0 + read-write + + + MPCM0 + Multi-processor Communication Mode + [0:0] + + + U2X0 + Double the USART transmission speed + [1:1] + + + UPE0 + Parity Error + [2:2] + read-only + + DOR0 + Data overRun + [3:3] + read-only + + FE0 + Framing Error + [4:4] + read-only + + UDRE0 + USART Data Register Empty + [5:5] + read-only + + TXC0 + USART Transmit Complete + [6:6] + + + RXC0 + USART Receive Complete + [7:7] + read-only + + + + UCSR0B + USART Control and Status Register B + 0x1 + + + TXB80 + Transmit Data Bit 8 + [0:0] + + + RXB80 + Receive Data Bit 8 + [1:1] + read-only + + UCSZ02 + Character Size - together with UCSZ0 in UCSR0C + [2:2] + + + TXEN0 + Transmitter Enable + [3:3] + + + RXEN0 + Receiver Enable + [4:4] + + + UDRIE0 + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE0 + TX Complete Interrupt Enable + [6:6] + + + RXCIE0 + RX Complete Interrupt Enable + [7:7] + + + + + UCSR0C + USART Control and Status Register C + 0x2 + + + UCPOL0 + Clock Polarity + [0:0] + UCPOL0read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 + + + UCSZ0 + Character Size - together with UCSZ2 in UCSR0B + [2:1] + + + 0 + 3 + + + UCSZ0read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 + + + USBS0 + Stop Bit Select + [3:3] + + true + + USBS0read-writeSTOP11-bit0STOP22-bit1 + + + UPM0 + Parity Mode Bits + [5:4] + + true + + UPM0read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 + + + UMSEL0 + USART Mode Select + [7:6] + + true + + UMSEL0read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 + + + + + UDR0 + USART I/O Data Register + 0x6 + + + 0 + 255 + + + + + + + WDT + Watchdog Timer + 0x60 + + + WDTCSR + Watchdog Timer Control Register + 0x0 + read-write + + + WDE + Watch Dog Enable + [3:3] + + + WDCE + Watchdog Change Enable + [4:4] + + + WDIE + Watchdog Timeout Interrupt Enable + [6:6] + + + WDIF + Watchdog Timeout Interrupt Flag + [7:7] + + WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 + + WDPHWatchdog Timer Prescaler - High Bit[5:5] + + + + + + \ No newline at end of file diff --git a/misc/svd/atmega64.svd b/misc/svd/atmega64.svd new file mode 100644 index 0000000..60a69bf --- /dev/null +++ b/misc/svd/atmega64.svd @@ -0,0 +1,4326 @@ + + Atmel + ATmega64 + 8 + 8 + read-write + 0 + 0xff + + + AC + Analog Comparator + 0x28 + + + ACSR + Analog Comparator Control And Status Register + 0x0 + read-write + + + ACIS + Analog Comparator Interrupt Mode Select + [1:0] + + true + + ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 + + + ACIC + Analog Comparator Input Capture Enable + [2:2] + + + ACIE + Analog Comparator Interrupt Enable + [3:3] + + + ACI + Analog Comparator Interrupt Flag + [4:4] + + + ACO + Analog Compare Output + [5:5] + read-only + + ACBG + Analog Comparator Bandgap Select + [6:6] + + + ACD + Analog Comparator Disable + [7:7] + + + + + SFIOR + Special Function IO Register + 0x18 + + + ACME + Analog Comparator Multiplexer Enable + [3:3] + + + + + + + ADC + Analog-to-Digital Converter + 0x24 + + + ADC + ADC Data Register Bytes + 0x0 + 16 + + + 0 + 65535 + + + + + ADCSRA + The ADC Control and Status register A + 0x2 + read-write + + + ADPS + ADC Prescaler Select Bits + [2:0] + + true + + ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 + + + ADIE + ADC Interrupt Enable + [3:3] + + + ADIF + ADC Interrupt Flag + [4:4] + + + ADATE + ADC Auto Trigger Enable + [5:5] + + + ADSC + ADC Start Conversion + [6:6] + + + ADEN + ADC Enable + [7:7] + + + + + ADCSRB + The ADC Control and Status register B + 0x6A + + + ADTS + ADC Auto Trigger Source bits + [2:0] + + true + + + + VAL_0x00 + Free Running mode + 0 + + + VAL_0x01 + Analog Comparator + 1 + + + VAL_0x02 + External Interrupt Request 0 + 2 + + + VAL_0x03 + Timer/Counter0 Compare Match A + 3 + + + VAL_0x04 + Timer/Counter0 Overflow + 4 + + + VAL_0x05 + Timer/Counter1 Compare Match B + 5 + + + VAL_0x06 + Timer/Counter1 Overflow + 6 + + + VAL_0x07 + Timer/Counter1 Capture Event + 7 + + + + + + + ADMUX + The ADC multiplexer Selection Register + 0x3 + + + MUX + Analog Channel and Gain Selection Bits + [4:0] + + + 0 + 31 + + + + + ADLAR + Left Adjust Result + [5:5] + + + REFS + Reference Selection Bits + [7:6] + + true + + REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 + + + + + + + BOOT_LOAD + Bootloader + 0x68 + + + SPMCSR + Store Program Memory Control Register + 0x0 + + + SPMEN + Store Program Memory Enable + [0:0] + + + PGERS + Page Erase + [1:1] + + + PGWRT + Page Write + [2:2] + + + BLBSET + Boot Lock Bit Set + [3:3] + + + RWWSRE + Read While Write section read enable + [4:4] + + + RWWSB + Read While Write Section Busy + [6:6] + + + SPMIE + SPM Interrupt Enable + [7:7] + + + + + + + CPU + CPU Registers + 0x54 + + RESET + External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + 0 + + + INT0 + External Interrupt Request 0 + 1 + + + INT1 + External Interrupt Request 1 + 2 + + + INT2 + External Interrupt Request 2 + 3 + + + INT3 + External Interrupt Request 3 + 4 + + + INT4 + External Interrupt Request 4 + 5 + + + INT5 + External Interrupt Request 5 + 6 + + + INT6 + External Interrupt Request 6 + 7 + + + INT7 + External Interrupt Request 7 + 8 + + + TIMER2_COMP + Timer/Counter2 Compare Match + 9 + + + TIMER2_OVF + Timer/Counter2 Overflow + 10 + + + TIMER1_CAPT + Timer/Counter1 Capture Event + 11 + + + TIMER1_COMPA + Timer/Counter1 Compare Match A + 12 + + + TIMER1_COMPB + Timer/Counter Compare Match B + 13 + + + TIMER1_OVF + Timer/Counter1 Overflow + 14 + + + TIMER0_COMP + Timer/Counter0 Compare Match + 15 + + + TIMER0_OVF + Timer/Counter0 Overflow + 16 + + + SPI_STC + SPI Serial Transfer Complete + 17 + + + USART0_RX + USART0, Rx Complete + 18 + + + USART0_UDRE + USART0 Data Register Empty + 19 + + + USART0_TX + USART0, Tx Complete + 20 + + + ADC + ADC Conversion Complete + 21 + + + EE_READY + EEPROM Ready + 22 + + + ANALOG_COMP + Analog Comparator + 23 + + + TIMER1_COMPC + Timer/Counter1 Compare Match C + 24 + + + TIMER3_CAPT + Timer/Counter3 Capture Event + 25 + + + TIMER3_COMPA + Timer/Counter3 Compare Match A + 26 + + + TIMER3_COMPB + Timer/Counter3 Compare Match B + 27 + + + TIMER3_COMPC + Timer/Counter3 Compare Match C + 28 + + + TIMER3_OVF + Timer/Counter3 Overflow + 29 + + + USART1_RX + USART1, Rx Complete + 30 + + + USART1_UDRE + USART1, Data Register Empty + 31 + + + USART1_TX + USART1, Tx Complete + 32 + + + TWI + 2-wire Serial Interface + 33 + + + SPM_READY + Store Program Memory Read + 34 + + + + MCUCR + MCU Control Register + 0x1 + + + IVCE + Interrupt Vector Change Enable + [0:0] + + + IVSEL + Interrupt Vector Select + [1:1] + + + SM2 + Sleep Mode Select + [2:2] + + true + + + + IDLE + Idle + 0 + + + + + SM + Sleep Mode Select + [4:3] + + + 0 + 3 + + + + + SE + Sleep Enable + [5:5] + + + SRW10 + External SRAM Wait State Select + [6:6] + + + SRE + External SRAM Enable + [7:7] + + + + + MCUCSR + MCU Control And Status Register + 0x0 + + + PORF + Power-on reset flag + [0:0] + + + EXTRF + External Reset Flag + [1:1] + + + BORF + Brown-out Reset Flag + [2:2] + + + WDRF + Watchdog Reset Flag + [3:3] + + + JTRF + JTAG Reset Flag + [4:4] + + + JTD + JTAG Interface Disable + [7:7] + + + + + OSCCAL + Oscillator Calibration Value + 0x1B + + + OSCCAL + Oscillator Calibration + [7:0] + + + 0 + 255 + + + + + + + XDIV + XTAL Divide Control Register + 0x8 + + + XDIV + XTAl Divide Select Bits + [6:0] + + + 0 + 127 + + + + + XDIVEN + XTAL Divide Enable + [7:7] + + + + + XMCRA + External Memory Control Register A + 0x19 + + + SRW11 + Wait state select bit upper page + [1:1] + + + SRW0 + Wait state select bit lower page + [3:2] + + true + + + + VAL_0x00 + No wait-states + 0 + + + VAL_0x01 + Wait one cycle during read/write strobe + 1 + + + VAL_0x02 + Wait two cycles during read/write strobe + 2 + + + VAL_0x03 + Wait two cycles during read/write and wait one cycle before driving out new address + 3 + + + + + SRL + Wait state page limit + [6:4] + + true + + + + VAL_0x00 + LS = N/A, US = 0x1100 - 0xFFFF + 0 + + + VAL_0x01 + LS = 0x1100 - 0x1FFF, US = 0x2000 - 0xFFFF + 1 + + + VAL_0x02 + LS = 0x1100 - 0x3FFF, US = 0x4000 - 0xFFFF + 2 + + + VAL_0x03 + LS = 0x1100 - 0x5FFF, US = 0x6000 - 0xFFFF + 3 + + + VAL_0x04 + LS = 0x1100 - 0x7FFF, US = 0x8000 - 0xFFFF + 4 + + + VAL_0x05 + LS = 0x1100 - 0x9FFF, US = 0xA000 - 0xFFFF + 5 + + + VAL_0x06 + LS = 0x1100 - 0xBFFF, US = 0xC000 - 0xFFFF + 6 + + + VAL_0x07 + LS = 0x1100 - 0xDFFF, US = 0xE000 - 0xFFFF + 7 + + + + + + + XMCRB + External Memory Control Register B + 0x18 + + + XMM + External Memory High Mask + [2:0] + + + 0 + 7 + + + + + XMBK + External Memory Bus Keeper Enable + [7:7] + + + + + + + EEPROM + EEPROM + 0x3C + + + EEAR + EEPROM Read/Write Access Bytes + 0x2 + 16 + + + 0 + 65535 + + + + + EECR + EEPROM Control Register + 0x0 + + + EERE + EEPROM Read Enable + [0:0] + + + EEWE + EEPROM Write Enable + [1:1] + + + EEMWE + EEPROM Master Write Enable + [2:2] + + + EERIE + EEPROM Ready Interrupt Enable + [3:3] + + + + + EEDR + EEPROM Data Register + 0x1 + + + 0 + 255 + + + + + + + EXINT + External Interrupts + 0x58 + + + EICRA + External Interrupt Control Register A + 0x12 + + + ISC0 + External Interrupt Sense Control Bit + [1:0] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC1 + External Interrupt Sense Control Bit + [3:2] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC2 + External Interrupt Sense Control Bit + [5:4] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC3 + External Interrupt Sense Control Bit + [7:6] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + + + EICRB + External Interrupt Control Register B + 0x2 + + + ISC4 + External Interrupt 7-4 Sense Control Bit + [1:0] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC5 + External Interrupt 7-4 Sense Control Bit + [3:2] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC6 + External Interrupt 7-4 Sense Control Bit + [5:4] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC7 + External Interrupt 7-4 Sense Control Bit + [7:6] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + + + EIFR + External Interrupt Flag Register + 0x0 + read-only + + + INTF + External Interrupt Flags + [7:0] + + + 0 + 255 + + + + + + + EIMSK + External Interrupt Mask Register + 0x1 + + + INT + External Interrupt Request 7 Enable + [7:0] + + + 0 + 255 + + + + + + + + + FUSE + Fuses + 0x0 + + + EXTENDED + <TBD> + 0x2 + + + WDTON + Watchdog Timer always on + [0:0] + + + M103C + ATmega103 Compatibility Mode + [1:1] + + + + + HIGH + <TBD> + 0x1 + + + BOOTRST + Boot Reset vector Enabled + [0:0] + + + BOOTSZ + Select Boot Size + [2:1] + + true + + + + 4096W_7000 + Boot Flash size=4096 words Boot address=$7000 + 0 + + + 2048W_7800 + Boot Flash size=2048 words Boot address=$7800 + 1 + + + 1024W_7C00 + Boot Flash size=1024 words Boot address=$7C00 + 2 + + + 512W_7E00 + Boot Flash size=512 words Boot address=$7E00 + 3 + + + + + EESAVE + Preserve EEPROM through the Chip Erase cycle + [3:3] + + + CKOPT + CKOPT fuse (operation dependent of CKSEL fuses) + [4:4] + + + SPIEN + Serial program downloading (SPI) enabled + [5:5] + + + JTAGEN + JTAG Interface Enabled + [6:6] + + + OCDEN + On-Chip Debug Enabled + [7:7] + + + + + LOW + <TBD> + 0x0 + + + SUT_CKSEL + Select Clock Source + [5:0] + + true + + + + EXTCLK_6CK_0MS + Ext. Clock; Start-up time: 6 CK + 0 ms + 0 + + + INTRCOSC_1MHZ_6CK_0MS + Int. RC Osc. 1 MHz; Start-up time: 6 CK + 0 ms + 1 + + + INTRCOSC_2MHZ_6CK_0MS + Int. RC Osc. 2 MHz; Start-up time: 6 CK + 0 ms + 2 + + + INTRCOSC_4MHZ_6CK_0MS + Int. RC Osc. 4 MHz; Start-up time: 6 CK + 0 ms + 3 + + + INTRCOSC_8MHZ_6CK_0MS + Int. RC Osc. 8 MHz; Start-up time: 6 CK + 0 ms + 4 + + + EXTRCOSC_XX_0MHZ9_18CK_0MS + Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 0 ms + 5 + + + EXTRCOSC_0MHZ9_3MHZ_18CK_0MS + Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 0 ms + 6 + + + EXTRCOSC_3MHZ_8MHZ_18CK_0MS + Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 0 ms + 7 + + + EXTRCOSC_8MHZ_12MHZ_18CK_0MS + Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 0 ms + 8 + + + EXTLOFXTAL_1KCK_4MS + Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4 ms + 9 + + + EXTLOFXTALRES_258CK_4MS + Ext. Crystal/Resonator Low Freq.; Start-up time: 258 CK + 4 ms + 10 + + + EXTLOFXTALRES_1KCK_64MS + Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 64 ms + 11 + + + EXTMEDFXTALRES_258CK_4MS + Ext. Crystal/Resonator Medium Freq.; Start-up time: 258 CK + 4 ms + 12 + + + EXTMEDFXTALRES_1KCK_64MS + Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 64 ms + 13 + + + EXTHIFXTALRES_258CK_4MS + Ext. Crystal/Resonator High Freq.; Start-up time: 258 CK + 4 ms + 14 + + + EXTHIFXTALRES_1KCK_64MS + Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 64 ms + 15 + + + EXTCLK_6CK_4MS + Ext. Clock; Start-up time: 6 CK + 4 ms + 16 + + + INTRCOSC_1MHZ_6CK_4MS + Int. RC Osc. 1 MHz; Start-up time: 6 CK + 4 ms + 17 + + + INTRCOSC_2MHZ_6CK_4MS + Int. RC Osc. 2 MHz; Start-up time: 6 CK + 4 ms + 18 + + + INTRCOSC_4MHZ_6CK_4MS + Int. RC Osc. 4 MHz; Start-up time: 6 CK + 4 ms + 19 + + + INTRCOSC_8MHZ_6CK_4MS + Int. RC Osc. 8 MHz; Start-up time: 6 CK + 4 ms + 20 + + + EXTRCOSC_XX_0MHZ9_18CK_4MS + Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 4 ms + 21 + + + EXTRCOSC_0MHZ9_3MHZ_18CK_4MS + Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 4 ms + 22 + + + EXTRCOSC_3MHZ_8MHZ_18CK_4MS + Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 4 ms + 23 + + + EXTRCOSC_8MHZ_12MHZ_18CK_4MS + Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 4 ms + 24 + + + EXTLOFXTAL_1KCK_64MS + Ext. Low-Freq. Crystal; Start-up time: 1K CK + 64 ms + 25 + + + EXTLOFXTALRES_258CK_64MS + Ext. Crystal/Resonator Low Freq.; Start-up time: 258 CK + 64 ms + 26 + + + EXTLOFXTALRES_16KCK_0MS + Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 0 ms + 27 + + + EXTMEDFXTALRES_258CK_64MS + Ext. Crystal/Resonator Medium Freq.; Start-up time: 258 CK + 64 ms + 28 + + + EXTMEDFXTALRES_16KCK_0MS + Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 0 ms + 29 + + + EXTHIFXTALRES_258CK_64MS + Ext. Crystal/Resonator High Freq.; Start-up time: 258 CK + 64 ms + 30 + + + EXTHIFXTALRES_16KCK_0MS + Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 0 ms + 31 + + + EXTCLK_6CK_64MS + Ext. Clock; Start-up time: 6 CK + 64 ms + 32 + + + INTRCOSC_1MHZ_6CK_64MS + Int. RC Osc. 1 MHz; Start-up time: 6 CK + 64 ms + 33 + + + INTRCOSC_2MHZ_6CK_64MS + Int. RC Osc. 2 MHz; Start-up time: 6 CK + 64 ms + 34 + + + INTRCOSC_4MHZ_6CK_64MS + Int. RC Osc. 4 MHz; Start-up time: 6 CK + 64 ms + 35 + + + INTRCOSC_8MHZ_6CK_64MS + Int. RC Osc. 8 MHz; Start-up time: 6 CK + 64 ms + 36 + + + EXTRCOSC_XX_0MHZ9_18CK_64MS + Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 64 ms + 37 + + + EXTRCOSC_0MHZ9_3MHZ_18CK_64MS + Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 64 ms + 38 + + + EXTRCOSC_3MHZ_8MHZ_18CK_64MS + Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 64 ms + 39 + + + EXTRCOSC_8MHZ_12MHZ_18CK_64MS + Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 64 ms + 40 + + + EXTLOFXTAL_32KCK_64MS + Ext. Low-Freq. Crystal; Start-up time: 32K CK + 64 ms + 41 + + + EXTLOFXTALRES_1KCK_0MS + Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 0 ms + 42 + + + EXTLOFXTALRES_16KCK_4MS + Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 4 ms + 43 + + + EXTMEDFXTALRES_1KCK_0MS + Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 0 ms + 44 + + + EXTMEDFXTALRES_16KCK_4MS + Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 4 ms + 45 + + + EXTHIFXTALRES_1KCK_0MS + Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 0 ms + 46 + + + EXTHIFXTALRES_16KCK_4MS + Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 4 ms + 47 + + + EXTRCOSC_XX_0MHZ9_6CK_4MS + Ext. RC Osc. - 0.9 MHz; Start-up time: 6 CK + 4 ms + 53 + + + EXTRCOSC_0MHZ9_3MHZ_6CK_4MS + Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 6 CK + 4 ms + 54 + + + EXTRCOSC_3MHZ_8MHZ_6CK_4MS + Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 6 CK + 4 ms + 55 + + + EXTRCOSC_8MHZ_12MHZ_6CK_4MS + Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 6 CK + 4 ms + 56 + + + EXTLOFXTALRES_1KCK_4MS + Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 4 ms + 58 + + + EXTLOFXTALRES_16KCK_64MS + Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 64 ms + 59 + + + EXTMEDFXTALRES_1KCK_4MS + Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 4 ms + 60 + + + EXTMEDFXTALRES_16KCK_64MS + Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 64 ms + 61 + + + EXTHIFXTALRES_1KCK_4MS + Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 4 ms + 62 + + + EXTHIFXTALRES_16KCK_64MS + Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 64 ms + 63 + + + + + BODEN + Brown-out detection enabled + [6:6] + + + BODLEVEL + Brownout detector trigger level + [7:7] + + true + + + + 4V0 + Brown-out detection at VCC=4.0 V + 0 + + + 2V7 + Brown-out detection at VCC=2.7 V + 1 + + + + + + + + + JTAG + JTAG Interface + 0x42 + + + MCUCSR + MCU Control And Status Register + 0x12 + + + JTRF + JTAG Reset Flag + [4:4] + + + JTD + JTAG Interface Disable + [7:7] + + + + + OCDR + On-Chip Debug Related Register in I/O Memory + 0x0 + + + OCDR + On-Chip Debug Register Bits + [7:0] + + + 0 + 255 + + + + + + + + + LOCKBIT + Lockbits + 0x0 + + + LOCKBIT + <TBD> + 0x0 + + + LB + Memory Lock + [1:0] + + true + + + + PROG_VER_DISABLED + Further programming and verification disabled + 0 + + + PROG_DISABLED + Further programming disabled + 2 + + + NO_LOCK + No memory lock features enabled + 3 + + + + + BLB0 + Boot Loader Protection Mode + [3:2] + + true + + + + LPM_SPM_DISABLE + LPM and SPM prohibited in Application Section + 0 + + + LPM_DISABLE + LPM prohibited in Application Section + 1 + + + SPM_DISABLE + SPM prohibited in Application Section + 2 + + + NO_LOCK + No lock on SPM and LPM in Application Section + 3 + + + + + BLB1 + Boot Loader Protection Mode + [5:4] + + true + + + + LPM_SPM_DISABLE + LPM and SPM prohibited in Boot Section + 0 + + + LPM_DISABLE + LPM prohibited in Boot Section + 1 + + + SPM_DISABLE + SPM prohibited in Boot Section + 2 + + + NO_LOCK + No lock on SPM and LPM in Boot Section + 3 + + + + + + + + + MISC + Other Registers + 0x40 + + + SFIOR + Special Function IO Register + 0x0 + + + PSR321 + Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1 + [0:0] + + + PSR0 + Prescaler Reset Timer/Counter0 + [1:1] + + + PUD + Pull Up Disable + [2:2] + + + ACME + Analog Comparator Multiplexer Enable + [3:3] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + + + PORTA + I/O Port + 0x39 + + + DDRA + Port A Data Direction Register + 0x1 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + PINA + Port A Input Pins + 0x0 + read-write + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + PORTA + Port A Data Register + 0x2 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + + + PORTB + I/O Port + 0x36 + + + DDRB + Port B Data Direction Register + 0x1 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PINB + Port B Input Pins + 0x0 + read-write + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PORTB + Port B Data Register + 0x2 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + + + PORTC + I/O Port + 0x33 + + + DDRC + Port C Data Direction Register + 0x1 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + PINC + Port C Input Pins + 0x0 + read-write + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + PORTC + Port C Data Register + 0x2 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + + + PORTD + I/O Port + 0x30 + + + DDRD + Port D Data Direction Register + 0x1 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PIND + Port D Input Pins + 0x0 + read-write + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PORTD + Port D Data Register + 0x2 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + + + PORTE + I/O Port + 0x21 + + + DDRE + Data Direction Register, Port E + 0x1 + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + PE4 + Pin E4 + [4:4] + + + PE5 + Pin E5 + [5:5] + + + PE6 + Pin E6 + [6:6] + + + PE7 + Pin E7 + [7:7] + + + + + PINE + Input Pins, Port E + 0x0 + read-write + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + PE4 + Pin E4 + [4:4] + + + PE5 + Pin E5 + [5:5] + + + PE6 + Pin E6 + [6:6] + + + PE7 + Pin E7 + [7:7] + + + + + PORTE + Data Register, Port E + 0x2 + + + PE0 + Pin E0 + [0:0] + + + PE1 + Pin E1 + [1:1] + + + PE2 + Pin E2 + [2:2] + + + PE3 + Pin E3 + [3:3] + + + PE4 + Pin E4 + [4:4] + + + PE5 + Pin E5 + [5:5] + + + PE6 + Pin E6 + [6:6] + + + PE7 + Pin E7 + [7:7] + + + + + + + PORTF + I/O Port + 0x20 + + + DDRF + Data Direction Register, Port F + 0x41 + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF2 + Pin F2 + [2:2] + + + PF3 + Pin F3 + [3:3] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + PF7 + Pin F7 + [7:7] + + + + + PINF + Input Pins, Port F + 0x0 + read-write + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF2 + Pin F2 + [2:2] + + + PF3 + Pin F3 + [3:3] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + PF7 + Pin F7 + [7:7] + + + + + PORTF + Data Register, Port F + 0x42 + + + PF0 + Pin F0 + [0:0] + + + PF1 + Pin F1 + [1:1] + + + PF2 + Pin F2 + [2:2] + + + PF3 + Pin F3 + [3:3] + + + PF4 + Pin F4 + [4:4] + + + PF5 + Pin F5 + [5:5] + + + PF6 + Pin F6 + [6:6] + + + PF7 + Pin F7 + [7:7] + + + + + + + PORTG + I/O Port + 0x63 + + + DDRG + Data Direction Register, Port G + 0x1 + + + PG0 + Pin G0 + [0:0] + + + PG1 + Pin G1 + [1:1] + + + PG2 + Pin G2 + [2:2] + + + PG3 + Pin G3 + [3:3] + + + PG4 + Pin G4 + [4:4] + + + + + PING + Input Pins, Port G + 0x0 + read-write + + + PG0 + Pin G0 + [0:0] + + + PG1 + Pin G1 + [1:1] + + + PG2 + Pin G2 + [2:2] + + + PG3 + Pin G3 + [3:3] + + + PG4 + Pin G4 + [4:4] + + + + + PORTG + Data Register, Port G + 0x2 + + + PG0 + Pin G0 + [0:0] + + + PG1 + Pin G1 + [1:1] + + + PG2 + Pin G2 + [2:2] + + + PG3 + Pin G3 + [3:3] + + + PG4 + Pin G4 + [4:4] + + + + + + + SPI + Serial Peripheral Interface + 0x2D + + + SPCR + SPI Control Register + 0x0 + + + SPR + SPI Clock Rate Selects + [1:0] + + true + + SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 + + + CPHA + Clock Phase + [2:2] + + + CPOL + Clock polarity + [3:3] + + + MSTR + Master/Slave Select + [4:4] + + + DORD + Data Order + [5:5] + + + SPE + SPI Enable + [6:6] + + + SPIE + SPI Interrupt Enable + [7:7] + + + + + SPDR + SPI Data Register + 0x2 + + + 0 + 255 + + + + + SPSR + SPI Status Register + 0x1 + read-write + + + SPI2X + Double SPI Speed Bit + [0:0] + read-write + + WCOL + Write Collision Flag + [6:6] + read-only + + SPIF + SPI Interrupt Flag + [7:7] + read-only + + + + + + TC0 + Timer/Counter, 8-bit Async + 0x40 + + + ASSR + Asynchronus Status Register + 0x10 + + + TCR0UB + Timer/Counter Control Register 0 Update Busy + [0:0] + + + OCR0UB + Output Compare register 0 Busy + [1:1] + + + TCN0UB + Timer/Counter0 Update Busy + [2:2] + + + AS0 + Asynchronus Timer/Counter 0 + [3:3] + + + + + OCR0 + Output Compare Register + 0x11 + + + 0 + 255 + + + + + SFIOR + Special Function IO Register + 0x0 + + + PSR0 + Prescaler Reset Timer/Counter0 + [1:1] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + TCCR0 + Timer/Counter Control Register + 0x13 + + + CS0 + Clock Selects + [2:0] + + true + + + + VAL_0x00 + No Clock Source (Stopped) + 0 + + + VAL_0x01 + Running, No Prescaling + 1 + + + VAL_0x02 + Running, CLK/8 + 2 + + + VAL_0x03 + Running, CLK/32 + 3 + + + VAL_0x04 + Running, CLK/64 + 4 + + + VAL_0x05 + Running, CLK/128 + 5 + + + VAL_0x06 + Running, CLK/256 + 6 + + + VAL_0x07 + Running, CLK/1024 + 7 + + + + + WGM01 + Waveform Generation Mode 1 + [3:3] + + + COM0 + Compare Match Output Modes + [5:4] + + + 0 + 3 + + + + + WGM00 + Waveform Generation Mode 0 + [6:6] + + true + + + + VAL_0x00 + Normal + 0 + + + VAL_0x01 + CTC + 1 + + + + + FOC0 + Force Output Compare + [7:7] + + + + + TCNT0 + Timer/Counter Register + 0x12 + + + 0 + 255 + + + + + TIFR + Timer/Counter Interrupt Flag register + 0x16 + read-only + + + TOV0 + Timer/Counter0 Overflow Flag + [0:0] + + + OCF0 + Output Compare Flag 0 + [1:1] + + + + + TIMSK + Timer/Counter Interrupt Mask Register + 0x17 + + + TOIE0 + Timer/Counter0 Overflow Interrupt Enable + [0:0] + + + OCIE0 + Timer/Counter0 Output Compare Match Interrupt register + [1:1] + + + + + + + TC1 + Timer/Counter, 16-bit + 0x40 + + + ETIFR + Extended Timer/Counter Interrupt Flag register + 0x3C + read-only + + + OCF1C + Timer/Counter 1, Output Compare C Match Flag + [0:0] + + + + + ETIMSK + Extended Timer/Counter Interrupt Mask Register + 0x3D + + + OCIE1C + Timer/Counter 1, Output Compare Match C Interrupt Enable + [0:0] + + + + + ICR1 + Timer/Counter1 Input Capture Register Bytes + 0x6 + 16 + + + 0 + 65535 + + + + + OCR1A + Timer/Counter1 Output Compare Register Bytes + 0xA + 16 + + + 0 + 65535 + + + + + OCR1B + Timer/Counter1 Output Compare Register Bytes + 0x8 + 16 + + + 0 + 65535 + + + + + OCR1C + Timer/Counter1 Output Compare Register Bytes + 0x38 + 16 + + + 0 + 65535 + + + + + SFIOR + Special Function IO Register + 0x0 + + + PSR321 + Prescaler Reset, T/C3, T/C2, T/C1 + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + TCCR1A + Timer/Counter1 Control Register A + 0xF + + + WGM1 + Waveform Generation Mode Bits + [1:0] + + + 0 + 3 + + + + + COM1C + Compare Output Mode 1C, bits + [3:2] + + + 0 + 3 + + + + + COM1B + Compare Output Mode 1B, bits + [5:4] + + + 0 + 3 + + + + + COM1A + Compare Output Mode 1A, bits + [7:6] + + + 0 + 3 + + + + + + + TCCR1B + Timer/Counter1 Control Register B + 0xE + + + CS1 + Clock Select1 bits + [2:0] + + true + + + + VAL_0x00 + No Clock Source (Stopped) + 0 + + + VAL_0x01 + Running, No Prescaling + 1 + + + VAL_0x02 + Running, CLK/8 + 2 + + + VAL_0x03 + Running, CLK/64 + 3 + + + VAL_0x04 + Running, CLK/256 + 4 + + + VAL_0x05 + Running, CLK/1024 + 5 + + + VAL_0x06 + Running, ExtClk Tx Falling Edge + 6 + + + VAL_0x07 + Running, ExtClk Tx Rising Edge + 7 + + + + + WGM1 + Waveform Generation Mode + [4:3] + + + 0 + 3 + + + + + ICES1 + Input Capture 1 Edge Select + [6:6] + + + ICNC1 + Input Capture 1 Noise Canceler + [7:7] + + + + + TCCR1C + Timer/Counter1 Control Register C + 0x3A + + + FOC1C + Force Output Compare for channel C + [5:5] + + + FOC1B + Force Output Compare for channel B + [6:6] + + + FOC1A + Force Output Compare for channel A + [7:7] + + + + + TCNT1 + Timer/Counter1 Bytes + 0xC + 16 + + + 0 + 65535 + + + + + TIFR + Timer/Counter Interrupt Flag register + 0x16 + read-only + + + TOV1 + Timer/Counter1 Overflow Flag + [2:2] + + + OCF1B + Output Compare Flag 1B + [3:3] + + + OCF1A + Output Compare Flag 1A + [4:4] + + + ICF1 + Input Capture Flag 1 + [5:5] + + + + + TIMSK + Timer/Counter Interrupt Mask Register + 0x17 + + + TOIE1 + Timer/Counter1 Overflow Interrupt Enable + [2:2] + + + OCIE1B + Timer/Counter1 Output CompareB Match Interrupt Enable + [3:3] + + + OCIE1A + Timer/Counter1 Output CompareA Match Interrupt Enable + [4:4] + + + TICIE1 + Timer/Counter1 Input Capture Interrupt Enable + [5:5] + + + + + + + TC2 + Timer/Counter, 8-bit + 0x43 + + + OCR2 + Output Compare Register + 0x0 + + + 0 + 255 + + + + + TCCR2 + Timer/Counter Control Register + 0x2 + + + CS2 + Clock Select + [2:0] + + true + + + + VAL_0x00 + No Clock Source (Stopped) + 0 + + + VAL_0x01 + Running, No Prescaling + 1 + + + VAL_0x02 + Running, CLK/8 + 2 + + + VAL_0x03 + Running, CLK/64 + 3 + + + VAL_0x04 + Running, CLK/256 + 4 + + + VAL_0x05 + Running, CLK/1024 + 5 + + + VAL_0x06 + Running, ExtClk Tx Falling Edge + 6 + + + VAL_0x07 + Running, ExtClk Tx Rising Edge + 7 + + + + + WGM21 + Waveform Generation Mode + [3:3] + + + COM2 + Compare Match Output Mode + [5:4] + + + 0 + 3 + + + + + WGM20 + Wafeform Generation Mode + [6:6] + + true + + + + VAL_0x00 + Normal + 0 + + + VAL_0x01 + CTC + 1 + + + + + FOC2 + Force Output Compare + [7:7] + + + + + TCNT2 + Timer/Counter Register + 0x1 + + + 0 + 255 + + + + + TIFR + Timer/Counter Interrupt Flag Register + 0x13 + read-only + + + TOV2 + Timer/Counter2 Overflow Flag + [6:6] + + + OCF2 + Output Compare Flag 2 + [7:7] + + + + + TIMSK + <TBD> + 0x14 + + + TOIE2 + <TBD> + [6:6] + + + OCIE2 + <TBD> + [7:7] + + + + + + + TC3 + Timer/Counter, 16-bit + 0x40 + + + ETIFR + Extended Timer/Counter Interrupt Flag register + 0x3C + read-only + + + OCF3C + Timer/Counter3 Output Compare C Match Flag + [1:1] + + + TOV3 + Timer/Counter3 Overflow Flag + [2:2] + + + OCF3B + Output Compare Flag 3B + [3:3] + + + OCF3A + Output Compare Flag 3A + [4:4] + + + ICF3 + Input Capture Flag 3 + [5:5] + + + + + ETIMSK + Extended Timer/Counter Interrupt Mask Register + 0x3D + + + OCIE3C + Timer/Counter3, Output Compare Match Interrupt Enable + [1:1] + + + TOIE3 + Timer/Counter3 Overflow Interrupt Enable + [2:2] + + + OCIE3B + Timer/Counter3 Output CompareB Match Interrupt Enable + [3:3] + + + OCIE3A + Timer/Counter3 Output CompareA Match Interrupt Enable + [4:4] + + + TICIE3 + Timer/Counter3 Input Capture Interrupt Enable + [5:5] + + + + + ICR3 + Timer/Counter3 Input Capture Register Bytes + 0x40 + 16 + + + 0 + 65535 + + + + + OCR3A + Timer/Counter3 Output Compare Register A Bytes + 0x46 + 16 + + + 0 + 65535 + + + + + OCR3B + Timer/Counter3 Output Compare Register B Bytes + 0x44 + 16 + + + 0 + 65535 + + + + + OCR3C + Timer/Counter3 Output compare Register C Bytes + 0x42 + 16 + + + 0 + 65535 + + + + + SFIOR + Special Function IO Register + 0x0 + + + PSR321 + Prescaler Reset, T/C3, T/C2, T/C1 + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + TCCR3A + Timer/Counter3 Control Register A + 0x4B + + + WGM3 + Waveform Generation Mode Bits + [1:0] + + + 0 + 3 + + + + + COM3C + Compare Output Mode 3C, bits + [3:2] + + + 0 + 3 + + + + + COM3B + Compare Output Mode 3B, bits + [5:4] + + + 0 + 3 + + + + + COM3A + Compare Output Mode 3A, bits + [7:6] + + + 0 + 3 + + + + + + + TCCR3B + Timer/Counter3 Control Register B + 0x4A + + + CS3 + Clock Select3 bits + [2:0] + + true + + + + VAL_0x00 + No Clock Source (Stopped) + 0 + + + VAL_0x01 + Running, No Prescaling + 1 + + + VAL_0x02 + Running, CLK/8 + 2 + + + VAL_0x03 + Running, CLK/64 + 3 + + + VAL_0x04 + Running, CLK/256 + 4 + + + VAL_0x05 + Running, CLK/1024 + 5 + + + VAL_0x06 + Running, ExtClk Tx Falling Edge + 6 + + + VAL_0x07 + Running, ExtClk Tx Rising Edge + 7 + + + + + WGM3 + Waveform Generation Mode + [4:3] + + + 0 + 3 + + + + + ICES3 + Input Capture 3 Edge Select + [6:6] + + + ICNC3 + Input Capture 3 Noise Canceler + [7:7] + + + + + TCCR3C + Timer/Counter3 Control Register C + 0x4C + + + FOC3C + Force Output Compare for channel C + [5:5] + + + FOC3B + Force Output Compare for channel B + [6:6] + + + FOC3A + Force Output Compare for channel A + [7:7] + + + + + TCNT3 + Timer/Counter3 Bytes + 0x48 + 16 + + + 0 + 65535 + + + + + + + TWI + Two Wire Serial Interface + 0x70 + + + TWAR + TWI (Slave) Address register + 0x2 + + + TWGCE + TWI General Call Recognition Enable Bit + [0:0] + + + TWA + TWI (Slave) Address register Bits + [7:1] + + + 0 + 127 + + + + + + + TWBR + TWI Bit Rate register + 0x0 + + + 0 + 255 + + + + + TWCR + TWI Control Register + 0x4 + read-only + + + TWIE + TWI Interrupt Enable + [0:0] + + + TWEN + TWI Enable Bit + [2:2] + + + TWWC + TWI Write Collition Flag + [3:3] + + + TWSTO + TWI Stop Condition Bit + [4:4] + + + TWSTA + TWI Start Condition Bit + [5:5] + + + TWEA + TWI Enable Acknowledge Bit + [6:6] + + + TWINT + TWI Interrupt Flag + [7:7] + + + + + TWDR + TWI Data register + 0x3 + + + 0 + 255 + + + + + TWSR + TWI Status Register + 0x1 + + + TWPS + TWI Prescaler + [1:0] + + true + + + + VAL_0x00 + 1 + 0 + + + VAL_0x01 + 4 + 1 + + + VAL_0x02 + 16 + 2 + + + VAL_0x03 + 64 + 3 + + + + + TWS + TWI Status + [7:3] + + + 0 + 31 + + + + + + + + + USART0 + USART + 0x29 + + + UBRR0H + USART Baud Rate Register Hight Byte + 0x67 + + + 0 + 255 + + + + + UBRR0L + USART Baud Rate Register Low Byte + 0x0 + + + 0 + 255 + + + + + UCSR0A + USART Control and Status Register A + 0x2 + read-write + + + MPCM0 + Multi-processor Communication Mode + [0:0] + + + U2X0 + Double the USART transmission speed + [1:1] + + + UPE0 + Parity Error + [2:2] + read-only + + DOR0 + Data overRun + [3:3] + read-only + + FE0 + Framing Error + [4:4] + read-only + + UDRE0 + USART Data Register Empty + [5:5] + read-only + + TXC0 + USART Transmit Complete + [6:6] + + + RXC0 + USART Receive Complete + [7:7] + read-only + + + + UCSR0B + USART Control and Status Register B + 0x1 + + + TXB80 + Transmit Data Bit 8 + [0:0] + + + RXB80 + Receive Data Bit 8 + [1:1] + read-only + + UCSZ02 + Character Size + [2:2] + + + TXEN0 + Transmitter Enable + [3:3] + + + RXEN0 + Receiver Enable + [4:4] + + + UDRIE0 + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE0 + TX Complete Interrupt Enable + [6:6] + + + RXCIE0 + RX Complete Interrupt Enable + [7:7] + + + + + UCSR0C + USART Control and Status Register C + 0x6C + + + UCPOL0 + Clock Polarity + [0:0] + UCPOL0read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 + + + UCSZ0 + Character Size + [2:1] + + + 0 + 3 + + + UCSZ0read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 + + + USBS0 + Stop Bit Select + [3:3] + + true + + USBS0read-writeSTOP11-bit0STOP22-bit1 + + + UPM0 + Parity Mode Bits + [5:4] + + true + + UPM0read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 + + + UMSEL0 + USART Mode Select + [7:6] + + true + + UMSEL0read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 + + + + + UDR0 + USART I/O Data Register + 0x3 + + + 0 + 255 + + + + + + + USART1 + USART + 0x98 + + + UBRR1H + USART Baud Rate Register Hight Byte + 0x0 + + + 0 + 255 + + + + + UBRR1L + USART Baud Rate Register Low Byte + 0x1 + + + 0 + 255 + + + + + UCSR1A + USART Control and Status Register A + 0x3 + read-write + + + MPCM1 + Multi-processor Communication Mode + [0:0] + + + U2X1 + Double the USART transmission speed + [1:1] + + + UPE1 + Parity Error + [2:2] + read-only + + DOR1 + Data overRun + [3:3] + read-only + + FE1 + Framing Error + [4:4] + read-only + + UDRE1 + USART Data Register Empty + [5:5] + read-only + + TXC1 + USART Transmit Complete + [6:6] + + + RXC1 + USART Receive Complete + [7:7] + read-only + + + + UCSR1B + USART Control and Status Register B + 0x2 + + + TXB81 + Transmit Data Bit 8 + [0:0] + + + RXB81 + Receive Data Bit 8 + [1:1] + read-only + + UCSZ12 + Character Size + [2:2] + + + TXEN1 + Transmitter Enable + [3:3] + + + RXEN1 + Receiver Enable + [4:4] + + + UDRIE1 + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE1 + TX Complete Interrupt Enable + [6:6] + + + RXCIE1 + RX Complete Interrupt Enable + [7:7] + + + + + UCSR1C + USART Control and Status Register C + 0x5 + + + UCPOL1 + Clock Polarity + [0:0] + UCPOL1read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 + + + UCSZ1 + Character Size + [2:1] + + + 0 + 3 + + + UCSZ1read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 + + + USBS1 + Stop Bit Select + [3:3] + + true + + USBS1read-writeSTOP11-bit0STOP22-bit1 + + + UPM1 + Parity Mode Bits + [5:4] + + true + + UPM1read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 + + + UMSEL1 + USART Mode Select + [7:6] + + true + + UMSEL1read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 + + + + + UDR1 + USART I/O Data Register + 0x4 + + + 0 + 255 + + + + + + + WDT + Watchdog Timer + 0x41 + + + WDTCR + Watchdog Timer Control Register + 0x0 + + + WDP + Watch Dog Timer Prescaler bits + [2:0] + + true + + + + VAL_0x00 + Oscillator Cycles 16K + 0 + + + VAL_0x01 + Oscillator Cycles 32K + 1 + + + VAL_0x02 + Oscillator Cycles 64K + 2 + + + VAL_0x03 + Oscillator Cycles 128K + 3 + + + VAL_0x04 + Oscillator Cycles 256K + 4 + + + VAL_0x05 + Oscillator Cycles 512K + 5 + + + VAL_0x06 + Oscillator Cycles 1024K + 6 + + + VAL_0x07 + Oscillator Cycles 2048K + 7 + + + + + WDE + Watch Dog Enable + [3:3] + + + WDCE + Watchdog Change Enable + [4:4] + + + + + + + \ No newline at end of file diff --git a/misc/svd/atmega644.svd b/misc/svd/atmega644.svd new file mode 100644 index 0000000..59a7402 --- /dev/null +++ b/misc/svd/atmega644.svd @@ -0,0 +1,3479 @@ + + Atmel + ATmega644 + 8 + 8 + read-write + 0 + 0xff + + + AC + Analog Comparator + 0x50 + + + ACSR + Analog Comparator Control And Status Register + 0x0 + read-write + + + ACIS + Analog Comparator Interrupt Mode Select + [1:0] + + true + + ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 + + + ACIC + Analog Comparator Input Capture Enable + [2:2] + + + ACIE + Analog Comparator Interrupt Enable + [3:3] + + + ACI + Analog Comparator Interrupt Flag + [4:4] + + + ACO + Analog Compare Output + [5:5] + read-only + + ACBG + Analog Comparator Bandgap Select + [6:6] + + + ACD + Analog Comparator Disable + [7:7] + + + + + ADCSRB + ADC Control and Status Register B + 0x2B + + + ACME + Analog Comparator Multiplexer Enable + [6:6] + + + + + DIDR1 + Digital Input Disable Register 1 + 0x2F + + + AIN0D + AIN0 Digital Input Disable + [0:0] + + + AIN1D + AIN1 Digital Input Disable + [1:1] + + + + + + + ADC + Analog-to-Digital Converter + 0x78 + + + ADC + ADC Data Register Bytes + 0x0 + 16 + + + 0 + 65535 + + + + + ADCSRA + The ADC Control and Status register A + 0x2 + read-write + + + ADPS + ADC Prescaler Select Bits + [2:0] + + true + + ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 + + + ADIE + ADC Interrupt Enable + [3:3] + + + ADIF + ADC Interrupt Flag + [4:4] + + + ADATE + ADC Auto Trigger Enable + [5:5] + + + ADSC + ADC Start Conversion + [6:6] + + + ADEN + ADC Enable + [7:7] + + + + + ADCSRB + The ADC Control and Status register B + 0x3 + + + ADTS + ADC Auto Trigger Source bits + [2:0] + + true + + + + VAL_0x00 + Free Running mode + 0 + + + VAL_0x01 + Analog Comparator + 1 + + + VAL_0x02 + External Interrupt Request 0 + 2 + + + VAL_0x03 + Timer/Counter0 Compare Match A + 3 + + + VAL_0x04 + Timer/Counter0 Overflow + 4 + + + VAL_0x05 + Timer/Counter1 Compare Match B + 5 + + + VAL_0x06 + Timer/Counter1 Overflow + 6 + + + VAL_0x07 + Timer/Counter1 Capture Event + 7 + + + + + ACME + <TBD> + [6:6] + + + + + ADMUX + The ADC multiplexer Selection Register + 0x4 + + + MUX + Analog Channel and Gain Selection Bits + [4:0] + + true + + + + ADC0 + ADC Single Ended Input pin 0 + 0 + + + ADC1 + ADC Single Ended Input pin 1 + 1 + + + ADC2 + ADC Single Ended Input pin 2 + 2 + + + ADC3 + ADC Single Ended Input pin 3 + 3 + + + ADC4 + ADC Single Ended Input pin 4 + 4 + + + ADC5 + ADC Single Ended Input pin 5 + 5 + + + ADC6 + ADC Single Ended Input pin 6 + 6 + + + ADC7 + ADC Single Ended Input pin 7 + 7 + + + ADC0_ADC0_10X + ADC Differential Inputs Postive pin 0 Negative pin 0 10x Gain + 8 + + + ADC1_ADC0_10X + ADC Differential Inputs Postive pin 1 Negative pin 0 10x Gain + 9 + + + ADC0_ADC0_200x + ADC Differential Inputs Postive pin 0 Negative pin 0 200x Gain + 10 + + + ADC1_ADC0_200X + ADC Differential Inputs Postive pin 1 Negative pin 0 200x Gain + 11 + + + ADC2_ADC2_10X + ADC Differential Inputs Postive pin 2 Negative pin 2 10x Gain + 12 + + + ADC3_ADC2_10X + ADC Differential Inputs Postive pin 3 Negative pin 2 10x Gain + 13 + + + ADC2_ADC2_200X + ADC Differential Inputs Postive pin 2 Negative pin 2 200x Gain + 14 + + + ADC3_ADC2_200X + ADC Differential Inputs Postive pin 3 Negative pin 2 200x Gain + 15 + + + ADC0_ADC1_1X + ADC Differential Inputs Postive pin 0 Negative pin 1 1x Gain + 16 + + + ADC1_ADC1_1X + ADC Differential Inputs Postive pin 1 Negative pin 1 1x Gain + 17 + + + ADC2_ADC1_1X + ADC Differential Inputs Postive pin 2 Negative pin 1 1x Gain + 18 + + + ADC3_ADC1_1X + ADC Differential Inputs Postive pin 3 Negative pin 1 1x Gain + 19 + + + ADC4_ADC1_1X + ADC Differential Inputs Postive pin 4 Negative pin 1 1x Gain + 20 + + + ADC5_ADC1_1X + ADC Differential Inputs Postive pin 5 Negative pin 1 1x Gain + 21 + + + ADC6_ADC1_1X + ADC Differential Inputs Postive pin 6 Negative pin 1 1x Gain + 22 + + + ADC7_ADC1_1X + ADC Differential Inputs Postive pin 7 Negative pin 1 1x Gain + 23 + + + ADC0_ADC2_1X + ADC Differential Inputs Postive pin 0 Negative pin 2 1x Gain + 24 + + + ADC1_ADC2_1X + ADC Differential Inputs Postive pin 1 Negative pin 2 1x Gain + 25 + + + ADC2_ADC2_1X + ADC Differential Inputs Postive pin 2 Negative pin 2 1x Gain + 26 + + + ADC3_ADC2_1X + ADC Differential Inputs Postive pin 3 Negative pin 2 1x Gain + 27 + + + ADC4_ADC2_1X + ADC Differential Inputs Postive pin 4 Negative pin 2 1x Gain + 28 + + + ADC5_ADC2_1X + ADC Differential Inputs Postive pin 5 Negative pin 2 1x Gain + 29 + + + ADC_VBG + Internal Reference (VBG) + 30 + + + ADC_GND + 0V (GND) + 31 + + + + + ADLAR + Left Adjust Result + [5:5] + + + REFS + Reference Selection Bits + [7:6] + + true + + REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 + + + + + DIDR0 + Digital Input Disable Register + 0x6 + + + ADC0D + <TBD> + [0:0] + + + ADC1D + <TBD> + [1:1] + + + ADC2D + <TBD> + [2:2] + + + ADC3D + <TBD> + [3:3] + + + ADC4D + <TBD> + [4:4] + + + ADC5D + <TBD> + [5:5] + + + ADC6D + <TBD> + [6:6] + + + ADC7D + <TBD> + [7:7] + + + + + + + BOOT_LOAD + Bootloader + 0x57 + + + SPMCSR + Store Program Memory Control Register + 0x0 + + + SPMEN + Store Program Memory Enable + [0:0] + + + PGERS + Page Erase + [1:1] + + + PGWRT + Page Write + [2:2] + + + BLBSET + Boot Lock Bit Set + [3:3] + + + RWWSRE + Read While Write section read enable + [4:4] + + + SIGRD + Signature Row Read + [5:5] + + + RWWSB + Read While Write Section Busy + [6:6] + + + SPMIE + SPM Interrupt Enable + [7:7] + + + + + + + CPU + CPU Registers + 0x3E + + RESET + External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + 0 + + + INT0 + External Interrupt Request 0 + 1 + + + INT1 + External Interrupt Request 1 + 2 + + + INT2 + External Interrupt Request 2 + 3 + + + PCINT0 + Pin Change Interrupt Request 0 + 4 + + + PCINT1 + Pin Change Interrupt Request 1 + 5 + + + PCINT2 + Pin Change Interrupt Request 2 + 6 + + + PCINT3 + Pin Change Interrupt Request 3 + 7 + + + WDT + Watchdog Time-out Interrupt + 8 + + + TIMER2_COMPA + Timer/Counter2 Compare Match A + 9 + + + TIMER2_COMPB + Timer/Counter2 Compare Match B + 10 + + + TIMER2_OVF + Timer/Counter2 Overflow + 11 + + + TIMER1_CAPT + Timer/Counter1 Capture Event + 12 + + + TIMER1_COMPA + Timer/Counter1 Compare Match A + 13 + + + TIMER1_COMPB + Timer/Counter1 Compare Match B + 14 + + + TIMER1_OVF + Timer/Counter1 Overflow + 15 + + + TIMER0_COMPA + Timer/Counter0 Compare Match A + 16 + + + TIMER0_COMPB + Timer/Counter0 Compare Match B + 17 + + + TIMER0_OVF + Timer/Counter0 Overflow + 18 + + + SPI_STC + SPI Serial Transfer Complete + 19 + + + USART0_RX + USART0, Rx Complete + 20 + + + USART0_UDRE + USART0 Data register Empty + 21 + + + USART0_TX + USART0, Tx Complete + 22 + + + ANALOG_COMP + Analog Comparator + 23 + + + ADC + ADC Conversion Complete + 24 + + + EE_READY + EEPROM Ready + 25 + + + TWI + 2-wire Serial Interface + 26 + + + SPM_READY + Store Program Memory Read + 27 + + + + CLKPR + <TBD> + 0x23 + + + CLKPS + <TBD> + [3:0] + + true + + + + VAL_0x00 + 1 + 0 + + + VAL_0x01 + 2 + 1 + + + VAL_0x02 + 4 + 2 + + + VAL_0x03 + 8 + 3 + + + VAL_0x04 + 16 + 4 + + + VAL_0x05 + 32 + 5 + + + VAL_0x06 + 64 + 6 + + + VAL_0x07 + 128 + 7 + + + VAL_0x08 + 256 + 8 + + + + + CLKPCE + <TBD> + [7:7] + + + + + GPIOR0 + General Purpose IO Register 0 + 0x0 + + + GPIOR00 + General Purpose IO Register 0 bit 0 + [0:0] + + + GPIOR01 + General Purpose IO Register 0 bit 1 + [1:1] + + + GPIOR02 + General Purpose IO Register 0 bit 2 + [2:2] + + + GPIOR03 + General Purpose IO Register 0 bit 3 + [3:3] + + + GPIOR04 + General Purpose IO Register 0 bit 4 + [4:4] + + + GPIOR05 + General Purpose IO Register 0 bit 5 + [5:5] + + + GPIOR06 + General Purpose IO Register 0 bit 6 + [6:6] + + + GPIOR07 + General Purpose IO Register 0 bit 7 + [7:7] + + + + + GPIOR1 + General Purpose IO Register 1 + 0xC + + + GPIOR + General Purpose IO Register 1 bis + [7:0] + + + 0 + 255 + + + + + + + GPIOR2 + General Purpose IO Register 2 + 0xD + + + GPIOR + General Purpose IO Register 2 bis + [7:0] + + + 0 + 255 + + + + + + + MCUCR + MCU Control Register + 0x17 + + + IVCE + Interrupt Vector Change Enable + [0:0] + + + IVSEL + Interrupt Vector Select + [1:1] + + + PUD + Pull-up disable + [4:4] + + + JTD + JTAG Interface Disable + [7:7] + + + + + MCUSR + MCU Status Register + 0x16 + + + PORF + Power-on reset flag + [0:0] + + + EXTRF + External Reset Flag + [1:1] + + + BORF + Brown-out Reset Flag + [2:2] + + + WDRF + Watchdog Reset Flag + [3:3] + + + JTRF + JTAG Reset Flag + [4:4] + + + + + OSCCAL + Oscillator Calibration Value + 0x28 + + + OSCCAL + Oscillator Calibration + [7:0] + + + 0 + 255 + + + + + + + PRR + Power Reduction Register + 0x26 + + + PRADC + Power Reduction ADC + [0:0] + + + PRUSART0 + Power Reduction USART + [1:1] + + + PRSPI + Power Reduction Serial Peripheral Interface + [2:2] + + + PRTIM1 + Power Reduction Timer/Counter1 + [3:3] + + + PRTIM0 + Power Reduction Timer/Counter0 + [5:5] + + + PRTIM2 + Power Reduction Timer/Counter2 + [6:6] + + + PRTWI + Power Reduction TWI + [7:7] + + + + + SMCR + Sleep Mode Control Register + 0x15 + + + SE + Sleep Enable + [0:0] + + + SM + Sleep Mode Select bits + [3:1] + + true + + + + IDLE + Idle + 0 + + + ADC + ADC Noise Reduction (If Available) + 1 + + + PDOWN + Power Down + 2 + + + PSAVE + Power Save + 3 + + + VAL_0x04 + Reserved + 4 + + + VAL_0x05 + Reserved + 5 + + + STDBY + Standby + 6 + + + ESTDBY + Extended Standby + 7 + + + + + + + + + EEPROM + EEPROM + 0x3F + + + EEAR + EEPROM Address Register Low Bytes + 0x2 + 16 + + + 0 + 65535 + + + + + EECR + EEPROM Control Register + 0x0 + + + EERE + EEPROM Read Enable + [0:0] + + + EEPE + EEPROM Write Enable + [1:1] + + + EEMPE + EEPROM Master Write Enable + [2:2] + + + EERIE + EEPROM Ready Interrupt Enable + [3:3] + + + EEPM + EEPROM Programming Mode Bits + [5:4] + + true + + + + VAL_0x00 + Erase and Write in one operation + 0 + + + VAL_0x01 + Erase Only + 1 + + + VAL_0x02 + Write Only + 2 + + + + + + + EEDR + EEPROM Data Register + 0x1 + + + 0 + 255 + + + + + + + EXINT + External Interrupts + 0x3B + + + EICRA + External Interrupt Control Register A + 0x2E + + + ISC0 + External Interrupt Sense Control Bit + [1:0] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC1 + External Interrupt Sense Control Bit + [3:2] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC2 + External Interrupt Sense Control Bit + [5:4] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + + + EIFR + External Interrupt Flag Register + 0x1 + read-only + + + INTF + External Interrupt Flags + [2:0] + + + 0 + 7 + + + + + + + EIMSK + External Interrupt Mask Register + 0x2 + + + INT + External Interrupt Request 2 Enable + [2:0] + + + 0 + 7 + + + + + + + PCICR + Pin Change Interrupt Control Register + 0x2D + + + PCIE + Pin Change Interrupt Enables + [3:0] + + + 0 + 15 + + + + + + + PCIFR + Pin Change Interrupt Flag Register + 0x0 + read-only + + + PCIF + Pin Change Interrupt Flags + [3:0] + + + 0 + 15 + + + + + + + PCMSK0 + Pin Change Mask Register 0 + 0x30 + + + PCINT + Pin Change Enable Masks + [7:0] + + + 0 + 255 + + + + + + + PCMSK1 + Pin Change Mask Register 1 + 0x31 + + + PCINT + Pin Change Enable Masks + [7:0] + + + 0 + 255 + + + + + + + PCMSK2 + Pin Change Mask Register 2 + 0x32 + + + PCINT + Pin Change Enable Masks + [7:0] + + + 0 + 255 + + + + + + + PCMSK3 + Pin Change Mask Register 3 + 0x38 + + + PCINT + Pin Change Enable Masks + [7:0] + + + 0 + 255 + + + + + + + + + FUSE + Fuses + 0x0 + + + EXTENDED + <TBD> + 0x2 + + + BODLEVEL + Brown-out Detector trigger level + [2:0] + + true + + + + 4V3 + Brown-out detection at VCC=4.3 V + 4 + + + 2V7 + Brown-out detection at VCC=2.7 V + 5 + + + 1V8 + Brown-out detection at VCC=1.8 V + 6 + + + DISABLED + Brown-out detection disabled; [BODLEVEL=111] + 7 + + + + + + + HIGH + <TBD> + 0x1 + + + BOOTRST + Boot Reset vector Enabled + [0:0] + + + BOOTSZ + Select Boot Size + [2:1] + + true + + + + 4096W_7000 + Boot Flash size=4096 words Boot address=$7000 + 0 + + + 2048W_7800 + Boot Flash size=2048 words Boot address=$7800 + 1 + + + 1024W_7C00 + Boot Flash size=1024 words Boot address=$7C00 + 2 + + + 512W_7E00 + Boot Flash size=512 words Boot start address=$7E00 + 3 + + + + + EESAVE + Preserve EEPROM through the Chip Erase cycle + [3:3] + + + WDTON + Watchdog timer always on + [4:4] + + + SPIEN + Serial program downloading (SPI) enabled + [5:5] + + + JTAGEN + JTAG Interface Enabled + [6:6] + + + OCDEN + On-Chip Debug Enabled + [7:7] + + + + + LOW + <TBD> + 0x0 + + + SUT_CKSEL + Select Clock Source + [5:0] + + true + + + + EXTCLK_6CK_0MS + Ext. Clock; Start-up time: 6 CK + 0 ms + 0 + + + INTRCOSC_6CK_0MS + Int. RC Osc.; Start-up time: 6 CK + 0 ms + 2 + + + INTRCOSC_128KHZ_6CK_0MS + Int. 128kHz RC Osc.; Start-up time: 6 CK + 0 ms + 3 + + + EXTLOFXTAL_1KCK_0MS + Ext. Low-Freq. Crystal; Start-up time: 1K CK + 0 ms + 4 + + + EXTLOFXTAL_32KCK_0MS + Ext. Low-Freq. Crystal; Start-up time: 32K CK + 0 ms + 5 + + + FSOSC_258CK_4MS1_CRES_FASTPWR + Full Swing Oscillator; Start-up time: 258 CK + 4.1 ms; Ceramic res.; fast rising power + 6 + + + FSOSC_1KCK_65MS_CRES_SLOWPWR + Full Swing Oscillator; Start-up time: 1K CK + 65 ms; Ceramic res.; slowly rising power + 7 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 258 CK + 4.1 ms + 8 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 65 ms + 9 + + + EXTXOSC_0MHZ9_3MHZ_258CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 258 CK + 4.1 ms + 10 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 65 ms + 11 + + + EXTXOSC_3MHZ_8MHZ_258CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 258 CK + 4.1 ms + 12 + + + EXTXOSC_3MHZ_8MHZ_1KCK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 65 ms + 13 + + + EXTXOSC_8MHZ_XX_258CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time: 258 CK + 4.1 ms + 14 + + + EXTXOSC_8MHZ_XX_1KCK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 65 ms + 15 + + + EXTCLK_6CK_4MS1 + Ext. Clock; Start-up time: 6 CK + 4.1 ms + 16 + + + INTRCOSC_6CK_4MS1 + Int. RC Osc.; Start-up time: 6 CK + 4.1 ms + 18 + + + INTRCOSC_128KHZ_6CK_4MS + Int. 128kHz RC Osc.; Start-up time: 6 CK + 4 ms + 19 + + + EXTLOFXTAL_1KCK_4MS1 + Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4.1 ms + 20 + + + EXTLOFXTAL_32KCK_4MS1 + Ext. Low-Freq. Crystal; Start-up time: 32K CK + 4.1 ms + 21 + + + FSOSC_258CK_65MS_CRES_SLOWPWR + Full Swing Oscillator; Start-up time: 258 CK + 65 ms; Ceramic res.; slowly rising power + 22 + + + FSOSC_16KCK_0MS_XOSC_BODEN + Full Swing Oscillator; Start-up time: 16K CK + 0 ms; Crystal Osc.; BOD enabled + 23 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 258 CK + 65 ms + 24 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 0 ms + 25 + + + EXTXOSC_0MHZ9_3MHZ_258CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 258 CK + 65 ms + 26 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 0 ms + 27 + + + EXTXOSC_3MHZ_8MHZ_258CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 258 CK + 65 ms + 28 + + + EXTXOSC_3MHZ_8MHZ_16KCK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 0 ms + 29 + + + EXTXOSC_8MHZ_XX_258CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 258 CK + 65 ms + 30 + + + EXTXOSC_8MHZ_XX_16KCK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 0 ms + 31 + + + EXTCLK_6CK_65MS + Ext. Clock; Start-up time: 6 CK + 65 ms + 32 + + + INTRCOSC_6CK_65MS + Int. RC Osc.; Start-up time: 6 CK + 65 ms + 34 + + + INTRCOSC_128KHZ_6CK_64MS + Int. 128kHz RC Osc.; Start-up time: 6 CK + 64 ms + 35 + + + EXTLOFXTAL_1KCK_65MS + Ext. Low-Freq. Crystal; Start-up time: 1K CK + 65 ms + 36 + + + EXTLOFXTAL_32KCK_65MS + Ext. Low-Freq. Crystal; Start-up time: 32K CK + 65 ms + 37 + + + FSOSC_1KCK_0MS_CRES_BODEN + Full Swing Oscillator; Start-up time: 1K CK + 0 ms; Ceramic res.; BOD enable + 38 + + + FSOSC_16KCK_4MS1_XOSC_FASTPWR + Full Swing Oscillator; Start-up time: 16K CK + 4.1 ms; Crystal Osc.; fast rising power + 39 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 0 ms + 40 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 4.1 ms + 41 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 0 ms + 42 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 4.1 ms + 43 + + + EXTXOSC_3MHZ_8MHZ_1KCK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 0 ms + 44 + + + EXTXOSC_3MHZ_8MHZ_16KCK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 4.1 ms + 45 + + + EXTXOSC_8MHZ_XX_1KCK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 0 ms + 46 + + + EXTXOSC_8MHZ_XX_16KCK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 4.1 ms + 47 + + + FSOSC_1KCK_4MS1_CRES_FASTPWR + Full Swing Oscillator; Start-up time: 1K CK + 4.1 ms; Ceramic res.; fast rising power + 54 + + + FSOSC_16KCK_65MS_XOSC_SLOWPWR + Full Swing Oscillator; Start-up time: 16K CK + 65 ms; Crystal Osc.; slowly rising power + 55 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 4.1 ms + 56 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 65 ms + 57 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 4.1 ms + 58 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 65 ms + 59 + + + EXTXOSC_3MHZ_8MHZ_1KCK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 4.1 ms + 60 + + + EXTXOSC_3MHZ_8MHZ_16KCK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 65 ms + 61 + + + EXTXOSC_8MHZ_XX_1KCK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 4.1 ms + 62 + + + EXTXOSC_8MHZ_XX_16KCK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 65 ms + 63 + + + + + CKOUT + Clock output on PORTB1 + [6:6] + + + CKDIV8 + Divide clock by 8 internally + [7:7] + + + + + + + JTAG + JTAG Interface + 0x51 + + + MCUCR + MCU Control Register + 0x4 + + + JTD + JTAG Interface Disable + [7:7] + + + + + MCUSR + MCU Status Register + 0x3 + read-only + + + JTRF + JTAG Reset Flag + [4:4] + + + + + OCDR + On-Chip Debug Related Register in I/O Memory + 0x0 + + + 0 + 255 + + + + + + + LOCKBIT + Lockbits + 0x0 + + + LOCKBIT + <TBD> + 0x0 + + + LB + Memory Lock + [1:0] + + true + + + + PROG_VER_DISABLED + Further programming and verification disabled + 0 + + + PROG_DISABLED + Further programming disabled + 2 + + + NO_LOCK + No memory lock features enabled + 3 + + + + + BLB0 + Boot Loader Protection Mode + [3:2] + + true + + + + LPM_SPM_DISABLE + LPM and SPM prohibited in Application Section + 0 + + + LPM_DISABLE + LPM prohibited in Application Section + 1 + + + SPM_DISABLE + SPM prohibited in Application Section + 2 + + + NO_LOCK + No lock on SPM and LPM in Application Section + 3 + + + + + BLB1 + Boot Loader Protection Mode + [5:4] + + true + + + + LPM_SPM_DISABLE + LPM and SPM prohibited in Boot Section + 0 + + + LPM_DISABLE + LPM prohibited in Boot Section + 1 + + + SPM_DISABLE + SPM prohibited in Boot Section + 2 + + + NO_LOCK + No lock on SPM and LPM in Boot Section + 3 + + + + + + + + + PORTA + I/O Port + 0x20 + + + DDRA + Port A Data Direction Register + 0x1 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + PINA + Port A Input Pins + 0x0 + read-write + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + PORTA + Port A Data Register + 0x2 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + + + PORTB + I/O Port + 0x23 + + + DDRB + Port B Data Direction Register + 0x1 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PINB + Port B Input Pins + 0x0 + read-write + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PORTB + Port B Data Register + 0x2 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + + + PORTC + I/O Port + 0x26 + + + DDRC + Port C Data Direction Register + 0x1 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + PINC + Port C Input Pins + 0x0 + read-write + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + PORTC + Port C Data Register + 0x2 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + + + PORTD + I/O Port + 0x29 + + + DDRD + Port D Data Direction Register + 0x1 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PIND + Port D Input Pins + 0x0 + read-write + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PORTD + Port D Data Register + 0x2 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + + + SPI + Serial Peripheral Interface + 0x4C + + + SPCR + SPI Control Register + 0x0 + + + SPR + SPI Clock Rate Selects + [1:0] + + true + + SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 + + + CPHA + Clock Phase + [2:2] + + + CPOL + Clock polarity + [3:3] + + + MSTR + Master/Slave Select + [4:4] + + + DORD + Data Order + [5:5] + + + SPE + SPI Enable + [6:6] + + + SPIE + SPI Interrupt Enable + [7:7] + + + + + SPDR + SPI Data Register + 0x2 + + + 0 + 255 + + + + + SPSR + SPI Status Register + 0x1 + read-write + + + SPI2X + Double SPI Speed Bit + [0:0] + read-write + + WCOL + Write Collision Flag + [6:6] + read-only + + SPIF + SPI Interrupt Flag + [7:7] + read-only + + + + + + TC0 + Timer/Counter, 8-bit + 0x35 + + + GTCCR + General Timer/Counter Control Register + 0xE + + + PSRSYNC + Prescaler Reset Timer/Counter1 and Timer/Counter0 + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + OCR0A + Timer/Counter0 Output Compare Register + 0x12 + + + 0 + 255 + + + + + OCR0B + Timer/Counter0 Output Compare Register + 0x13 + + + 0 + 255 + + + + + TCCR0A + Timer/Counter Control Register A + 0xF + + + WGM0 + Waveform Generation Mode + [1:0] + + true + WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 + + + COM0B + Compare Output B Mode + [5:4] + + true + COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 + + + COM0A + Compare Output A Mode + [7:6] + + true + + + + + + TCCR0B + Timer/Counter Control Register B + 0x10 + + + CS0 + Clock Select + [2:0] + + true + + CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM02 + Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) + [3:3] + + + FOC0B + Force Output Compare B + [6:6] + write-only + + FOC0A + Force Output Compare A + [7:7] + write-only + + + + TCNT0 + Timer/Counter0 + 0x11 + + + 0 + 255 + + + + + TIFR0 + Timer/Counter0 Interrupt Flag register + 0x0 + read-write + + + TOV0 + Timer/Counter0 Overflow Flag + [0:0] + + + OCF0A + Timer/Counter0 Output Compare Flag 0A + [1:1] + + + OCF0B + Timer/Counter0 Output Compare Flag 0B + [2:2] + + + + + TIMSK0 + Timer/Counter0 Interrupt Mask Register + 0x39 + + + TOIE0 + Timer/Counter0 Overflow Interrupt Enable + [0:0] + + + OCIE0A + Timer/Counter0 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE0B + Timer/Counter0 Output Compare Match B Interrupt Enable + [2:2] + + + + + + + TC1 + Timer/Counter, 16-bit + 0x36 + + + ICR1 + Timer/Counter1 Input Capture Register Bytes + 0x50 + 16 + + + 0 + 65535 + + + + + OCR1A + Timer/Counter1 Output Compare Register A Bytes + 0x52 + 16 + + + 0 + 65535 + + + + + OCR1B + Timer/Counter1 Output Compare Register B Bytes + 0x54 + 16 + + + 0 + 65535 + + + + + TCCR1A + Timer/Counter1 Control Register A + 0x4A + + + WGM1 + Pulse Width Modulator Select Bits + [1:0] + + + 0 + 3 + + + + + COM1B + Compare Output Mode 1B, bits + [5:4] + + true + COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM1A + Compare Output Mode 1A, bits + [7:6] + + true + + + + + + TCCR1B + Timer/Counter1 Control Register B + 0x4B + + + CS1 + Clock Select1 bits + [2:0] + + true + CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM1 + Waveform Generation Mode Bits + [4:3] + + + 0 + 3 + + + + + ICES1 + Input Capture 1 Edge Select + [6:6] + + + ICNC1 + Input Capture 1 Noise Canceler + [7:7] + + + + + TCCR1C + Timer/Counter1 Control Register C + 0x4C + + + FOC1B + Force Output Compare for Channel B + [6:6] + write-only + + FOC1A + Force Output Compare for Channel A + [7:7] + write-only + + + + TCNT1 + Timer/Counter1 Bytes + 0x4E + 16 + + + 0 + 65535 + + + + + TIFR1 + Timer/Counter Interrupt Flag register + 0x0 + read-write + + + TOV1 + Timer/Counter1 Overflow Flag + [0:0] + + + OCF1A + Timer/Counter1 Output Compare A Match Flag + [1:1] + + + OCF1B + Timer/Counter1 Output Compare B Match Flag + [2:2] + + + ICF1 + Timer/Counter1 Input Capture Flag + [5:5] + + + + + TIMSK1 + Timer/Counter1 Interrupt Mask Register + 0x39 + + + TOIE1 + Timer/Counter1 Overflow Interrupt Enable + [0:0] + + + OCIE1A + Timer/Counter1 Output Compare A Match Interrupt Enable + [1:1] + + + OCIE1B + Timer/Counter1 Output Compare B Match Interrupt Enable + [2:2] + + + ICIE1 + Timer/Counter1 Input Capture Interrupt Enable + [5:5] + + + + + + + TC2 + Timer/Counter, 8-bit Async + 0x37 + + + ASSR + Asynchronous Status Register + 0x7F + + + TCR2BUB + Timer/Counter Control Register2 Update Busy + [0:0] + + + TCR2AUB + Timer/Counter Control Register2 Update Busy + [1:1] + + + OCR2BUB + Output Compare Register 2 Update Busy + [2:2] + + + OCR2AUB + Output Compare Register2 Update Busy + [3:3] + + + TCN2UB + Timer/Counter2 Update Busy + [4:4] + + + AS2 + Asynchronous Timer/Counter2 + [5:5] + + + EXCLK + Enable External Clock Input + [6:6] + + + + + GTCCR + General Timer Counter Control register + 0xC + + + PSRASY + Prescaler Reset Timer/Counter2 + [1:1] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + OCR2A + Timer/Counter2 Output Compare Register A + 0x7C + + + 0 + 255 + + + + + OCR2B + Timer/Counter2 Output Compare Register B + 0x7D + + + 0 + 255 + + + + + TCCR2A + Timer/Counter2 Control Register A + 0x79 + + + WGM2 + Waveform Genration Mode + [1:0] + + true + WGM2read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 + + + COM2B + Compare Output B Mode + [5:4] + + true + COM2Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 + + + COM2A + Compare Output A Mode + [7:6] + + true + + + + + + TCCR2B + Timer/Counter2 Control Register B + 0x7A + + + CS2 + Clock Select bits + [2:0] + + true + + CS2read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_32Running, CLK/323PRESCALE_64Running, CLK/644PRESCALE_128Running, CLK/1285PRESCALE_256Running, CLK/2566PRESCALE_1024Running, CLK/10247 + + + WGM22 + Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) + [3:3] + + + FOC2B + Force Output Compare B + [6:6] + write-only + + FOC2A + Force Output Compare A + [7:7] + write-only + + + + TCNT2 + Timer/Counter2 + 0x7B + + + 0 + 255 + + + + + TIFR2 + Timer/Counter Interrupt Flag Register + 0x0 + read-write + + + TOV2 + Timer/Counter2 Overflow Flag + [0:0] + + + OCF2A + Output Compare Flag 2A + [1:1] + + + OCF2B + Output Compare Flag 2B + [2:2] + + + + + TIMSK2 + Timer/Counter Interrupt Mask register + 0x39 + + + TOIE2 + Timer/Counter2 Overflow Interrupt Enable + [0:0] + + + OCIE2A + Timer/Counter2 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE2B + Timer/Counter2 Output Compare Match B Interrupt Enable + [2:2] + + + + + + + TWI + Two Wire Serial Interface + 0xB8 + + + TWAMR + TWI (Slave) Address Mask Register + 0x5 + + + TWAM + TWI (Slave) Address Mask Bits + [7:1] + + + 0 + 127 + + + + + + + TWAR + TWI (Slave) Address register + 0x2 + + + TWGCE + TWI General Call Recognition Enable Bit + [0:0] + + + TWA + TWI (Slave) Address register Bits + [7:1] + + + 0 + 127 + + + + + + + TWBR + TWI Bit Rate register + 0x0 + + + 0 + 255 + + + + + TWCR + TWI Control Register + 0x4 + read-write + + + TWIE + TWI Interrupt Enable + [0:0] + + + TWEN + TWI Enable Bit + [2:2] + + + TWWC + TWI Write Collition Flag + [3:3] + read-only + + TWSTO + TWI Stop Condition Bit + [4:4] + + + TWSTA + TWI Start Condition Bit + [5:5] + + + TWEA + TWI Enable Acknowledge Bit + [6:6] + + + TWINT + TWI Interrupt Flag + [7:7] + + + + + TWDR + TWI Data register + 0x3 + + + 0 + 255 + + + + + TWSR + TWI Status Register + 0x1 + + + TWPS + TWI Prescaler + [1:0] + + true + + TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 + + + TWS + TWI Status + [7:3] + read-only + + 0 + 31 + + + + + + + + + USART0 + USART + 0xC0 + + + UBRR0 + USART Baud Rate Register Bytes + 0x4 + 16 + + + 0 + 65535 + + + + + UCSR0A + USART Control and Status Register A + 0x0 + read-write + + + MPCM0 + Multi-processor Communication Mode + [0:0] + + + U2X0 + Double the USART transmission speed + [1:1] + + + UPE0 + Parity Error + [2:2] + read-only + + DOR0 + Data overRun + [3:3] + read-only + + FE0 + Framing Error + [4:4] + read-only + + UDRE0 + USART Data Register Empty + [5:5] + read-only + + TXC0 + USART Transmit Complete + [6:6] + + + RXC0 + USART Receive Complete + [7:7] + read-only + + + + UCSR0B + USART Control and Status Register B + 0x1 + + + TXB80 + Transmit Data Bit 8 + [0:0] + + + RXB80 + Receive Data Bit 8 + [1:1] + read-only + + UCSZ02 + Character Size + [2:2] + + + TXEN0 + Transmitter Enable + [3:3] + + + RXEN0 + Receiver Enable + [4:4] + + + UDRIE0 + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE0 + TX Complete Interrupt Enable + [6:6] + + + RXCIE0 + RX Complete Interrupt Enable + [7:7] + + + + + UCSR0C + USART Control and Status Register C + 0x2 + + + UCPOL0 + Clock Polarity + [0:0] + UCPOL0read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 + + + UCSZ0 + Character Size + [2:1] + + + 0 + 3 + + + UCSZ0read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 + + + USBS0 + Stop Bit Select + [3:3] + + true + + USBS0read-writeSTOP11-bit0STOP22-bit1 + + + UPM0 + Parity Mode Bits + [5:4] + + true + + UPM0read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 + + + UMSEL0 + USART Mode Select + [7:6] + + true + + UMSEL0read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 + + + + + UDR0 + USART I/O Data Register + 0x6 + + + 0 + 255 + + + + + + + WDT + Watchdog Timer + 0x60 + + + WDTCSR + Watchdog Timer Control Register + 0x0 + read-write + + + WDE + Watch Dog Enable + [3:3] + + + WDCE + Watchdog Change Enable + [4:4] + + + WDIE + Watchdog Timeout Interrupt Enable + [6:6] + + + WDIF + Watchdog Timeout Interrupt Flag + [7:7] + + WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 + + WDPHWatchdog Timer Prescaler - High Bit[5:5] + + + + + + \ No newline at end of file diff --git a/misc/svd/atmega8.svd b/misc/svd/atmega8.svd new file mode 100644 index 0000000..0fca25e --- /dev/null +++ b/misc/svd/atmega8.svd @@ -0,0 +1,2775 @@ + + Atmel + ATmega8 + 8 + 8 + read-write + 0 + 0xff + + + AC + Analog Comparator + 0x28 + + + ACSR + Analog Comparator Control And Status Register + 0x0 + read-only + + + ACIS + Analog Comparator Interrupt Mode Select bits + [1:0] + + true + + + + VAL_0x00 + Interrupt on Toggle + 0 + + + VAL_0x01 + Reserved + 1 + + + VAL_0x02 + Interrupt on Falling Edge + 2 + + + VAL_0x03 + Interrupt on Rising Edge + 3 + + + + + ACIC + Analog Comparator Input Capture Enable + [2:2] + + + ACIE + Analog Comparator Interrupt Enable + [3:3] + + + ACI + Analog Comparator Interrupt Flag + [4:4] + + + ACO + Analog Compare Output + [5:5] + + + ACBG + Analog Comparator Bandgap Select + [6:6] + + + ACD + Analog Comparator Disable + [7:7] + + + + + SFIOR + Special Function IO Register + 0x28 + + + ACME + Analog Comparator Multiplexer Enable + [3:3] + + + + + + + ADC + Analog-to-Digital Converter + 0x24 + + + ADC + ADC Data Register Bytes + 0x0 + 16 + + + 0 + 65535 + + + + + ADCSRA + The ADC Control and Status register + 0x2 + + + ADPS + ADC Prescaler Select Bits + [2:0] + + true + + + + VAL_0x00 + 2 + 0 + + + VAL_0x01 + 2 + 1 + + + VAL_0x02 + 4 + 2 + + + VAL_0x03 + 8 + 3 + + + VAL_0x04 + 16 + 4 + + + VAL_0x05 + 32 + 5 + + + VAL_0x06 + 64 + 6 + + + VAL_0x07 + 128 + 7 + + + + + ADIE + ADC Interrupt Enable + [3:3] + + + ADIF + ADC Interrupt Flag + [4:4] + + + ADFR + ADC Free Running Select + [5:5] + + + ADSC + ADC Start Conversion + [6:6] + + + ADEN + ADC Enable + [7:7] + + + + + ADMUX + The ADC multiplexer Selection Register + 0x3 + + + MUX + Analog Channel and Gain Selection Bits + [3:0] + + + 0 + 15 + + + + + ADLAR + Left Adjust Result + [5:5] + + + REFS + Reference Selection Bits + [7:6] + + true + + + + VAL_0x00 + AREF, Internal Vref turned off + 0 + + + VAL_0x01 + AVCC with external capacitor at AREF pin + 1 + + + VAL_0x02 + Reserved + 2 + + + VAL_0x03 + Internal 2.56V Voltage Reference with external capacitor at AREF pin + 3 + + + + + + + + + CPU + CPU Registers + 0x50 + + RESET + External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + 0 + + + INT0 + External Interrupt Request 0 + 1 + + + INT1 + External Interrupt Request 1 + 2 + + + TIMER2_COMP + Timer/Counter2 Compare Match + 3 + + + TIMER2_OVF + Timer/Counter2 Overflow + 4 + + + TIMER1_CAPT + Timer/Counter1 Capture Event + 5 + + + TIMER1_COMPA + Timer/Counter1 Compare Match A + 6 + + + TIMER1_COMPB + Timer/Counter1 Compare Match B + 7 + + + TIMER1_OVF + Timer/Counter1 Overflow + 8 + + + TIMER0_OVF + Timer/Counter0 Overflow + 9 + + + SPI_STC + Serial Transfer Complete + 10 + + + USART_RXC + USART, Rx Complete + 11 + + + USART_UDRE + USART Data Register Empty + 12 + + + USART_TXC + USART, Tx Complete + 13 + + + ADC + ADC Conversion Complete + 14 + + + EE_RDY + EEPROM Ready + 15 + + + ANA_COMP + Analog Comparator + 16 + + + TWI + 2-wire Serial Interface + 17 + + + SPM_RDY + Store Program Memory Ready + 18 + + + + MCUCR + MCU Control Register + 0x5 + + + ISC0 + Interrupt Sense Control 0 Bits + [1:0] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change in INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC1 + Interrupt Sense Control 1 Bits + [3:2] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change in INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + SM + Sleep Mode Select + [6:4] + + true + + + + IDLE + Idle + 0 + + + ADC + ADC Noise Reduction (If Available) + 1 + + + PDOWN + Power Down + 2 + + + PSAVE + Power Save + 3 + + + VAL_0x04 + Reserved + 4 + + + VAL_0x05 + Reserved + 5 + + + STDBY + Standby + 6 + + + VAL_0x07 + Reserved + 7 + + + + + SE + Sleep Enable + [7:7] + + + + + MCUCSR + MCU Control And Status Register + 0x4 + + + PORF + Power-on reset flag + [0:0] + + + EXTRF + External Reset Flag + [1:1] + + + BORF + Brown-out Reset Flag + [2:2] + + + WDRF + Watchdog Reset Flag + [3:3] + + + + + OSCCAL + Oscillator Calibration Value + 0x1 + + + OSCCAL + Oscillator Calibration + [7:0] + + + 0 + 255 + + + + + + + SFIOR + Special Function IO Register + 0x0 + + + PSR10 + Prescaler Reset Timer/Counter1 and Timer/Counter0 + [0:0] + + + PUD + Pull-up Disable + [2:2] + + + ADHSM + ADC High Speed Mode + [4:4] + + + + + SPMCR + Store Program Memory Control Register + 0x7 + + + SPMEN + Store Program Memory Enable + [0:0] + + + PGERS + Page Erase + [1:1] + + + PGWRT + Page Write + [2:2] + + + BLBSET + Boot Lock Bit Set + [3:3] + + + RWWSRE + Read-While-Write Section Read Enable + [4:4] + + + RWWSB + Read-While-Write Section Busy + [6:6] + + + SPMIE + SPM Interrupt Enable + [7:7] + + + + + + + EEPROM + EEPROM + 0x3C + + + EEAR + EEPROM Address Register Bytes + 0x2 + 16 + + + 0 + 65535 + + + + + EECR + EEPROM Control Register + 0x0 + + + EERE + EEPROM Read Enable + [0:0] + + + EEWE + EEPROM Write Enable + [1:1] + + + EEMWE + EEPROM Master Write Enable + [2:2] + + + EERIE + EEPROM Ready Interrupt Enable + [3:3] + + + + + EEDR + EEPROM Data Register + 0x1 + + + 0 + 255 + + + + + + + EXINT + External Interrupts + 0x55 + + + GICR + General Interrupt Control Register + 0x6 + + + IVCE + Interrupt Vector Change Enable + [0:0] + + + IVSEL + Interrupt Vector Select + [1:1] + + + INT + External Interrupt Request 1 Enable + [7:6] + + + 0 + 3 + + + + + + + GIFR + General Interrupt Flag Register + 0x5 + + + INTF + External Interrupt Flags + [7:6] + + + 0 + 3 + + + + + + + MCUCR + MCU Control Register + 0x0 + + + ISC0 + Interrupt Sense Control 0 Bits + [1:0] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + ISC1 + Interrupt Sense Control 1 Bits + [3:2] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + + + + + FUSE + Fuses + 0x0 + + + HIGH + <TBD> + 0x1 + + + BOOTRST + Boot Reset vector Enabled + [0:0] + + + BOOTSZ + Select Boot Size + [2:1] + + true + + + + 1024W_0C00 + Boot Flash size=1024 words Boot address=$0C00 + 0 + + + 512W_0E00 + Boot Flash size=512 words Boot address=$0E00 + 1 + + + 256W_0F00 + Boot Flash size=256 words Boot address=$0F00 + 2 + + + 128W_0F80 + Boot Flash size=128 words Boot address=$0F80 + 3 + + + + + EESAVE + Preserve EEPROM through the Chip Erase cycle + [3:3] + + + CKOPT + CKOPT fuse (operation dependent of CKSEL fuses) + [4:4] + + + SPIEN + Serial program downloading (SPI) enabled + [5:5] + + + WDTON + Watch-dog Timer always on + [6:6] + + + RSTDISBL + Reset Disabled (Enable PC6 as i/o pin) + [7:7] + + + + + LOW + <TBD> + 0x0 + + + SUT_CKSEL + Select Clock Source + [5:0] + + true + + + + EXTCLK_6CK_0MS + Ext. Clock; Start-up time: 6 CK + 0 ms + 0 + + + INTRCOSC_1MHZ_6CK_0MS + Int. RC Osc. 1 MHz; Start-up time: 6 CK + 0 ms + 1 + + + INTRCOSC_2MHZ_6CK_0MS + Int. RC Osc. 2 MHz; Start-up time: 6 CK + 0 ms + 2 + + + INTRCOSC_4MHZ_6CK_0MS + Int. RC Osc. 4 MHz; Start-up time: 6 CK + 0 ms + 3 + + + INTRCOSC_8MHZ_6CK_0MS + Int. RC Osc. 8 MHz; Start-up time: 6 CK + 0 ms + 4 + + + EXTRCOSC_XX_0MHZ9_18CK_0MS + Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 0 ms + 5 + + + EXTRCOSC_0MHZ9_3MHZ_18CK_0MS + Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 0 ms + 6 + + + EXTRCOSC_3MHZ_8MHZ_18CK_0MS + Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 0 ms + 7 + + + EXTRCOSC_8MHZ_12MHZ_18CK_0MS + Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 0 ms + 8 + + + EXTLOFXTAL_1KCK_4MS + Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4 ms + 9 + + + EXTLOFXTALRES_258CK_4MS + Ext. Crystal/Resonator Low Freq.; Start-up time: 258 CK + 4 ms + 10 + + + EXTLOFXTALRES_1KCK_64MS + Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 64 ms + 11 + + + EXTMEDFXTALRES_258CK_4MS + Ext. Crystal/Resonator Medium Freq.; Start-up time: 258 CK + 4 ms + 12 + + + EXTMEDFXTALRES_1KCK_64MS + Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 64 ms + 13 + + + EXTHIFXTALRES_258CK_4MS + Ext. Crystal/Resonator High Freq.; Start-up time: 258 CK + 4 ms + 14 + + + EXTHIFXTALRES_1KCK_64MS + Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 64 ms + 15 + + + EXTCLK_6CK_4MS + Ext. Clock; Start-up time: 6 CK + 4 ms + 16 + + + INTRCOSC_1MHZ_6CK_4MS + Int. RC Osc. 1 MHz; Start-up time: 6 CK + 4 ms + 17 + + + INTRCOSC_2MHZ_6CK_4MS + Int. RC Osc. 2 MHz; Start-up time: 6 CK + 4 ms + 18 + + + INTRCOSC_4MHZ_6CK_4MS + Int. RC Osc. 4 MHz; Start-up time: 6 CK + 4 ms + 19 + + + INTRCOSC_8MHZ_6CK_4MS + Int. RC Osc. 8 MHz; Start-up time: 6 CK + 4 ms + 20 + + + EXTRCOSC_XX_0MHZ9_18CK_4MS + Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 4 ms + 21 + + + EXTRCOSC_0MHZ9_3MHZ_18CK_4MS + Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 4 ms + 22 + + + EXTRCOSC_3MHZ_8MHZ_18CK_4MS + Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 4 ms + 23 + + + EXTRCOSC_8MHZ_12MHZ_18CK_4MS + Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 4 ms + 24 + + + EXTLOFXTAL_1KCK_64MS + Ext. Low-Freq. Crystal; Start-up time: 1K CK + 64 ms + 25 + + + EXTLOFXTALRES_258CK_64MS + Ext. Crystal/Resonator Low Freq.; Start-up time: 258 CK + 64 ms + 26 + + + EXTLOFXTALRES_16KCK_0MS + Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 0 ms + 27 + + + EXTMEDFXTALRES_258CK_64MS + Ext. Crystal/Resonator Medium Freq.; Start-up time: 258 CK + 64 ms + 28 + + + EXTMEDFXTALRES_16KCK_0MS + Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 0 ms + 29 + + + EXTHIFXTALRES_258CK_64MS + Ext. Crystal/Resonator High Freq.; Start-up time: 258 CK + 64 ms + 30 + + + EXTHIFXTALRES_16KCK_0MS + Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 0 ms + 31 + + + EXTCLK_6CK_64MS + Ext. Clock; Start-up time: 6 CK + 64 ms + 32 + + + INTRCOSC_1MHZ_6CK_64MS_DEFAULT + Int. RC Osc. 1 MHz; Start-up time: 6 CK + 64 ms; default value + 33 + + + INTRCOSC_2MHZ_6CK_64MS + Int. RC Osc. 2 MHz; Start-up time: 6 CK + 64 ms + 34 + + + INTRCOSC_4MHZ_6CK_64MS + Int. RC Osc. 4 MHz; Start-up time: 6 CK + 64 ms + 35 + + + INTRCOSC_8MHZ_6CK_64MS + Int. RC Osc. 8 MHz; Start-up time: 6 CK + 64 ms + 36 + + + EXTRCOSC_XX_0MHZ9_18CK_64MS + Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 64 ms + 37 + + + EXTRCOSC_0MHZ9_3MHZ_18CK_64MS + Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 64 ms + 38 + + + EXTRCOSC_3MHZ_8MHZ_18CK_64MS + Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 64 ms + 39 + + + EXTRCOSC_8MHZ_12MHZ_18CK_64MS + Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 64 ms + 40 + + + EXTLOFXTAL_32KCK_64MS + Ext. Low-Freq. Crystal; Start-up time: 32K CK + 64 ms + 41 + + + EXTLOFXTALRES_1KCK_0MS + Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 0 ms + 42 + + + EXTLOFXTALRES_16KCK_4MS + Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 4 ms + 43 + + + EXTMEDFXTALRES_1KCK_0MS + Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 0 ms + 44 + + + EXTMEDFXTALRES_16KCK_4MS + Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 4 ms + 45 + + + EXTHIFXTALRES_1KCK_0MS + Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 0 ms + 46 + + + EXTHIFXTALRES_16KCK_4MS + Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 4 ms + 47 + + + EXTRCOSC_XX_0MHZ9_6CK_4MS + Ext. RC Osc. - 0.9 MHz; Start-up time: 6 CK + 4 ms + 53 + + + EXTRCOSC_0MHZ9_3MHZ_6CK_4MS + Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 6 CK + 4 ms + 54 + + + EXTRCOSC_3MHZ_8MHZ_6CK_4MS + Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 6 CK + 4 ms + 55 + + + EXTRCOSC_8MHZ_12MHZ_6CK_4MS + Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 6 CK + 4 ms + 56 + + + EXTLOFXTALRES_1KCK_4MS + Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 4 ms + 58 + + + EXTLOFXTALRES_16KCK_64MS + Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 64 ms + 59 + + + EXTMEDFXTALRES_1KCK_4MS + Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 4 ms + 60 + + + EXTMEDFXTALRES_16KCK_64MS + Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 64 ms + 61 + + + EXTHIFXTALRES_1KCK_4MS + Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 4 ms + 62 + + + EXTHIFXTALRES_16KCK_64MS + Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 64 ms + 63 + + + + + BODEN + Brown-out detection enabled + [6:6] + + + BODLEVEL + Brownout detector trigger level + [7:7] + + true + + + + 4V0 + Brown-out detection at VCC=4.0 V + 0 + + + 2V7 + Brown-out detection at VCC=2.7 V + 1 + + + + + + + + + LOCKBIT + Lockbits + 0x0 + + + LOCKBIT + <TBD> + 0x0 + + + LB + Memory Lock + [1:0] + + true + + + + PROG_VER_DISABLED + Further programming and verification disabled + 0 + + + PROG_DISABLED + Further programming disabled + 2 + + + NO_LOCK + No memory lock features enabled + 3 + + + + + BLB0 + Boot Loader Protection Mode + [3:2] + + true + + + + LPM_SPM_DISABLE + LPM and SPM prohibited in Application Section + 0 + + + LPM_DISABLE + LPM prohibited in Application Section + 1 + + + SPM_DISABLE + SPM prohibited in Application Section + 2 + + + NO_LOCK + No lock on SPM and LPM in Application Section + 3 + + + + + BLB1 + Boot Loader Protection Mode + [5:4] + + true + + + + LPM_SPM_DISABLE + LPM and SPM prohibited in Boot Section + 0 + + + LPM_DISABLE + LPM prohibited in Boot Section + 1 + + + SPM_DISABLE + SPM prohibited in Boot Section + 2 + + + NO_LOCK + No lock on SPM and LPM in Boot Section + 3 + + + + + + + + + PORTB + I/O Port + 0x36 + + + DDRB + Port B Data Direction Register + 0x1 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PINB + Port B Input Pins + 0x0 + read-write + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PORTB + Port B Data Register + 0x2 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + + + PORTC + I/O Port + 0x33 + + + DDRC + Port C Data Direction Register + 0x1 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + + + PINC + Port C Input Pins + 0x0 + read-write + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + + + PORTC + Port C Data Register + 0x2 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + + + + + PORTD + I/O Port + 0x30 + + + DDRD + Port D Data Direction Register + 0x1 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PIND + Port D Input Pins + 0x0 + read-write + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PORTD + Port D Data Register + 0x2 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + + + SPI + Serial Peripheral Interface + 0x2D + + + SPCR + SPI Control Register + 0x0 + + + SPR + SPI Clock Rate Selects + [1:0] + + true + + + + VAL_0x00 + fosc/4 + 0 + + + VAL_0x01 + fosc/16 + 1 + + + VAL_0x02 + fosc/64 + 2 + + + VAL_0x03 + fosc/128 + 3 + + + + + CPHA + Clock Phase + [2:2] + + + CPOL + Clock polarity + [3:3] + + + MSTR + Master/Slave Select + [4:4] + + + DORD + Data Order + [5:5] + + + SPE + SPI Enable + [6:6] + + + SPIE + SPI Interrupt Enable + [7:7] + + + + + SPDR + SPI Data Register + 0x2 + + + 0 + 255 + + + + + SPSR + SPI Status Register + 0x1 + read-only + + + SPI2X + Double SPI Speed Bit + [0:0] + + + WCOL + Write Collision Flag + [6:6] + + + SPIF + SPI Interrupt Flag + [7:7] + + + + + + + TC0 + Timer/Counter, 8-bit + 0x52 + + + TCCR0 + Timer/Counter0 Control Register + 0x1 + + + CS00 + Clock Select0 bit 0 + [0:0] + + true + + + + VAL_0x00 + No Clock Source (Stopped) + 0 + + + VAL_0x01 + Running, No Prescaling + 1 + + + + + CS01 + Clock Select0 bit 1 + [1:1] + + + CS02 + Clock Select0 bit 2 + [2:2] + + + + + TCNT0 + Timer Counter 0 + 0x0 + + + 0 + 255 + + + + + TIFR + Timer/Counter Interrupt Flag register + 0x6 + + + TOV0 + Timer/Counter0 Overflow Flag + [0:0] + + + + + TIMSK + Timer/Counter Interrupt Mask Register + 0x7 + + + TOIE0 + Timer/Counter0 Overflow Interrupt Enable + [0:0] + + + + + + + TC1 + Timer/Counter, 16-bit + 0x46 + + + ICR1 + Timer/Counter1 Input Capture Register Bytes + 0x0 + 16 + + + 0 + 65535 + + + + + OCR1A + Timer/Counter1 Output Compare Register Bytes + 0x4 + 16 + + + 0 + 65535 + + + + + OCR1B + Timer/Counter1 Output Compare Register Bytes + 0x2 + 16 + + + 0 + 65535 + + + + + TCCR1A + Timer/Counter1 Control Register A + 0x9 + + + WGM1 + Waveform Generation Mode + [1:0] + + + 0 + 3 + + + + + FOC1B + Force Output Compare 1B + [2:2] + + + FOC1A + Force Output Compare 1A + [3:3] + + + COM1B + Compare Output Mode 1B, bits + [5:4] + + + 0 + 3 + + + + + COM1A + Compare Output Mode 1A, bits + [7:6] + + + 0 + 3 + + + + + + + TCCR1B + Timer/Counter1 Control Register B + 0x8 + + + CS1 + Prescaler source of Timer/Counter 1 + [2:0] + + true + + + + VAL_0x00 + No Clock Source (Stopped) + 0 + + + VAL_0x01 + Running, No Prescaling + 1 + + + VAL_0x02 + Running, CLK/8 + 2 + + + VAL_0x03 + Running, CLK/64 + 3 + + + VAL_0x04 + Running, CLK/256 + 4 + + + VAL_0x05 + Running, CLK/1024 + 5 + + + VAL_0x06 + Running, ExtClk Tx Falling Edge + 6 + + + VAL_0x07 + Running, ExtClk Tx Rising Edge + 7 + + + + + WGM1 + Waveform Generation Mode + [4:3] + + + 0 + 3 + + + + + ICES1 + Input Capture 1 Edge Select + [6:6] + + + ICNC1 + Input Capture 1 Noise Canceler + [7:7] + + + + + TCNT1 + Timer/Counter1 Bytes + 0x6 + 16 + + + 0 + 65535 + + + + + TIFR + Timer/Counter Interrupt Flag register + 0x12 + read-only + + + TOV1 + Timer/Counter1 Overflow Flag + [2:2] + + + OCF1B + Output Compare Flag 1B + [3:3] + + + OCF1A + Output Compare Flag 1A + [4:4] + + + ICF1 + Input Capture Flag 1 + [5:5] + + + + + TIMSK + Timer/Counter Interrupt Mask Register + 0x13 + + + TOIE1 + Timer/Counter1 Overflow Interrupt Enable + [2:2] + + + OCIE1B + Timer/Counter1 Output CompareB Match Interrupt Enable + [3:3] + + + OCIE1A + Timer/Counter1 Output CompareA Match Interrupt Enable + [4:4] + + + TICIE1 + Timer/Counter1 Input Capture Interrupt Enable + [5:5] + + + + + + + TC2 + Timer/Counter, 8-bit Async + 0x42 + + + ASSR + Asynchronous Status Register + 0x0 + + + TCR2UB + Timer/counter Control Register2 Update Busy + [0:0] + + + OCR2UB + Output Compare Register2 Update Busy + [1:1] + + + TCN2UB + Timer/Counter2 Update Busy + [2:2] + + + AS2 + Asynchronous Timer/counter2 + [3:3] + + + + + OCR2 + Timer/Counter2 Output Compare Register + 0x1 + + + 0 + 255 + + + + + SFIOR + Special Function IO Register + 0xE + + + PSR2 + Prescaler Reset Timer/Counter2 + [1:1] + + + + + TCCR2 + Timer/Counter2 Control Register + 0x3 + + + CS2 + Clock Select bits + [2:0] + + true + + + + VAL_0x00 + No Clock Source (Stopped) + 0 + + + VAL_0x01 + Running, No Prescaling + 1 + + + VAL_0x02 + Running, CLK/8 + 2 + + + VAL_0x03 + Running, CLK/32 + 3 + + + VAL_0x04 + Running, CLK/64 + 4 + + + VAL_0x05 + Running, CLK/128 + 5 + + + VAL_0x06 + Running, CLK/256 + 6 + + + VAL_0x07 + Running, CLK/1024 + 7 + + + + + WGM21 + Waveform Generation Mode + [3:3] + + + COM2 + Compare Output Mode bits + [5:4] + + + 0 + 3 + + + + + WGM20 + Waveform Genration Mode + [6:6] + + true + + + + VAL_0x00 + Normal + 0 + + + VAL_0x01 + CTC + 1 + + + + + FOC2 + Force Output Compare + [7:7] + + + + + TCNT2 + Timer/Counter2 + 0x2 + + + 0 + 255 + + + + + TIFR + Timer/Counter Interrupt Flag Register + 0x16 + read-only + + + TOV2 + Timer/Counter2 Overflow Flag + [6:6] + + + OCF2 + Output Compare Flag 2 + [7:7] + + + + + TIMSK + Timer/Counter Interrupt Mask register + 0x17 + + + TOIE2 + Timer/Counter2 Overflow Interrupt Enable + [6:6] + + + OCIE2 + Timer/Counter2 Output Compare Match Interrupt Enable + [7:7] + + + + + + + TWI + Two Wire Serial Interface + 0x20 + + + TWAR + TWI (Slave) Address register + 0x2 + + + TWGCE + TWI General Call Recognition Enable Bit + [0:0] + + + TWA + TWI (Slave) Address register Bits + [7:1] + + + 0 + 127 + + + + + + + TWBR + TWI Bit Rate register + 0x0 + + + 0 + 255 + + + + + TWCR + TWI Control Register + 0x36 + read-only + + + TWIE + TWI Interrupt Enable + [0:0] + + + TWEN + TWI Enable Bit + [2:2] + + + TWWC + TWI Write Collition Flag + [3:3] + + + TWSTO + TWI Stop Condition Bit + [4:4] + + + TWSTA + TWI Start Condition Bit + [5:5] + + + TWEA + TWI Enable Acknowledge Bit + [6:6] + + + TWINT + TWI Interrupt Flag + [7:7] + + + + + TWDR + TWI Data register + 0x3 + + + 0 + 255 + + + + + TWSR + TWI Status Register + 0x1 + + + TWPS + TWI Prescaler + [1:0] + + true + + + + VAL_0x00 + 1 + 0 + + + VAL_0x01 + 4 + 1 + + + VAL_0x02 + 16 + 2 + + + VAL_0x03 + 64 + 3 + + + + + TWS + TWI Status + [7:3] + + + 0 + 31 + + + + + + + + + USART + USART + 0x29 + + + UBRRH + USART Baud Rate Register Hight Byte + 0x17 + + + 0 + 255 + + + + + UBRRL + USART Baud Rate Register Low Byte + 0x0 + + + 0 + 255 + + + + + UCSRA + USART Control and Status Register A + 0x2 + read-only + + + MPCM + Multi-processor Communication Mode + [0:0] + + + U2X + Double the USART transmission speed + [1:1] + + + UPE + Parity Error + [2:2] + + + DOR + Data overRun + [3:3] + + + FE + Framing Error + [4:4] + + + UDRE + USART Data Register Empty + [5:5] + + + TXC + USART Transmitt Complete + [6:6] + + + RXC + USART Receive Complete + [7:7] + + + + + UCSRB + USART Control and Status Register B + 0x1 + + + TXB8 + Transmit Data Bit 8 + [0:0] + + + RXB8 + Receive Data Bit 8 + [1:1] + + + UCSZ2 + Character Size + [2:2] + + + TXEN + Transmitter Enable + [3:3] + + + RXEN + Receiver Enable + [4:4] + + + UDRIE + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE + TX Complete Interrupt Enable + [6:6] + + + RXCIE + RX Complete Interrupt Enable + [7:7] + + + + + UCSRC + USART Control and Status Register C + 0x17 + + + UCPOL + Clock Polarity + [0:0] + + + UCSZ + Character Size + [2:1] + + + 0 + 3 + + + + + USBS + Stop Bit Select + [3:3] + + true + + + + VAL_0x00 + 1-bit + 0 + + + VAL_0x01 + 2-bit + 1 + + + + + UPM + Parity Mode Bits + [5:4] + + true + + + + VAL_0x00 + Disabled + 0 + + + VAL_0x01 + Reserved + 1 + + + VAL_0x02 + Enabled, Even Parity + 2 + + + VAL_0x03 + Enabled, Odd Parity + 3 + + + + + UMSEL + USART Mode Select + [6:6] + + true + + + + VAL_0x00 + Asynchronous Operation + 0 + + + VAL_0x01 + Synchronous Operation + 1 + + + + + URSEL + Register Select + [7:7] + + + + + UDR + USART I/O Data Register + 0x3 + + + 0 + 255 + + + + + + + WDT + Watchdog Timer + 0x41 + + + WDTCR + Watchdog Timer Control Register + 0x0 + + + WDP + Watch Dog Timer Prescaler bits + [2:0] + + true + + + + VAL_0x00 + Oscillator Cycles 16K + 0 + + + VAL_0x01 + Oscillator Cycles 32K + 1 + + + VAL_0x02 + Oscillator Cycles 64K + 2 + + + VAL_0x03 + Oscillator Cycles 128K + 3 + + + VAL_0x04 + Oscillator Cycles 256K + 4 + + + VAL_0x05 + Oscillator Cycles 512K + 5 + + + VAL_0x06 + Oscillator Cycles 1024K + 6 + + + VAL_0x07 + Oscillator Cycles 2048K + 7 + + + + + WDE + Watch Dog Enable + [3:3] + + + WDCE + Watchdog Change Enable + [4:4] + + + + + + + \ No newline at end of file diff --git a/misc/svd/attiny84.svd b/misc/svd/attiny84.svd new file mode 100644 index 0000000..2f65316 --- /dev/null +++ b/misc/svd/attiny84.svd @@ -0,0 +1,1627 @@ + + Atmel + ATtiny84 + 8 + 8 + read-write + 0 + 0xff + + + AC + Analog Comparator + 0x21 + + + ACSR + Analog Comparator Control And Status Register + 0x7 + read-write + + + ACIS + Analog Comparator Interrupt Mode Select + [1:0] + + true + + ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 + + + ACIC + Analog Comparator Input Capture Enable + [2:2] + + + ACIE + Analog Comparator Interrupt Enable + [3:3] + + + ACI + Analog Comparator Interrupt Flag + [4:4] + + + ACO + Analog Compare Output + [5:5] + read-only + + ACBG + Analog Comparator Bandgap Select + [6:6] + + + ACD + Analog Comparator Disable + [7:7] + + + + + ADCSRB + ADC Control and Status Register B + 0x2 + + + ACME + Analog Comparator Multiplexer Enable + [6:6] + + + + + DIDR0 + Digital Input Disable Register 0 + 0x0 + + + ADC1D + ADC1 (AIN0) Digital input buffer disable + [1:1] + + ADC2DADC2 (AIN1) Digital input buffer disable21read-write + + + + + + ADC + Analog-to-Digital Converter + 0x21 + + + ADC + ADC Data Register Bytes + 0x3 + 16 + + + 0 + 65535 + + + + + ADCSRA + ADC Control and Status Register A + 0x5 + read-write + + + ADPS + ADC Prescaler Select Bits + [2:0] + + true + + ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 + + + ADIE + ADC Interrupt Enable + [3:3] + + + ADIF + ADC Interrupt Flag + [4:4] + + + ADATE + ADC Auto Trigger Enable + [5:5] + + + ADSC + ADC Start Conversion + [6:6] + + + ADEN + ADC Enable + [7:7] + + + + + ADCSRB + ADC Control and Status Register B + 0x2 + + + ADTS + ADC Auto Trigger Source bits + [2:0] + + true + + ADTSread-writeFREEFree Running mode0ACAnalog Comparator1INT0External Interrupt Request 02TC0_CMATimer/Counter0 Compare Match A3TC0_OVFTimer/Counter0 Overflow4TC0_CMBTimer/Counter0 Compare Match B5PCIRPin Change Interrupt Request6 + + + ADLAR + ADC Left Adjust Result + [4:4] + + + BIN + Bipolar Input Mode + [7:7] + + + + + ADMUX + ADC Multiplexer Selection Register + 0x6 + + + 0 + 255 + + + MUXAnalog Channel and Gain Selection Bits06read-writeMUXread-writeADC0Single-ended Input ADC00ADC1Single-ended Input ADC11ADC2Single-ended Input ADC22ADC3Single-ended Input ADC33ADC4Single-ended Input ADC44ADC5Single-ended Input ADC55ADC6Single-ended Input ADC66ADC7Single-ended Input ADC77ADC_GND0V (GND)32ADC_VBGInternal Reference (VBG)33TEMPSENSTemperature sensor34ADC0_ADC0_20XDifferential Inputs Positive ADC0 Negative ADC0 20x Gain35ADC0_ADC1_1XDifferential Inputs Positive ADC0 Negative ADC1 1x Gain8ADC0_ADC1_20XDifferential Inputs Postive ADC0 Negative ADC1 20x Gain9ADC0_ADC3_1XDifferential Inputs Positive ADC0 Negative ADC3 1x Gain10ADC0_ADC3_20XDifferential Inputs Positive ADC0 Negative ADC3 20x Gain11ADC1_ADC0_1XDifferential Inputs Positive ADC1 Negative ADC0 1x Gain40ADC1_ADC0_20XDifferential Inputs Positive ADC1 Negative ADC0 20x Gain41ADC1_ADC2_1XDifferential Inputs Positive ADC1 Negative ADC2 1x Gain12ADC1_ADC2_20XDifferential Inputs Positive ADC1 Negative ADC2 20x Gain13ADC1_ADC3_1XDifferential Inputs Positive ADC1 Negative ADC3 1x Gain14ADC1_ADC3_20XDifferential Inputs Positive ADC1 Negative ADC3 20x Gain15ADC2_ADC1_1XDifferential Inputs Positive ADC2 Negative ADC2 1x Gain44ADC2_ADC1_20XDifferential Inputs Positive ADC2 Negative ADC2 20x Gain45ADC2_ADC3_1XDifferential Inputs Positive ADC2 Negative ADC3 1x Gain16ADC2_ADC3_20XDifferential Inputs Positive ADC2 Negative ADC3 20x Gain17ADC3_ADC0_1XDifferential Inputs Positive ADC3 Negative ADC0 1x Gain42ADC3_ADC0_20XDifferential Inputs Positive ADC3 Negative ADC0 20x Gain43ADC3_ADC1_1XDifferential Inputs Positive ADC3 Negative ADC1 1x Gain46ADC3_ADC1_20XDifferential Inputs Positive ADC3 Negative ADC1 20x Gain47ADC3_ADC2_1XDifferential Inputs Positive ADC3 Negative ADC2 1x Gain48ADC3_ADC2_20XDifferential Inputs Positive ADC3 Negative ADC2 20x Gain49ADC3_ADC3_1XDifferential Inputs Positive ADC3 Negative ADC3 1x Gain36ADC3_ADC3_20XDifferential Inputs Positive ADC3 Negative ADC3 20x Gain37ADC3_ADC4_1XDifferential Inputs Positive ADC4 Negative ADC0 1x Gain18ADC3_ADC4_20XDifferential Inputs Positive ADC4 Negative ADC0 20x Gain19ADC3_ADC5_1XDifferential Inputs Positive ADC5 Negative ADC1 1x Gain20ADC3_ADC5_20XDifferential Inputs Positive ADC5 Negative ADC1 20x Gain21ADC3_ADC6_1XDifferential Inputs Positive ADC6 Negative ADC2 1x Gain22ADC3_ADC6_20XDifferential Inputs Positive ADC6 Negative ADC2 20x Gain23ADC3_ADC7_1XDifferential Inputs Positive ADC7 Negative ADC3 1x Gain24ADC3_ADC7_20XDifferential Inputs Positive ADC7 Negative ADC3 20x Gain25ADC4_ADC3_1XDifferential Inputs Positive ADC4 Negative ADC3 1x Gain50ADC4_ADC3_20XDifferential Inputs Positive ADC4 Negative ADC3 20x Gain51ADC4_ADC5_1XDifferential Inputs Positive ADC4 Negative ADC5 1x Gain26ADC4_ADC5_20XDifferential Inputs Positive ADC4 Negative ADC5 20x Gain27ADC5_ADC3_1XDifferential Inputs Positive ADC5 Negative ADC3 1x Gain52ADC5_ADC3_20XDifferential Inputs Positive ADC5 Negative ADC3 20x Gain53ADC5_ADC4_1XDifferential Inputs Positive ADC5 Negative ADC4 1x Gain58ADC5_ADC4_20XDifferential Inputs Positive ADC5 Negative ADC4 20x Gain59ADC5_ADC6_1XDifferential Inputs Positive ADC5 Negative ADC6 1x Gain28ADC5_ADC6_20XDifferential Inputs Positive ADC5 Negative ADC6 20x Gain29ADC6_ADC3_1XDifferential Inputs Positive ADC6 Negative ADC3 1x Gain54ADC6_ADC3_20XDifferential Inputs Positive ADC6 Negative ADC3 20x Gain55ADC6_ADC5_1XDifferential Inputs Positive ADC6 Negative ADC5 1x Gain60ADC6_ADC5_20XDifferential Inputs Positive ADC6 Negative ADC5 20x Gain61ADC6_ADC7_1XDifferential Inputs Positive ADC6 Negative ADC7 1x Gain30ADC6_ADC7_20XDifferential Inputs Positive ADC6 Negative ADC7 20x Gain31ADC7_ADC3_1XDifferential Inputs Positive ADC7 Negative ADC3 1x Gain56ADC7_ADC3_20XDifferential Inputs Positive ADC7 Negative ADC3 20x Gain57ADC7_ADC6_1XDifferential Inputs Positive ADC7 Negative ADC6 1x Gain62ADC7_ADC6_20XDifferential Inputs Positive ADC7 Negative ADC6 20x Gain63ADC7_ADC7_1XDifferential Inputs Positive ADC7 Negative ADC7 1x Gain38ADC7_ADC7_20XDifferential Inputs Positive ADC7 Negative ADC7 20x Gain39 + + REFSReference Selection Bits62read-writeREFSread-writeVCCVcc used as Voltage Reference, disconnected from Aref0AREFExternal Voltage Reference at AREF pin, Internal Voltage Reference turned off1INTERNALInternal 1.1V Voltage Reference2 + + + + DIDR0 + Digital Input Disable Register 0 + 0x0 + + + 0 + 255 + + + + + + + BOOT_LOAD + Bootloader + 0x57 + + + SPMCSR + Store Program Memory Control Register + 0x0 + read-only + + + SPMEN + Store Program Memory Enable + [0:0] + + + PGERS + Page Erase + [1:1] + + + PGWRT + Page Write + [2:2] + + + RFLB + Read fuse and lock bits + [3:3] + + + CTPB + Clear temporary page buffer + [4:4] + + + + + + + CPU + CPU Registers + 0x20 + + RESET + External Pin, Power-on Reset, Brown-out Reset,Watchdog Reset + 0 + + + EXT_INT0 + External Interrupt Request 0 + 1 + + + PCINT0 + Pin Change Interrupt Request 0 + 2 + + + PCINT1 + Pin Change Interrupt Request 1 + 3 + + + WDT + Watchdog Time-out + 4 + + + TIM1_CAPT + Timer/Counter1 Capture Event + 5 + + + TIM1_COMPA + Timer/Counter1 Compare Match A + 6 + + + TIM1_COMPB + Timer/Counter1 Compare Match B + 7 + + + TIM1_OVF + Timer/Counter1 Overflow + 8 + + + TIM0_COMPA + Timer/Counter0 Compare Match A + 9 + + + TIM0_COMPB + Timer/Counter0 Compare Match B + 10 + + + TIM0_OVF + Timer/Counter0 Overflow + 11 + + + ANA_COMP + Analog Comparator + 12 + + + ADC + ADC Conversion Complete + 13 + + + EE_RDY + EEPROM Ready + 14 + + + USI_STR + USI START + 15 + + + USI_OVF + USI Overflow + 16 + + + + CLKPR + Clock Prescale Register + 0x26 + + + CLKPS + Clock Prescaler Select Bits + [3:0] + + true + + CLKPSread-writePRESCALER_1Prescaler Value 10PRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287PRESCALER_256Prescaler Value 2568 + + + CLKPCE + Clock Prescaler Change Enable + [7:7] + + + + + GPIOR0 + General Purpose I/O Register 0 + 0x13 + + + 0 + 255 + + + + + GPIOR1 + General Purpose I/O Register 1 + 0x14 + + + 0 + 255 + + + + + GPIOR2 + General Purpose I/O Register 2 + 0x15 + + + 0 + 255 + + + + + MCUCR + MCU Control Register + 0x35 + + + SM + Sleep Mode Select Bits + [4:3] + + true + + + + IDLE + Idle + 0 + + + ADC + ADC Noise Reduction (If Available) + 1 + + + PDOWN + Power Down + 2 + + + STDBY + Standby + 3 + + + + + SE + Sleep Enable + [5:5] + + + PUD + Pull-up Disable + [6:6] + + BODSBOD Sleep (available on some devices)71read-write + BODSEBOD Sleep Enable (available on some devices)21read-write + + + + MCUSR + MCU Status Register + 0x34 + + + PORF + Power-on reset flag + [0:0] + + + EXTRF + External Reset Flag + [1:1] + + + BORF + Brown-out Reset Flag + [2:2] + + + WDRF + Watchdog Reset Flag + [3:3] + + + + + OSCCAL + Oscillator Calibration Value + 0x31 + read-write + + + OSCCAL + Oscillator Calibration + [7:0] + + + 0 + 255 + + + + + + + PRR + Power Reduction Register + 0x0 + + + PRADC + Power Reduction ADC + [0:0] + + + PRUSI + Power Reduction USI + [1:1] + + + PRTIM0 + Power Reduction Timer/Counter0 + [2:2] + + + PRTIM1 + Power Reduction Timer/Counter1 + [3:3] + + + + + + + EEPROM + EEPROM + 0x3C + + + EEAR + EEPROM Address Register Bytes + 0x2 + 16 + + + 0 + 65535 + + + + + EECR + EEPROM Control Register + 0x0 + + + EERE + EEPROM Read Enable + [0:0] + + + EEPE + EEPROM Write Enable + [1:1] + + + EEMPE + EEPROM Master Write Enable + [2:2] + + + EERIE + EEPROM Ready Interrupt Enable + [3:3] + + + EEPM + EEPROM Programming Mode Bits + [5:4] + + true + + EEPMread-writeATOMICAtomic (erase and write in one operation)0ERASEErase only1WRITEWrite only2 + + + + + EEDR + EEPROM Data Register + 0x1 + + + 0 + 255 + + + + + + + EXINT + External Interrupts + 0x32 + + + GIFR + General Interrupt Flag register + 0x28 + read-write + + + PCIF + Pin Change Interrupt Flags + [5:4] + + + 0 + 3 + + + + + INTF0 + External Interrupt Flag 0 + [6:6] + + + + + GIMSK + General Interrupt Mask Register + 0x29 + + + PCIE + Pin Change Interrupt Enables + [5:4] + + + 0 + 3 + + + + + INT0 + External Interrupt Request 0 Enable + [6:6] + + + + + MCUCR + MCU Control Register + 0x23 + + ISC0Interrupt Sense Control 0 bits02read-writeISC0read-writeLOWThe low level of INTx generates an interrupt request0TOGGLEAny logical change on INTx generates an interrupt request1FALLINGThe falling edge of INTx generates an interrupt request2RISINGThe rising edge of INTx generates an interrupt request3 + + + + + PCMSK0 + Pin Change Enable Mask 0 + 0x0 + + + 0 + 255 + + + + + PCMSK1 + Pin Change Enable Mask 1 + 0xE + + + 0 + 255 + + + + + + + FUSE + Fuses + 0x0 + + + EXTENDED + <TBD> + 0x2 + + + SELFPRGEN + Self Programming enable + [0:0] + + + + + HIGH + <TBD> + 0x1 + + + BODLEVEL + Brown-out Detector trigger level + [2:0] + + true + + + + 4V3 + Brown-out detection at VCC=4.3 V + 4 + + + 2V7 + Brown-out detection at VCC=2.7 V + 5 + + + 1V8 + Brown-out detection at VCC=1.8 V + 6 + + + DISABLED + Brown-out detection disabled + 7 + + + + + EESAVE + Preserve EEPROM through the Chip Erase cycle + [3:3] + + + WDTON + Watch-dog Timer always on + [4:4] + + + SPIEN + Serial program downloading (SPI) enabled + [5:5] + + + DWEN + Debug Wire enable + [6:6] + + + RSTDISBL + Reset Disabled (Enable PB3 as i/o pin) + [7:7] + + + + + LOW + <TBD> + 0x0 + + + SUT_CKSEL + Select Clock source + [5:0] + + true + + + + EXTCLK_6CK_14CK_0MS + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 0 + + + INTRCOSC_8MHZ_6CK_14CK_0MS + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 2 + + + WDOSC_128KHZ_6CK_14CK_0MS + WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 4 + + + EXTLOFXTAL_1KCK_14CK_0MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms + 6 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 8 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 9 + + + EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 10 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 11 + + + EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 12 + + + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 13 + + + EXTXOSC_8MHZ_XX_258CK_14CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 14 + + + EXTXOSC_8MHZ_XX_1KCK_14CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 15 + + + EXTCLK_6CK_14CK_4MS1 + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + 16 + + + INTRCOSC_8MHZ_6CK_14CK_4MS + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms + 18 + + + WDOSC_128KHZ_6CK_14CK_4MS + WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms + 20 + + + EXTLOFXTAL_1KCK_14CK_4MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms + 22 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 24 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 25 + + + EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 26 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 27 + + + EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 28 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 29 + + + EXTXOSC_8MHZ_XX_258CK_14CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 30 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 31 + + + EXTCLK_6CK_14CK_65MS + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + 32 + + + INTRCOSC_8MHZ_6CK_14CK_64MS_DEFAULT + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms; default value + 34 + + + WDOSC_128KHZ_6CK_14CK_64MS + WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms + 36 + + + EXTLOFXTAL_32KCK_14CK_64MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 64 ms + 38 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 40 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 41 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 42 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 43 + + + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 44 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 45 + + + EXTXOSC_8MHZ_XX_1KCK_14CK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 46 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 47 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 56 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 57 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 58 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 59 + + + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 60 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 61 + + + EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 62 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 63 + + + + + CKOUT + Clock output on PORTB2 + [6:6] + + + CKDIV8 + Divide clock by 8 internally + [7:7] + + + + + + + LOCKBIT + Lockbits + 0x0 + + + LOCKBIT + <TBD> + 0x0 + + + LB + Memory Lock + [1:0] + + true + + + + PROG_VER_DISABLED + Further programming and verification disabled + 0 + + + PROG_DISABLED + Further programming disabled + 2 + + + NO_LOCK + No memory lock features enabled + 3 + + + + + + + + + PORTA + I/O Port + 0x39 + + + DDRA + Port A Data Direction Register + 0x1 + + + 0 + 255 + + + + + PINA + Port A Input Pins + 0x0 + read-write + + + 0 + 255 + + + + + PORTA + Port A Data Register + 0x2 + + + 0 + 255 + + + + + + + PORTB + I/O Port + 0x36 + + + DDRB + Data Direction Register, Port B + 0x1 + + + 0 + 255 + + + + + PINB + Input Pins, Port B + 0x0 + read-write + + + 0 + 255 + + + + + PORTB + Data Register, Port B + 0x2 + + + 0 + 255 + + + + + + + TC0 + Timer/Counter0, 8-bit, PWM + 0x43 + + + GTCCR + General Timer/Counter Control Register + 0x0 + + + PSR10 + Prescaler Reset Timer/CounterN + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + OCR0A + Output Compare Register A + 0x13 + + + 0 + 255 + + + + + OCR0B + Output Compare Register B + 0x19 + + + 0 + 255 + + + + + TCCR0A + Timer/Counter Control Register A + 0xD + + + WGM0 + Waveform Generation Mode bits + [1:0] + + true + WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *BOTTOM*, Flag: *TOP*3 + + + COM0B + Compare Output B Mode + [5:4] + + true + COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM0A + Compare Output A Mode + [7:6] + + true + + + + + + TCCR0B + Timer/Counter Control Register B + 0x10 + + + CS0 + Clock Select bits + [2:0] + + true + + CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM02 + Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) + [3:3] + + + FOC0B + Force Output Compare B + [6:6] + write-only + + FOC0A + Force Output Compare A + [7:7] + write-only + + + + TCNT0 + Timer/Counter0 + 0xF + + + 0 + 255 + + + + + TIFR0 + Timer/Counter0 Interrupt Flag Register + 0x15 + read-only + + + TOV0 + Timer/Counter0 Overflow Flag + [0:0] + + + OCF0A + Timer/Counter0 Output Compare Flag A + [1:1] + + + OCF0B + Timer/Counter0 Output Compare Flag B + [2:2] + + + + + TIMSK0 + Timer/Counter Interrupt Mask Register + 0x16 + + + TOIE0 + Timer/Counter0 Overflow Interrupt Enable + [0:0] + + + OCIE0A + Timer/Counter0 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE0B + Timer/Counter0 Output Compare Match B Interrupt Enable + [2:2] + + + + + + + TC1 + Timer/Counter, 16-bit + 0x2B + + + ICR1 + Timer/Counter1 Input Capture Register Bytes + 0x19 + 16 + + + 0 + 65535 + + + + + OCR1A + Timer/Counter1 Output Compare Register A Bytes + 0x1F + 16 + + + 0 + 65535 + + + + + OCR1B + Timer/Counter1 Output Compare Register B Bytes + 0x1D + 16 + + + 0 + 65535 + + + + + TCCR1A + Timer/Counter1 Control Register A + 0x24 + + + WGM1 + Pulse Width Modulator Select Bits + [1:0] + + + 0 + 3 + + + + + COM1B + Compare Output Mode 1B, bits + [5:4] + + true + COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM1A + Compare Output Mode 1A, bits + [7:6] + + true + + + + + + TCCR1B + Timer/Counter1 Control Register B + 0x23 + + + CS1 + Clock Select1 bits + [2:0] + + true + CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM1 + Waveform Generation Mode Bits + [4:3] + + + 0 + 3 + + + + + ICES1 + Input Capture 1 Edge Select + [6:6] + + + ICNC1 + Input Capture 1 Noise Canceler + [7:7] + + + + + TCCR1C + Timer/Counter1 Control Register C + 0x17 + + + FOC1B + Force Output Compare for Channel B + [6:6] + write-only + + FOC1A + Force Output Compare for Channel A + [7:7] + write-only + + + + TCNT1 + Timer/Counter1 Bytes + 0x21 + 16 + + + 0 + 65535 + + + + + TIFR1 + Timer/Counter Interrupt Flag register + 0x0 + read-write + + + TOV1 + Timer/Counter1 Overflow Flag + [0:0] + + + OCF1A + Timer/Counter1 Output Compare A Match Flag + [1:1] + + + OCF1B + Timer/Counter1 Output Compare B Match Flag + [2:2] + + + ICF1 + Timer/Counter1 Input Capture Flag + [5:5] + + + + + TIMSK1 + Timer/Counter1 Interrupt Mask Register + 0x1 + + + TOIE1 + Timer/Counter1 Overflow Interrupt Enable + [0:0] + + + OCIE1A + Timer/Counter1 Output Compare A Match Interrupt Enable + [1:1] + + + OCIE1B + Timer/Counter1 Output Compare B Match Interrupt Enable + [2:2] + + + ICIE1 + Timer/Counter1 Input Capture Interrupt Enable + [5:5] + + + + + + + USI + Universal Serial Interface + 0x2D + + + USIBR + USI Buffer Register + 0x3 + read-only + + + 0 + 255 + + + + + USICR + USI Control Register + 0x0 + + + USITC + Toggle Clock Port Pin + [0:0] + write-only + + USICLK + Clock Strobe + [1:1] + write-only + + USICS + USI Clock Source Select Bits + [3:2] + + + 0 + 3 + + + USICSread-writeNO_CLOCKNo Clock/Software clock strobe0TC0Timer/Counter0 Compare Match1EXT_POSExternal, positive edge2EXT_NEGExternal, negative edge3 + + + USIWM + USI Wire Mode Bits + [5:4] + + true + + USIWMread-writeDISABLEDAll detectors disabled. Port pins operates as normal.0THREE_WIREThree-wire mode. Uses DO, DI, and USCK pins.1TWO_WIRE_SLAVETwo-wire mode (Slave). Uses SDA (DI) and SCL (USCK) pins.2TWO_WIRE_MASTERTwo-wire mode (Master). Uses SDA and SCL pins.3 + + + USIOIE + Counter Overflow Interrupt Enable + [6:6] + + + USISIE + Start Condition Interrupt Enable + [7:7] + + + + + USIDR + USI Data Register + 0x2 + + + 0 + 255 + + + + + USISR + USI Status Register + 0x1 + read-write + + + USICNT + USI Counter Value Bits + [3:0] + + + 0 + 15 + + + + + USIDC + Data Output Collision + [4:4] + read-only + + USIPF + Stop Condition Flag + [5:5] + + + USIOIF + Counter Overflow Interrupt Flag + [6:6] + + + USISIF + Start Condition Interrupt Flag + [7:7] + + + + + + + WDT + Watchdog Timer + 0x41 + + + WDTCSR + Watchdog Timer Control Register + 0x0 + read-write + + + WDE + Watch Dog Enable + [3:3] + + + WDCE + Watchdog Change Enable + [4:4] + + + WDIE + Watchdog Timeout Interrupt Enable + [6:6] + + + WDIF + Watchdog Timeout Interrupt Flag + [7:7] + + WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 + + WDPHWatchdog Timer Prescaler - High Bit[5:5] + + + + + + \ No newline at end of file diff --git a/misc/svd/attiny841.svd b/misc/svd/attiny841.svd new file mode 100644 index 0000000..ff35c22 --- /dev/null +++ b/misc/svd/attiny841.svd @@ -0,0 +1,3309 @@ + + Atmel + ATtiny841 + 8 + 8 + read-write + 0 + 0xff + + + AC + Analog Comparator + 0x2A + + + ACSR0A + Analog Comparator 0 Control And Status Register A + 0x0 + read-write + + ACIS0 + Analog Comparator Interrupt Mode Select + [1:0] + + true + + ACIS0read-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 + + + ACIC0 + Analog Comparator 0 Input Capture Enable + [2:2] + + + ACIE0 + Analog Comparator 0 Interrupt Enable + [3:3] + + + ACI0 + Analog Comparator 0 Interrupt Flag + [4:4] + + + ACO0 + Analog Comparator 0 Output + [5:5] + + + ACPMUX2 + Analog Comparator 0 Positive Input Multiplexer Bit 2 + [6:6] + + + ACD0 + Analog Comparator 0 Disable + [7:7] + + + + + ACSR0B + Analog Comparator 0 Control And Status Register B + 0x1 + + + ACPMUX + Analog Comparator 0 Positive Input Multiplexer Bits 1:0 + [1:0] + + + 0 + 3 + + + + + ACNMUX + Analog Comparator 0 Negative Input Multiplexer + [3:2] + + + 0 + 3 + + + + + ACOE0 + Analog Comparator 0 Output Pin Enable + [4:4] + + + HLEV0 + Analog Comparator 0 Hysteresis Level + [6:6] + + + HSEL0 + Analog Comparator 0 Hysteresis Select + [7:7] + + + + + ACSR1A + Analog Comparator 1 Control And Status Register A + 0x2 + read-write + + ACIS1 + Analog Comparator Interrupt Mode Select + [1:0] + + true + + ACIS1read-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 + + + ACIC1 + Analog Comparator 1 Input Capture Enable + [2:2] + + + ACIE1 + Analog Comparator 1 Interrupt Enable + [3:3] + + + ACI1 + Analog Comparator 1 Interrupt Flag + [4:4] + + + ACO1 + Analog Comparator 1 Output + [5:5] + + + ACBG1 + Analog Comparator 1 Bandgap Select + [6:6] + + + ACD1 + Analog Comparator 1 Disable + [7:7] + + + + + ACSR1B + Analog Comparator 1 Control And Status Register B + 0x3 + + + ACME1 + Analog Comparator 1 Multiplexer Enable + [2:2] + + + ACOE1 + Analog Comparator 1 Output Pin Enable + [4:4] + + + HLEV1 + Analog Comparator 1 Hysteresis Level + [6:6] + + + HSEL1 + Analog Comparator 1 Hysteresis Select + [7:7] + + + + + + + ADC + Analog-to-Digital Converter + 0x24 + + + ADC + ADC Data Register Bytes + 0x2 + 16 + + + 0 + 65535 + + + + + ADCSRA + The ADC Control and Status register + 0x1 + read-write + + + ADPS + ADC Prescaler Select Bits + [2:0] + + true + + ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 + + + ADIE + ADC Interrupt Enable + [3:3] + + + ADIF + ADC Interrupt Flag + [4:4] + + + ADATE + ADC Auto Trigger Enable + [5:5] + + + ADSC + ADC Start Conversion + [6:6] + + + ADEN + ADC Enable + [7:7] + + + + + ADCSRB + ADC Control and Status Register B + 0x0 + + + ADTS + ADC Auto Trigger Sources + [2:0] + + true + + + + VAL_0x00 + Free Running mode + 0 + + + VAL_0x01 + Analog Comparator 0 + 1 + + + VAL_0x02 + External Interrupt Request 0 + 2 + + + VAL_0x03 + Timer/Counter0 Compare Match A + 3 + + + VAL_0x04 + Timer/Counter0 Overflow + 4 + + + VAL_0x05 + Timer/Counter1 Compare Match A + 5 + + + VAL_0x06 + Timer/Counter1 Overflow + 6 + + + VAL_0x07 + Timer/Counter1 Capture Event + 7 + + + + + ADLAR + <TBD> + [3:3] + + + + + ADMUXA + The ADC multiplexer Selection Register A + 0x5 + + + MUX + Analog Channel and Gain Selection Bits + [5:0] + + + 0 + 63 + + + + + + + ADMUXB + The ADC multiplexer Selection Register B + 0x4 + + + GSEL + Gain Selection Bits + [1:0] + + + 0 + 3 + + + + + REFS + Reference Selection Bits + [7:5] + + + 0 + 7 + + + REFSread-writeVCCVcc0INTERNAL_1Internal 1.1V Voltage Reference with AREF disconnected1INTERNAL_2Internal 2.2V Voltage Reference with AREF disconnected2INTERNAL_4Internal 4.096V Voltage Reference with AREF disconnected3AREFAREF with internal reference off4AREF_INTERNAL_1Internal 1.1V Voltage Reference with external capacitor at AREF pin5AREF_INTERNAL_2Internal 2.2V Voltage Reference with external capacitor at AREF pin6AREF_INTERNAL_4Internal 4.096V Voltage Reference with external capacitor at AREF pin7 + + + + + DIDR0 + Digital Input Disable Register 0 + 0x3C + + + ADC0D + ADC0/AREF Digital input Disable + [0:0] + + + ADC1D + ADC1/AIN00 Digital input Disable + [1:1] + + + ADC2D + ADC2/AIN01 Digital input Disable + [2:2] + + + ADC3D + ADC3/AIN10 Digital Input Disable + [3:3] + + + ADC4D + ADC4/AIN11 Digital input Disable + [4:4] + + + ADC5D + ADC5 Digital input Disable + [5:5] + + + ADC6D + ADC6 Digital input Disable + [6:6] + + + ADC7D + ADC7 Digital input Disable + [7:7] + + + + + DIDR1 + Digital Input Disable Register 1 + 0x3D + + + ADC11D + ADC11 Digital input Disable + [0:0] + + + ADC10D + ADC10 Digital input Disable + [1:1] + + + ADC8D + ADC8 Digital input Disable + [2:2] + + + ADC9D + ADC9 Digital Input Disable + [3:3] + + + + + + + CPU + CPU Registers + 0x33 + + RESET + External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + 0 + + + INT0 + External Interrupt Request 0 + 1 + + + PCINT0 + Pin Change Interrupt Request 0 + 2 + + + PCINT1 + Pin Change Interrupt Request 1 + 3 + + + WDT + Watchdog Time-out Interrupt + 4 + + + TIMER1_CAPT + Timer/Counter1 Capture Event + 5 + + + TIMER1_COMPA + Timer/Counter1 Compare Match A + 6 + + + TIMER1_COMPB + Timer/Counter1 Compare Match B + 7 + + + TIMER1_OVF + Timer/Counter1 Overflow + 8 + + + TIMER0_COMPA + TimerCounter0 Compare Match A + 9 + + + TIMER0_COMPB + TimerCounter0 Compare Match B + 10 + + + TIMER0_OVF + Timer/Couner0 Overflow + 11 + + + ANA_COMP0 + Analog Comparator 0 + 12 + + + ADC + ADC Conversion Complete + 13 + + + EE_RDY + EEPROM Ready + 14 + + + ANA_COMP1 + Analog Comparator 1 + 15 + + + TIMER2_CAPT + Timer/Counter2 Capture Event + 16 + + + TIMER2_COMPA + Timer/Counter2 Compare Match A + 17 + + + TIMER2_COMPB + Timer/Counter2 Compare Match B + 18 + + + TIMER2_OVF + Timer/Counter2 Overflow + 19 + + + SPI + Serial Peripheral Interface + 20 + + + USART0_START + USART0, Start + 21 + + + USART0_RX + USART0, Rx Complete + 22 + + + USART0_UDRE + USART0 Data Register Empty + 23 + + + USART0_TX + USART0, Tx Complete + 24 + + + USART1_START + USART1, Start + 25 + + + USART1_RX + USART1, Rx Complete + 26 + + + USART1_UDRE + USART1 Data Register Empty + 27 + + + USART1_TX + USART1, Tx Complete + 28 + + + TWI_SLAVE + Two-wire Serial Interface + 29 + + + + CCP + Configuration Change Protection + 0x3E + + + 0 + 255 + + + + + CLKCR + Clock Control Register + 0x3F + + + CKSEL + Clock Select Bits + [3:0] + + + 0 + 15 + + + + + SUT + Start-up Time + [4:4] + + + CKOUTC + Clock Output (Copy). Active low. + [5:5] + + + CSTR + Clock Switch Trigger + [6:6] + + + OSCRDY + Oscillator Ready + [7:7] + + + + + CLKPR + Clock Prescale Register + 0x40 + + + CLKPS + Clock Prescaler Select Bits + [3:0] + + true + + + + VAL_0x00 + 1 + 0 + + + VAL_0x01 + 2 + 1 + + + VAL_0x02 + 4 + 2 + + + VAL_0x03 + 8 + 3 + + + VAL_0x04 + 16 + 4 + + + VAL_0x05 + 32 + 5 + + + VAL_0x06 + 64 + 6 + + + VAL_0x07 + 128 + 7 + + + VAL_0x08 + 256 + 8 + + + + + + + GPIOR0 + General Purpose I/O Register 0 + 0x0 + + + 0 + 255 + + + + + GPIOR1 + General Purpose I/O Register 1 + 0x1 + + + 0 + 255 + + + + + GPIOR2 + General Purpose I/O Register 2 + 0x2 + + + 0 + 255 + + + + + MCUCR + MCU Control Register + 0x22 + + + ISC0 + Interrupt Sense Control 0 bits + [1:0] + + + 0 + 3 + + + + + SM + Sleep Mode Select Bits + [4:3] + + true + + + + IDLE + Idle + 0 + + + ADC + ADC Noise Reduction (If Available) + 1 + + + PDOWN + Power Down + 2 + + + STDBY + Standby + 3 + + + + + SE + Sleep Enable + [5:5] + + + + + MCUSR + MCU Status Register + 0x21 + + + PORF + Power-on reset flag + [0:0] + + + EXTRF + External Reset Flag + [1:1] + + + BORF + Brown-out Reset Flag + [2:2] + + + WDRF + Watchdog Reset Flag + [3:3] + + + + + OSCCAL0 + Oscillator Calibration Register 8MHz + 0x41 + + + 0 + 255 + + + + + OSCCAL1 + Oscillator Calibration Register 32kHz + 0x44 + + + 0 + 255 + + + + + OSCTCAL0A + Oscillator Temperature Calibration Register A + 0x42 + + + 0 + 255 + + + + + OSCTCAL0B + Oscillator Temperature Calibration Register B + 0x43 + + + 0 + 255 + + + + + PRR + Power Reduction Register + 0x3D + + + PRADC + Power Reduction ADC + [0:0] + + + PRTIM0 + Power Reduction Timer/Counter0 + [1:1] + + + PRTIM1 + Power Reduction Timer/Counter1 + [2:2] + + + PRTIM2 + Power Reduction Timer/Counter2 + [3:3] + + + PRSPI + Power Reduction SPI + [4:4] + + + PRUSART0 + Power Reduction USART0 + [5:5] + + + PRUSART1 + Power Reduction USART1 + [6:6] + + + PRTWI + Power Reduction TWI + [7:7] + + + + + SPMCSR + Store Program Memory Control and Status Register + 0x24 + read-only + + + SPMEN + Store program Memory Enable + [0:0] + + + PGERS + Page Erase + [1:1] + + + PGWRT + Page Write + [2:2] + + + RFLB + Read Fuse and Lock Bits + [3:3] + + + CTPB + Clear Temporary Page Buffer + [4:4] + + + RSIG + Read Device Signature Imprint Table + [5:5] + + + + + + + EEPROM + EEPROM + 0x3C + + + EEAR + EEPROM Address Register Bytes + 0x2 + 16 + + + 0 + 65535 + + + + + EECR + EEPROM Control Register + 0x0 + + + EERE + EEPROM Read Enable + [0:0] + + + EEPE + EEPROM Write Enable + [1:1] + + + EEMPE + EEPROM Master Write Enable + [2:2] + + + EERIE + EEPROM Ready Interrupt Enable + [3:3] + + + EEPM + EEPROM Programming Mode Bits + [5:4] + + true + + + + VAL_0x00 + Erase and Write in one operation + 0 + + + VAL_0x01 + Erase Only + 1 + + + VAL_0x02 + Write Only + 2 + + + + + + + EEDR + EEPROM Data Register + 0x1 + + + 0 + 255 + + + + + + + EXINT + External Interrupts + 0x32 + + + GIFR + General Interrupt Flag register + 0x28 + read-only + + + PCIF + Pin Change Interrupt Flags + [5:4] + + + 0 + 3 + + + + + INTF0 + External Interrupt Flag 0 + [6:6] + + + + + GIMSK + General Interrupt Mask Register + 0x29 + + + PCIE + Pin Change Interrupt Enables + [5:4] + + + 0 + 3 + + + + + INT0 + External Interrupt Request 0 Enable + [6:6] + + + + + MCUCR + MCU Control Register + 0x23 + + + ISC00 + Interrupt Sense Control 0 Bit 0 + [0:0] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Reserved + 1 + + + + + ISC01 + Interrupt Sense Control 0 Bit 1 + [1:1] + + + + + PCMSK0 + Pin Change Enable Mask 0 + 0x0 + + + PCINT0 + Pin Change Enable Mask 0 Bit 0 + [0:0] + + + PCINT1 + Pin Change Enable Mask 0 Bit 1 + [1:1] + + + PCINT2 + Pin Change Enable Mask 0 Bit 2 + [2:2] + + + PCINT3 + Pin Change Enable Mask 0 Bit 3 + [3:3] + + + PCINT4 + Pin Change Enable Mask 0 Bit 4 + [4:4] + + + PCINT5 + Pin Change Enable Mask 0 Bit 5 + [5:5] + + + PCINT6 + Pin Change Enable Mask 0 Bit 6 + [6:6] + + + PCINT7 + Pin Change Enable Mask 0 Bit 7 + [7:7] + + + + + PCMSK1 + Pin Change Enable Mask 1 + 0xE + + + PCINT8 + Pin Change Enable Mask 1 Bit 0 + [0:0] + + + PCINT9 + Pin Change Enable Mask 1 Bit 1 + [1:1] + + + PCINT10 + Pin Change Enable Mask 1 Bit 2 + [2:2] + + + PCINT11 + Pin Change Enable Mask 1 Bit 3 + [3:3] + + + + + + + FUSE + Fuses + 0x0 + + + EXTENDED + <TBD> + 0x2 + + + SELFPRGEN + Self Programming enable + [0:0] + + + BODACT + BOD mode of operation when the device is active or idle + [2:1] + + true + + + + BOD_SAMPLED + Sampled + 1 + + + BOD_ENABLED + Enabled + 2 + + + BOD_DISABLED + Disabled + 3 + + + + + BODPD + BOD mode of operation when the device is in sleep mode + [4:3] + + true + + + + BOD_SAMPLED + Sampled + 1 + + + BOD_ENABLED + Enabled + 2 + + + BOD_DISABLED + Disabled + 3 + + + + + ULPOSCSEL + Frequency selection for internal ULP oscillator. The selection only affects system clock, watchdog and reset timeout always use 32 kHz clock. + [7:5] + + true + + + + ULPOSC_512KHZ + 512 kHz + 3 + + + ULPOSC_256KHZ + 256 kHz + 4 + + + ULPOSC_128KHZ + 128 kHz + 5 + + + ULPOSC_64KHZ + 64 kHz + 6 + + + ULPOSC_32KHZ + 32 kHz + 7 + + + + + + + HIGH + <TBD> + 0x1 + + + BODLEVEL + Brown-out Detector trigger level + [2:0] + + true + + + + 4V3 + Brown-out detection at VCC=4.3 V + 4 + + + 2V7 + Brown-out detection at VCC=2.7 V + 5 + + + 1V8 + Brown-out detection at VCC=1.8 V + 6 + + + + + EESAVE + Preserve EEPROM through the Chip Erase cycle + [3:3] + + + WDTON + Watch-dog Timer always on + [4:4] + + + SPIEN + Serial program downloading (SPI) enabled + [5:5] + + + DWEN + Debug Wire enable + [6:6] + + + RSTDISBL + Reset Disabled (Enable PC2 as i/o pin) + [7:7] + + + + + LOW + <TBD> + 0x0 + + + SUT_CKSEL + Select Clock Source + [4:0] + + true + + + + EXTCLK_6CK_16CK_16MS + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/16 CK + 16 ms + 0 + + + INTRCOSC_8MHZ_6CK_16CK_16MS + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/16 CK + 16 ms + 2 + + + INTULPOSC_32KHZ_6CK_16CK_16MS + Int. ULP Osc.; Start-up time PWRDWN/RESET: 6 CK/16 CK + 16 ms + 4 + + + EXTLOFXTAL_1KCK_16CK_16MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/16 CK + 16 ms + 6 + + + EXTCRES_0MHZ4_0MHZ9_258CK_16CK_16MS + Ext. Ceramic Res. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/16 CK + 16 ms + 8 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_16CK_16MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16 K CK/16 CK + 16 ms + 9 + + + EXTCRES_0MHZ9_3MHZ_258CK_16CK_16MS + Ext. Ceramic Res. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/16 CK + 16 ms + 10 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_16CK_16MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16 K CK/16 CK + 16 ms + 11 + + + EXTCRES_3MHZ_8MHZ_258CK_16CK_16MS + Ext. Ceramic Res. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/16 CK + 16 ms + 12 + + + EXTXOSC_3MHZ_8MHZ_16KCK_16CK_16MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16 K CK/16 CK + 16 ms + 13 + + + EXTCRES_8MHZ_XX_258CK_16CK_16MS + Ext. Ceramic Res. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/16 CK + 16 ms + 14 + + + EXTXOSC_8MHZ_XX_16KCK_16CK_16MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16 K CK/16 CK + 16 ms + 15 + + + EXTLOFXTAL_32KCK_14CK_16MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/16 CK + 16 ms + 22 + + + EXTCRES_0MHZ4_0MHZ9_1KCK_16CK_16MS + Ext. Ceramic Res. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK/16 CK + 16 ms + 24 + + + EXTCRES_0MHZ9_3MHZ_1KCK_16CK_16MS + Ext. Ceramic Res. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK/16 CK + 16 ms + 26 + + + EXTCRES_3MHZ_8MHZ_1KCK_16CK_16MS + Ext. Ceramic Res. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK/16 CK + 16 ms + 28 + + + EXTCRES_8MHZ_XX_1KCK_16CK_16MS + Ext. Ceramic Res. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK/16 CK + 16 ms + 30 + + + + + CKOUT + Clock output on PORTC2 + [6:6] + + + CKDIV8 + Divide clock by 8 internally + [7:7] + + + + + + + LOCKBIT + Lockbits + 0x0 + + + LOCKBIT + <TBD> + 0x0 + + + LB + Memory Lock + [1:0] + + true + + + + PROG_VER_DISABLED + Further programming and verification disabled + 0 + + + PROG_DISABLED + Further programming disabled + 2 + + + NO_LOCK + No memory lock features enabled + 3 + + + + + + + + + PORTA + I/O Port + 0x39 + + + DDRA + Data Direction Register, Port A + 0x1 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + PHDE + Port High Drive Enable Register + 0x31 + + + PHDEA + PortA High Drive Enable + [1:0] + + + 0 + 3 + + + + + + + PINA + Port A Input Pins + 0x0 + read-write + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + PORTA + Port A Data Register + 0x2 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + PORTCR + Port Control Register + 0x2B + + + BBMA + Break-Before-Make Mode Enable + [0:0] + + + + + PUEA + Pull-up Enable Control Register + 0x2A + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + + + PORTB + I/O Port + 0x36 + + + DDRB + Data Direction Register, Port B + 0x1 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + + + PINB + Port B Data register + 0x0 + read-write + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + + + PORTB + Input Pins, Port B + 0x2 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + + + PORTCR + Port Control Register + 0x2E + + + BBMB + Break-Before-Make Mode Enable + [1:1] + + + + + PUEB + Pull-up Enable Control Register + 0x2C + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + + + + + SPI + Serial Peripheral Interface + 0x65 + + + REMAP + Remap Port Pins + 0x0 + + + SPIMAP + SPI Pin Mapping + [1:1] + + + + + SPCR + SPI Control Register + 0x4D + + + SPR + SPI Clock Rate Selects + [1:0] + + true + + SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 + + + CPHA + Clock Phase + [2:2] + + + CPOL + Clock polarity + [3:3] + + + MSTR + Master/Slave Select + [4:4] + + + DORD + Data Order + [5:5] + + + SPE + SPI Enable + [6:6] + + + SPIE + SPI Interrupt Enable + [7:7] + + + + + SPDR + SPI Data Register + 0x4B + + + 0 + 255 + + + + + SPSR + SPI Status Register + 0x4C + read-write + + SPI2X + Double SPI Speed Bit + [0:0] + read-write + + WCOL + Write Collision Flag + [6:6] + read-only + + SPIF + SPI Interrupt Flag + [7:7] + read-only + + + + + + TC0 + Timer/Counter0, 8-bit, PWM + 0x43 + + + GTCCR + General Timer/Counter Control Register + 0x0 + + + PSR + Prescaler Reset Timer/CounterN + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + OCR0A + Output Compare Register A + 0x13 + + + 0 + 255 + + + + + OCR0B + Output Compare Register B + 0x19 + + + 0 + 255 + + + + + TCCR0A + Timer/Counter Control Register A + 0xD + + + WGM0 + Waveform Generation Mode bits + [1:0] + + true + WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *BOTTOM*, Flag: *TOP*3 + + + COM0B + Compare Output B Mode + [5:4] + + true + COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM0A + Compare Output A Mode + [7:6] + + true + + + + + + TCCR0B + Timer/Counter Control Register B + 0x10 + + + CS0 + Clock Select bits + [2:0] + + true + + CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM02 + Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) + [3:3] + + + FOC0B + Force Output Compare B + [6:6] + write-only + + FOC0A + Force Output Compare A + [7:7] + write-only + + + + TCNT0 + Timer/Counter0 + 0xF + + + 0 + 255 + + + + + TIFR0 + Timer/Counter0 Interrupt Flag Register + 0x15 + read-only + + + TOV0 + Timer/Counter0 Overflow Flag + [0:0] + + + OCF0A + Timer/Counter0 Output Compare Flag A + [1:1] + + + OCF0B + Timer/Counter0 Output Compare Flag B + [2:2] + + + + + TIMSK0 + Timer/Counter Interrupt Mask Register + 0x16 + + + TOIE0 + Timer/Counter0 Overflow Interrupt Enable + [0:0] + + + OCIE0A + Timer/Counter0 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE0B + Timer/Counter0 Output Compare Match B Interrupt Enable + [2:2] + + + + + + + TC1 + Timer/Counter1, 16-bit + 0x2E + + + GTCCR + General Timer/Counter Control Register + 0x15 + + + PSR + Prescaler Reset Timer/CounterN + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + ICR1 + Timer/Counter1 Input Capture Register Bytes + 0x16 + 16 + + + 0 + 65535 + + + + + OCR1A + Timer/Counter1 Output Compare Register A Bytes + 0x1C + 16 + + + 0 + 65535 + + + + + OCR1B + Timer/Counter1 Output Compare Register B Bytes + 0x1A + 16 + + + 0 + 65535 + + + + + TCCR1A + Timer/Counter1 Control Register A + 0x21 + + + WGM1 + Pulse Width Modulator Select Bits + [1:0] + + + 0 + 3 + + + + + COM1B + Compare Output Mode 1B, bits + [5:4] + + true + COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM1A + Compare Output Mode 1A, bits + [7:6] + + true + + + + + + TCCR1B + Timer/Counter1 Control Register B + 0x20 + + + CS1 + Clock Select bits + [2:0] + + true + CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM1 + Waveform Generation Mode Bits + [4:3] + + + 0 + 3 + + + + + ICES1 + Input Capture 1 Edge Select + [6:6] + + + ICNC1 + Input Capture 1 Noise Canceler + [7:7] + + + + + TCCR1C + Timer/Counter1 Control Register C + 0x14 + + + FOC1B + Force Output Compare for Channel B + [6:6] + write-only + + FOC1A + Force Output Compare for Channel A + [7:7] + write-only + + + + TCNT1 + Timer/Counter1 Bytes + 0x1E + 16 + + + 0 + 65535 + + + + + TIFR1 + Timer/Counter Interrupt Flag register + 0x0 + read-write + + + TOV1 + Timer/Counter1 Overflow Flag + [0:0] + + + OCF1A + Timer/Counter1 Output Compare A Match Flag + [1:1] + + + OCF1B + Timer/Counter1 Output Compare B Match Flag + [2:2] + + + ICF1 + Timer/Counter1 Input Capture Flag + [5:5] + + + + + TIMSK1 + Timer/Counter1 Interrupt Mask Register + 0x1 + + + TOIE1 + Timer/Counter1 Overflow Interrupt Enable + [0:0] + + + OCIE1A + Timer/Counter1 Output Compare A Match Interrupt Enable + [1:1] + + + OCIE1B + Timer/Counter1 Output Compare B Match Interrupt Enable + [2:2] + + + ICIE1 + Timer/Counter1 Input Capture Interrupt Enable + [5:5] + + + + + + + TC2 + Timer/Counter2, 16-bit + 0x30 + + + GTCCR + General Timer/Counter Control Register + 0x13 + + + PSR + Prescaler Reset Timer/CounterN + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + ICR2 + Timer/Counter2 Input Capture Register Bytes + 0x90 + 16 + + + 0 + 65535 + + + + + OCR2A + Timer/Counter2 Output Compare Register A Bytes + 0x94 + 16 + + + 0 + 65535 + + + + + OCR2B + Timer/Counter2 Output Compare Register B Bytes + 0x92 + 16 + + + 0 + 65535 + + + + + TCCR2A + Timer/Counter2 Control Register A + 0x9A + + + WGM2 + Pulse Width Modulator Select Bits + [1:0] + + + 0 + 3 + + + + + COM2B + Compare Output Mode 2B, bits + [5:4] + + true + COM2Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM2A + Compare Output Mode 2A, bits + [7:6] + + true + + + + + + TCCR2B + Timer/Counter2 Control Register B + 0x99 + + + CS2 + Clock Select bits + [2:0] + + true + CS2read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM2 + Waveform Generation Mode Bits + [4:3] + + + 0 + 3 + + + + + ICES2 + Input Capture 2 Edge Select + [6:6] + + + ICNC2 + Input Capture 2 Noise Canceler + [7:7] + + + + + TCCR2C + Timer/Counter2 Control Register C + 0x98 + + + FOC2B + Force Output Compare for Channel B + [6:6] + write-only + + FOC2A + Force Output Compare for Channel A + [7:7] + write-only + + + + TCNT2 + Timer/Counter2 Bytes + 0x96 + 16 + + + 0 + 65535 + + + + + TIFR2 + Timer/Counter Interrupt Flag register + 0x0 + read-write + + + TOV2 + Timer/Counter2 Overflow Flag + [0:0] + + + OCF2A + Timer/Counter2 Output Compare A Match Flag + [1:1] + + + OCF2B + Timer/Counter2 Output Compare B Match Flag + [2:2] + + + ICF2 + Timer/Counter2 Input Capture Flag + [5:5] + + + + + TIMSK2 + Timer/Counter2 Interrupt Mask Register + 0x1 + + + TOIE2 + Timer/Counter2 Overflow Interrupt Enable + [0:0] + + + OCIE2A + Timer/Counter2 Output Compare A Match Interrupt Enable + [1:1] + + + OCIE2B + Timer/Counter2 Output Compare B Match Interrupt Enable + [2:2] + + + ICIE2 + Timer/Counter2 Input Capture Interrupt Enable + [5:5] + + + + + + + TOCPM + Timer/Counter Output Compare Pin + 0x66 + + + TOCPMCOE + Timer Output Compare Pin Mux Channel Output Enable + 0x0 + + + TOCC0OE + Timer Output Compare Channel 0 Output Enable + [0:0] + + + TOCC1OE + Timer Output Compare Channel 1 Output Enable + [1:1] + + + TOCC2OE + Timer Output Compare Channel 2 Output Enable + [2:2] + + + TOCC3OE + Timer Output Compare Channel 3 Output Enable + [3:3] + + + TOCC4OE + Timer Output Compare Channel 4 Output Enable + [4:4] + + + TOCC5OE + Timer Output Compare Channel 5 Output Enable + [5:5] + + + TOCC6OE + Timer Output Compare Channel 6 Output Enable + [6:6] + + + TOCC7OE + Timer Output Compare Channel 7 Output Enable + [7:7] + + + + + TOCPMSA0 + Timer Output Compare Pin Mux Selection 0 + 0x1 + + + TOCC0S + Timer Output Compare Channel 0 Selection Bits + [1:0] + + + 0 + 3 + + + + + TOCC1S + Timer Output Compare Channel 1 Selection Bits + [3:2] + + + 0 + 3 + + + + + TOCC2S + Timer Output Compare Channel 2 Selection Bits + [5:4] + + + 0 + 3 + + + + + TOCC3S + Timer Output Compare Channel 3 Selection Bits + [7:6] + + + 0 + 3 + + + + + + + TOCPMSA1 + Timer Output Compare Pin Mux Selection 1 + 0x2 + + + TOCC4S + Timer Output Compare Channel 4 Selection Bits + [1:0] + + + 0 + 3 + + + + + TOCC5S + Timer Output Compare Channel 5 Selection Bits + [3:2] + + + 0 + 3 + + + + + TOCC6S + Timer Output Compare Channel 6 Selection Bits + [5:4] + + + 0 + 3 + + + + + TOCC7S + Timer Output Compare Channel 7 Selection Bits + [7:6] + + + 0 + 3 + + + + + + + + + TWI + Two Wire Serial Interface + 0xA0 + + + TWSA + TWI Slave Address Register + 0x2 + read-only + + + 0 + 255 + + + + + TWSAM + TWI Slave Address Mask Register + 0x1 + + + TWAE + TWI Address Enable + [0:0] + + + TWSAM + TWI Address Mask Bits + [7:1] + + + 0 + 127 + + + + + + + TWSCRA + TWI Slave Control Register A + 0x5 + + + TWSME + TWI Smart Mode Enable + [0:0] + + + TWPME + TWI Promiscuous Mode Enable + [1:1] + + + TWSIE + TWI Stop Interrupt Enable + [2:2] + + + TWEN + Two-Wire Interface Enable + [3:3] + + + TWASIE + TWI Address/Stop Interrupt Enable + [4:4] + + + TWDIE + TWI Data Interrupt Enable + [5:5] + + + TWSHE + TWI SDA Hold Time Enable + [7:7] + + + + + TWSCRB + TWI Slave Control Register B + 0x4 + + + TWCMD + <TBD> + [1:0] + + + 0 + 3 + + + + + TWAA + TWI Acknowledge Action + [2:2] + TWAAread-writeACK_WRITESend ACK when TWCMD is written as 10 or 110ACK_READSend ACK when TWSD is read1NACK_WRITESend NACK when TWCMD is written as 10 or 112NACK_READSend NACK when TWSD is read3 + + + TWHNM + TWI High Noise Mode + [3:3] + + + + + TWSD + TWI Slave Data Register + 0x0 + read-only + + + TWSD + TWI slave data bit + [7:0] + + + 0 + 255 + + + + + + + TWSSRA + TWI Slave Status Register A + 0x3 + + + TWAS + TWI Address or Stop + [0:0] + + + TWDIR + TWI Read/Write Direction + [1:1] + + + TWBE + TWI Bus Error + [2:2] + + + TWC + TWI Collision + [3:3] + + + TWRA + TWI Receive Acknowledge + [4:4] + + + TWCH + TWI Clock Hold + [5:5] + + + TWASIF + TWI Address/Stop Interrupt Flag + [6:6] + + + TWDIF + TWI Data Interrupt Flag. + [7:7] + + + + + + + USART0 + USART + 0x65 + + + REMAP + Remap Port Pins + 0x0 + + + U0MAP + USART0 Pin Mapping + [0:0] + + + + + UBRR0 + USART Baud Rate Register Bytes + 0x1C + 16 + + + 0 + 65535 + + + + + UCSR0A + USART Control and Status Register A + 0x21 + read-write + + + MPCM0 + Multi-processor Communication Mode + [0:0] + + + U2X0 + Double the USART transmission speed + [1:1] + + + UPE0 + Parity Error + [2:2] + read-only + + DOR0 + Data overRun + [3:3] + read-only + + FE0 + Framing Error + [4:4] + read-only + + UDRE0 + USART Data Register Empty + [5:5] + read-only + + TXC0 + USART Transmit Complete + [6:6] + + + RXC0 + USART Receive Complete + [7:7] + read-only + + + + UCSR0B + USART Control and Status Register B + 0x20 + + + TXB80 + Transmit Data Bit 8 + [0:0] + + + RXB80 + Receive Data Bit 8 + [1:1] + read-only + + UCSZ02 + Character Size + [2:2] + + + TXEN0 + Transmitter Enable + [3:3] + + + RXEN0 + Receiver Enable + [4:4] + + + UDRIE0 + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE0 + TX Complete Interrupt Enable + [6:6] + + + RXCIE0 + RX Complete Interrupt Enable + [7:7] + + + + + UCSR0C + USART Control and Status Register C + 0x1F + + + UCPOL0 + Clock Polarity + [0:0] + UCPOL0read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 + + + UCSZ0 + Character Size + [2:1] + + + 0 + 3 + + + UCSZ0read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 + + + USBS0 + Stop Bit Select + [3:3] + + true + + USBS0read-writeSTOP11-bit0STOP22-bit1 + + + UPM0 + Parity Mode Bits + [5:4] + + true + + UPM0read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 + + + UMSEL0 + USART Mode Select + [7:6] + + true + + UMSEL0read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 + + + + + UCSR0D + USART Control and Status Register D + 0x1E + + + SFDE0 + USART RX Start Frame Detection Enable + [5:5] + + + RXS0 + USART RX Start Flag + [6:6] + + + RXSIE0 + USART RX Start Interrupt Enable + [7:7] + + + + + UDR0 + USART I/O Data Register + 0x1B + + + 0 + 255 + + + + + + + USART1 + USART + 0x90 + + + UBRR1 + USART Baud Rate Register Bytes + 0x1 + 16 + + + 0 + 65535 + + + + + UCSR1A + USART Control and Status Register A + 0x6 + read-write + + + MPCM1 + Multi-processor Communication Mode + [0:0] + + + U2X1 + Double the USART transmission speed + [1:1] + + + UPE1 + Parity Error + [2:2] + read-only + + DOR1 + Data overRun + [3:3] + read-only + + FE1 + Framing Error + [4:4] + read-only + + UDRE1 + USART Data Register Empty + [5:5] + read-only + + TXC1 + USART Transmit Complete + [6:6] + + + RXC1 + USART Receive Complete + [7:7] + read-only + + + + UCSR1B + USART Control and Status Register B + 0x5 + + + TXB81 + Transmit Data Bit 8 + [0:0] + + + RXB81 + Receive Data Bit 8 + [1:1] + read-only + + UCSZ12 + Character Size + [2:2] + + + TXEN1 + Transmitter Enable + [3:3] + + + RXEN1 + Receiver Enable + [4:4] + + + UDRIE1 + USART Data register Empty Interrupt Enable + [5:5] + + + TXCIE1 + TX Complete Interrupt Enable + [6:6] + + + RXCIE1 + RX Complete Interrupt Enable + [7:7] + + + + + UCSR1C + USART Control and Status Register C + 0x4 + + + UCPOL1 + Clock Polarity + [0:0] + UCPOL1read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 + + + UCSZ1 + Character Size + [2:1] + + + 0 + 3 + + + UCSZ1read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 + + + USBS1 + Stop Bit Select + [3:3] + + true + + USBS1read-writeSTOP11-bit0STOP22-bit1 + + + UPM1 + Parity Mode Bits + [5:4] + + true + + UPM1read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 + + + UMSEL1 + USART Mode Select + [7:6] + + true + + UMSEL1read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 + + + + + UCSR1D + USART Control and Status Register D + 0x3 + + + SFDE1 + USART RX Start Frame Detection Enable + [5:5] + + + RXS1 + USART RX Start Flag + [6:6] + + + RXSIE1 + USART RX Start Interrupt Enable + [7:7] + + + + + UDR1 + USART I/O Data Register + 0x0 + + + 0 + 255 + + + + + + + WDT + Watchdog Timer + 0x41 + + + WDTCSR + Watchdog Timer Control and Status Register + 0x0 + read-write + + WDE + Watch Dog Enable + [3:3] + + + WDIE + Watchdog Timer Interrupt Enable + [6:6] + + + WDIF + Watchdog Timer Interrupt Flag + [7:7] + + WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 + + WDPHWatchdog Timer Prescaler - High Bit[5:5] + + + + + + \ No newline at end of file diff --git a/misc/svd/attiny85.svd b/misc/svd/attiny85.svd new file mode 100644 index 0000000..5dadaaf --- /dev/null +++ b/misc/svd/attiny85.svd @@ -0,0 +1,1792 @@ + + Atmel + ATtiny85 + 8 + 8 + read-write + 0 + 0xff + + + AC + Analog Comparator + 0x23 + + + ACSR + Analog Comparator Control And Status Register + 0x5 + read-write + + + ACIS + Analog Comparator Interrupt Mode Select + [1:0] + + true + + ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 + + + ACIE + Analog Comparator Interrupt Enable + [3:3] + + + ACI + Analog Comparator Interrupt Flag + [4:4] + + + ACO + Analog Compare Output + [5:5] + read-only + + ACBG + Analog Comparator Bandgap Select + [6:6] + + + ACD + Analog Comparator Disable + [7:7] + + + + + ADCSRB + ADC Control and Status Register B + 0x0 + + + ACME + Analog Comparator Multiplexer Enable + [6:6] + + + + + DIDR0 + Digital Input Disable Register 0 + 0x11 + + + AIN0D + AIN0 Digital Input Disable + [0:0] + + + AIN1D + AIN1 Digital Input Disable + [1:1] + + + + + + + ADC + Analog-to-Digital Converter + 0x23 + + + ADC + ADC Data Register Bytes + 0x1 + 16 + + + 0 + 65535 + + + + + ADCSRA + ADC Control and Status Register A + 0x3 + + + ADPS + ADC Prescaler Select Bits + [2:0] + + true + + ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 + + + ADIE + ADC Interrupt Enable + [3:3] + + + ADIF + ADC Interrupt Flag + [4:4] + + + ADATE + ADC Auto Trigger Enable + [5:5] + + + ADSC + ADC Start Conversion + [6:6] + + + ADEN + ADC Enable + [7:7] + + + + + ADCSRB + ADC Control and Status Register B + 0x0 + + + ADTS + ADC Auto Trigger Sources + [2:0] + + true + + ADTSread-writeFREEFree Running mode0ACAnalog Comparator1INT0External Interrupt Request 02TC0_CMATimer/Counter0 Compare Match A3TC0_OVFTimer/Counter0 Overflow4TC0_CMBTimer/Counter0 Compare Match B5PCIRPin Change Interrupt Request6 + + + IPR + Input Polarity Mode + [5:5] + + + BIN + Bipolar Input Mode + [7:7] + + + + + ADMUX + The ADC multiplexer Selection Register + 0x4 + + + MUX + Analog Channel and Gain Selection Bits + [3:0] + + true + MUXread-writeADC0Single-ended Input ADC00ADC1Single-ended Input ADC11ADC2Single-ended Input ADC22ADC3Single-ended Input ADC33ADC2_ADC2_1XDifferential Inputs Positive ADC2 Negative ADC2 1x Gain4ADC2_ADC2_20XDifferential Inputs Positive ADC2 Negative ADC2 20x Gain5ADC2_ADC3_1XDifferential Inputs Positive ADC2 Negative ADC3 1x Gain6ADC2_ADC3_20XDifferential Inputs Positive ADC2 Negative ADC3 20x Gain7ADC0_ADC0_1XDifferential Inputs Positive ADC0 Negative ADC0 1x Gain8ADC0_ADC0_20XDifferential Inputs Positive ADC0 Negative ADC0 20x Gain9ADC0_ADC1_1XDifferential Inputs Positive ADC0 Negative ADC1 1x Gain10ADC0_ADC1_20XDifferential Inputs Positive ADC0 Negative ADC1 20x Gain11ADC_VBGInternal Reference (VBG)12ADC_GND0V (GND)13TEMPSENSTemperature sensor15 + + + REFS2 + Reference Selection Bit 2 + [4:4] + + + ADLAR + Left Adjust Result + [5:5] + + + REFS + Reference Selection Bits + [7:6] + + true + REFSread-writeVCCVcc used as Voltage Reference, disconnected from Aref0AREFExternal Voltage Reference at AREF pin, Internal Voltage Reference turned off1INTERNALInternal Voltage Reference (1.1V when REFS2 is cleared, 2.56V when REFS2 is set) without external bypass2INTERNAL_BYPASSInternal 2.56V Voltage Reference with external bypass capacitor at AREF pin (REFS2 must be set)3 + + + + + DIDR0 + Digital Input Disable Register 0 + 0x11 + + + ADC1D + ADC1 Digital input Disable + [2:2] + + + ADC3D + ADC3 Digital input Disable + [3:3] + + + ADC2D + ADC2 Digital input Disable + [4:4] + + + ADC0D + ADC0 Digital input Disable + [5:5] + + + + + + + BOOT_LOAD + Bootloader + 0x57 + + + SPMCSR + Store Program Memory Control Register + 0x0 + read-only + + + SPMEN + Store Program Memory Enable + [0:0] + + + PGERS + Page Erase + [1:1] + + + PGWRT + Page Write + [2:2] + + + RFLB + Read fuse and lock bits + [3:3] + + + CTPB + Clear temporary page buffer + [4:4] + + + RSIG + Read Device Signature Imprint Table + [5:5] + + + + + + + CPU + CPU Registers + 0x31 + + RESET + External Pin, Power-on Reset, Brown-out Reset,Watchdog Reset + 0 + + + INT0 + External Interrupt 0 + 1 + + + PCINT0 + Pin change Interrupt Request 0 + 2 + + + TIMER1_COMPA + Timer/Counter1 Compare Match 1A + 3 + + + TIMER1_OVF + Timer/Counter1 Overflow + 4 + + + TIMER0_OVF + Timer/Counter0 Overflow + 5 + + + EE_RDY + EEPROM Ready + 6 + + + ANA_COMP + Analog comparator + 7 + + + ADC + ADC Conversion ready + 8 + + + TIMER1_COMPB + Timer/Counter1 Compare Match B + 9 + + + TIMER0_COMPA + Timer/Counter0 Compare Match A + 10 + + + TIMER0_COMPB + Timer/Counter0 Compare Match B + 11 + + + WDT + Watchdog Time-out + 12 + + + USI_START + USI START + 13 + + + USI_OVF + USI Overflow + 14 + + + + CLKPR + Clock Prescale Register + 0x15 + read-write + + + CLKPS + Clock Prescaler Select Bits + [3:0] + + true + + CLKPSread-writePRESCALER_1Prescaler Value 10PRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287PRESCALER_256Prescaler Value 2568 + + + CLKPCE + Clock Prescaler Change Enable + [7:7] + + + + + DWDR + debugWire data register + 0x11 + + + 0 + 255 + + + + + GPIOR0 + General purpose register 0 + 0x0 + + + 0 + 255 + + + + + GPIOR1 + General Purpose register 1 + 0x1 + + + 0 + 255 + + + + + GPIOR2 + General Purpose IO register 2 + 0x2 + + + 0 + 255 + + + + + MCUCR + MCU Control Register + 0x24 + + + SM + Sleep Mode Select Bits + [4:3] + + true + + + + IDLE + Idle + 0 + + + ADC + ADC Noise Reduction (If Available) + 1 + + + PDOWN + Power Down + 2 + + + VAL_0x03 + Reserved + 3 + + + + + SE + Sleep Enable + [5:5] + + + PUD + Pull-up Disable + [6:6] + + BODSBOD Sleep (available on some devices)71read-write + BODSEBOD Sleep Enable (available on some devices)21read-write + + + + MCUSR + MCU Status register + 0x23 + read-write + + + PORF + Power-On Reset Flag + [0:0] + + + EXTRF + External Reset Flag + [1:1] + + + BORF + Brown-out Reset Flag + [2:2] + + + WDRF + Watchdog Reset Flag + [3:3] + + + + + OSCCAL + Oscillator Calibration Register + 0x20 + read-write + + + OSCCAL + Oscillator Calibration + [7:0] + + + 0 + 255 + + + + + + + PLLCSR + PLL Control and status register + 0x16 + + + PLOCK + PLL Lock detector + [0:0] + read-only + + PLLE + PLL Enable + [1:1] + + + PCKE + PCK Enable + [2:2] + + + LSM + Low speed mode + [7:7] + + + + + PRR + Power Reduction Register + 0xF + + + PRADC + Power Reduction ADC + [0:0] + + + PRUSI + Power Reduction USI + [1:1] + + + PRTIM0 + Power Reduction Timer/Counter0 + [2:2] + + + PRTIM1 + Power Reduction Timer/Counter1 + [3:3] + + + + + + + EEPROM + EEPROM + 0x3C + + + EEAR + EEPROM Address Register Bytes + 0x2 + 16 + + + 0 + 65535 + + + + + EECR + EEPROM Control Register + 0x0 + + + EERE + EEPROM Read Enable + [0:0] + + + EEPE + EEPROM Write Enable + [1:1] + + + EEMPE + EEPROM Master Write Enable + [2:2] + + + EERIE + EEPROM Ready Interrupt Enable + [3:3] + + + EEPM + EEPROM Programming Mode Bits + [5:4] + + true + + EEPMread-writeATOMICAtomic (erase and write in one operation)0ERASEErase only1WRITEWrite only2 + + + + + EEDR + EEPROM Data Register + 0x1 + + + 0 + 255 + + + + + + + EXINT + External Interrupts + 0x35 + + + GIFR + General Interrupt Flag register + 0x25 + read-write + + + PCIF + Pin Change Interrupt Flag + [5:5] + + + INTF0 + External Interrupt Flag 0 + [6:6] + + + + + GIMSK + General Interrupt Mask Register + 0x26 + + + PCIE + Pin Change Interrupt Enable + [5:5] + + + INT0 + External Interrupt Request 0 Enable + [6:6] + + + + + MCUCR + MCU Control Register + 0x20 + + ISC0Interrupt Sense Control 0 bits02read-writeISC0read-writeLOWThe low level of INTx generates an interrupt request0TOGGLEAny logical change on INTx generates an interrupt request1FALLINGThe falling edge of INTx generates an interrupt request2RISINGThe rising edge of INTx generates an interrupt request3 + + + + + PCMSK + Pin Change Enable Mask + 0x0 + + + 0 + 255 + + + + + + + FUSE + Fuses + 0x0 + + + EXTENDED + <TBD> + 0x2 + + + SELFPRGEN + Self Programming enable + [0:0] + + + + + HIGH + <TBD> + 0x1 + + + BODLEVEL + Brown-out Detector trigger level + [2:0] + + true + + + + 4V3 + Brown-out detection at VCC=4.3 V + 4 + + + 2V7 + Brown-out detection at VCC=2.7 V + 5 + + + 1V8 + Brown-out detection at VCC=1.8 V + 6 + + + DISABLED + Brown-out detection disabled + 7 + + + + + EESAVE + Preserve EEPROM through the Chip Erase cycle + [3:3] + + + WDTON + Watch-dog Timer always on + [4:4] + + + SPIEN + Serial program downloading (SPI) enabled + [5:5] + + + DWEN + Debug Wire enable + [6:6] + + + RSTDISBL + Reset Disabled (Enable PB5 as i/o pin) + [7:7] + + + + + LOW + <TBD> + 0x0 + + + SUT_CKSEL + Select Clock source + [5:0] + + true + + + + EXTCLK_6CK_14CK_0MS + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 0 + + + PLLCLK_1KCK_14CK_4MS + PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms + 1 + + + INTRCOSC_8MHZ_6CK_14CK_0MS + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 2 + + + INTRCOSC_6MHZ4_6CK_14CK_64MS + ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms + 3 + + + WDOSC_128KHZ_6CK_14CK_0MS + WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 4 + + + EXTLOFXTAL_1KCK_14CK_0MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms + 6 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 8 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 9 + + + EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 10 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 11 + + + EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 12 + + + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 13 + + + EXTXOSC_8MHZ_XX_258CK_14CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 14 + + + EXTXOSC_8MHZ_XX_1KCK_14CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 15 + + + EXTCLK_6CK_14CK_4MS1 + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + 16 + + + PLLCLK_16KCK_14CK_4MS + PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4 ms + 17 + + + INTRCOSC_8MHZ_6CK_14CK_4MS + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms + 18 + + + WDOSC_128KHZ_6CK_14CK_4MS + WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms + 20 + + + EXTLOFXTAL_1KCK_14CK_4MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms + 22 + + + EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 24 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 25 + + + EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 26 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 27 + + + EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 28 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 29 + + + EXTXOSC_8MHZ_XX_258CK_14CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 30 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 31 + + + EXTCLK_6CK_14CK_65MS + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + 32 + + + PLLCLK_1KCK_14CK_64MS + PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 64 ms + 33 + + + INTRCOSC_8MHZ_6CK_14CK_64MS + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms + 34 + + + INTRCOSC_6MHZ4_6CK_14CK_4MS + ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms + 35 + + + WDOSC_128KHZ_6CK_14CK_64MS + WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms + 36 + + + EXTLOFXTAL_32KCK_14CK_64MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 64 ms + 38 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 40 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 41 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 42 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 43 + + + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 44 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 45 + + + EXTXOSC_8MHZ_XX_1KCK_14CK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 46 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 47 + + + PLLCLK_16KCK_14CK_64MS + PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 64 ms + 49 + + + INTRCOSC_6MHZ4_1CK_14CK_0MS + ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 1 CK/14 CK + 0 ms + 51 + + + EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 56 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 57 + + + EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 58 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 59 + + + EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 60 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 61 + + + EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 62 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 63 + + + + + CKOUT + Clock output on PORTB4 + [6:6] + + + CKDIV8 + Divide clock by 8 internally + [7:7] + + + + + + + LOCKBIT + Lockbits + 0x0 + + + LOCKBIT + <TBD> + 0x0 + + + LB + Memory Lock + [1:0] + + true + + + + PROG_VER_DISABLED + Further programming and verification disabled + 0 + + + PROG_DISABLED + Further programming disabled + 2 + + + NO_LOCK + No memory lock features enabled + 3 + + + + + + + + + PORTB + I/O Port + 0x36 + + + DDRB + Data Direction Register, Port B + 0x1 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + + + PINB + Input Pins, Port B + 0x0 + read-write + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + + + PORTB + Data Register, Port B + 0x2 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + + + + + TC0 + Timer/Counter0, 8-bit, PWM + 0x48 + + + GTCCR + General Timer/Counter Control Register + 0x4 + + + PSR0 + Prescaler Reset Timer/Counter1 and Timer/Counter0 + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + OCR0A + Output Compare Register A + 0x1 + + + 0 + 255 + + + + + OCR0B + Output Compare Register B + 0x0 + + + 0 + 255 + + + + + TCCR0A + Timer/Counter Control Register A + 0x2 + + + WGM0 + Waveform Generation Mode + [1:0] + + true + WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *BOTTOM*, Flag: *TOP*3 + + + COM0B + Compare Output B Mode + [5:4] + + true + COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM0A + Compare Output A Mode + [7:6] + + true + + + + + + TCCR0B + Timer/Counter Control Register B + 0xB + + + CS0 + Clock Select + [2:0] + + true + + CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM02 + Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) + [3:3] + + + FOC0B + Force Output Compare B + [6:6] + write-only + + FOC0A + Force Output Compare A + [7:7] + write-only + + + + TCNT0 + Timer/Counter0 + 0xA + + + 0 + 255 + + + + + TIFR + Timer/Counter0 Interrupt Flag register + 0x10 + + + TOV0 + Timer/Counter0 Overflow Flag + [1:1] + + + OCF0B + Timer/Counter0 Output Compare Flag 0B + [3:3] + + + OCF0A + Timer/Counter0 Output Compare Flag 0A + [4:4] + + + + + TIMSK + Timer/Counter Interrupt Mask Register + 0x11 + + + TOIE0 + Timer/Counter0 Overflow Interrupt Enable + [1:1] + + + OCIE0B + Timer/Counter0 Output Compare Match B Interrupt Enable + [3:3] + + + OCIE0A + Timer/Counter0 Output Compare Match A Interrupt Enable + [4:4] + + + + + + + TC1 + Timer/Counter1, 8-bit + 0x43 + + + DT1A + Dead Time Value Register A + 0x2 + + + DTVL + <TBD> + [3:0] + + + 0 + 15 + + + + + DTVH + <TBD> + [7:4] + + + 0 + 15 + + + + + + + DT1B + Dead Time Value Register B + 0x1 + + + DTVL + <TBD> + [3:0] + + + 0 + 15 + + + + + DTVH + <TBD> + [7:4] + + + 0 + 15 + + + + + + + DTPS + Dead time prescaler register + 0x0 + + + DTPS + <TBD> + [1:0] + + + 0 + 3 + + + DTPSread-writeDIRECTNo Prescaling0PRESCALE_2Division factor 21PRESCALE_4Division factor 42PRESCALE_8Division factor 83 + + + + + GTCCR + Timer counter control register + 0x9 + + + PSR1 + Prescaler Reset Timer/Counter1 + [1:1] + + + FOC1A + Force Output Compare 1A + [2:2] + write-only + + FOC1B + Force Output Compare Match 1B + [3:3] + write-only + + COM1B + Comparator B Output Mode + [5:4] + + + 0 + 3 + + + COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match1MATCH_CLEARClear OCix on Compare Match2MATCH_SETSet OCix on Compare Match3 + + + PWM1B + Pulse Width Modulator B Enable + [6:6] + + + + + OCR1A + Output Compare Register A + 0xB + + + 0 + 255 + + + + + OCR1B + Output Compare Register B + 0x8 + + + 0 + 255 + + + + + OCR1C + Output Compare Register C + 0xA + + + 0 + 255 + + + + + TCCR1 + Timer/Counter Control Register + 0xD + + + CS1 + Clock Select Bits + [3:0] + + true + + CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_2Running, CLK/22PRESCALE_4Running, CLK/43PRESCALE_8Running, CLK/84PRESCALE_16Running, CLK/165PRESCALE_32Running, CLK/326PRESCALE_64Running, CLK/647PRESCALE_128Running, CLK/1288PRESCALE_256Running, CLK/2569PRESCALE_512Running, CLK/51210PRESCALE_1024Running, CLK/102411PRESCALE_2048Running, CLK/204812PRESCALE_4096Running, CLK/409613PRESCALE_8192Running, CLK/819214PRESCALE_16384Running, CLK/1638415 + + + COM1A + Compare Output Mode, Bits + [5:4] + + true + + COM1Aread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match1MATCH_CLEARClear OCix on Compare Match2MATCH_SETSet OCix on Compare Match3 + + + PWM1A + Pulse Width Modulator Enable + [6:6] + + + CTC1 + Clear Timer/Counter on Compare Match + [7:7] + + + + + TCNT1 + Timer/Counter Register + 0xC + read-write + + + 0 + 255 + + + + + TIFR + Timer/Counter Interrupt Flag Register + 0x15 + + + TOV1 + Timer/Counter1 Overflow Flag + [2:2] + + + OCF1B + Timer/Counter1 Output Compare Flag 1B + [5:5] + + + OCF1A + Timer/Counter1 Output Compare Flag 1A + [6:6] + + + + + TIMSK + Timer/Counter Interrupt Mask Register + 0x16 + + + TOIE1 + Timer/Counter1 Overflow Interrupt Enable + [2:2] + + + OCIE1B + OCIE1A: Timer/Counter1 Output Compare B Interrupt Enable + [5:5] + + + OCIE1A + OCIE1A: Timer/Counter1 Output Compare Interrupt Enable + [6:6] + + + + + + + USI + Universal Serial Interface + 0x2D + + + USIBR + USI Buffer Register + 0x3 + read-only + + + 0 + 255 + + + + + USICR + USI Control Register + 0x0 + + + USITC + Toggle Clock Port Pin + [0:0] + write-only + + USICLK + Clock Strobe + [1:1] + write-only + + USICS + USI Clock Source Select Bits + [3:2] + + + 0 + 3 + + + USICSread-writeNO_CLOCKNo Clock/Software clock strobe0TC0Timer/Counter0 Compare Match1EXT_POSExternal, positive edge2EXT_NEGExternal, negative edge3 + + + USIWM + USI Wire Mode Bits + [5:4] + + true + + USIWMread-writeDISABLEDAll detectors disabled. Port pins operates as normal.0THREE_WIREThree-wire mode. Uses DO, DI, and USCK pins.1TWO_WIRE_SLAVETwo-wire mode (Slave). Uses SDA (DI) and SCL (USCK) pins.2TWO_WIRE_MASTERTwo-wire mode (Master). Uses SDA and SCL pins.3 + + + USIOIE + Counter Overflow Interrupt Enable + [6:6] + + + USISIE + Start Condition Interrupt Enable + [7:7] + + + + + USIDR + USI Data Register + 0x2 + + + 0 + 255 + + + + + USISR + USI Status Register + 0x1 + read-write + + + USICNT + USI Counter Value Bits + [3:0] + + + 0 + 15 + + + + + USIDC + Data Output Collision + [4:4] + read-only + + USIPF + Stop Condition Flag + [5:5] + + + USIOIF + Counter Overflow Interrupt Flag + [6:6] + + + USISIF + Start Condition Interrupt Flag + [7:7] + + + + + + + WDT + Watchdog Timer + 0x41 + + + WDTCR + Watchdog Timer Control Register + 0x0 + read-write + + + WDE + Watch Dog Enable + [3:3] + + + WDCE + Watchdog Change Enable + [4:4] + + + WDIE + Watchdog Timeout Interrupt Enable + [6:6] + + + WDIF + Watchdog Timeout Interrupt Flag + [7:7] + + WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 + + WDPHWatchdog Timer Prescaler - High Bit[5:5] + + + + + + \ No newline at end of file diff --git a/misc/svd/attiny861.svd b/misc/svd/attiny861.svd new file mode 100644 index 0000000..caa9add --- /dev/null +++ b/misc/svd/attiny861.svd @@ -0,0 +1,2354 @@ + + Atmel + ATtiny861 + 8 + 8 + read-write + 0 + 0xff + + + AC + Analog Comparator + 0x28 + + + ACSRA + Analog Comparator Control And Status Register A + 0x0 + read-write + + ACIS + Analog Comparator Interrupt Mode Select + [1:0] + + true + + ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 + + + ACME + Analog Comparator Multiplexer Enable + [2:2] + + + ACIE + Analog Comparator Interrupt Enable + [3:3] + + + ACI + Analog Comparator Interrupt Flag + [4:4] + + + ACO + Analog Compare Output + [5:5] + read-only + + ACBG + Analog Comparator Bandgap Select + [6:6] + + + ACD + Analog Comparator Disable + [7:7] + + + + + ACSRB + Analog Comparator Control And Status Register B + 0x1 + + + ACM + Analog Comparator Multiplexer + [2:0] + + + 0 + 7 + + + + + HLEV + Hysteresis Level + [6:6] + + + HSEL + Hysteresis Select + [7:7] + + + + + + + ADC + Analog-to-Digital Converter + 0x21 + + + ADC + ADC Data Register Bytes + 0x3 + 16 + + + 0 + 65535 + + + + + ADCSRA + The ADC Control and Status register + 0x5 + read-write + + + ADPS + ADC Prescaler Select Bits + [2:0] + + true + + ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 + + + ADIE + ADC Interrupt Enable + [3:3] + + + ADIF + ADC Interrupt Flag + [4:4] + + + ADATE + ADC Auto Trigger Enable + [5:5] + + + ADSC + ADC Start Conversion + [6:6] + + + ADEN + ADC Enable + [7:7] + + + + + ADCSRB + ADC Control and Status Register B + 0x2 + + + ADTS + ADC Auto Trigger Sources + [2:0] + + true + + + + VAL_0x00 + Free Running mode + 0 + + + VAL_0x01 + Analog Comparator + 1 + + + VAL_0x02 + External Interrupt Request 0 + 2 + + + VAL_0x03 + Timer/Counter0 Compare Match A + 3 + + + VAL_0x04 + Timer/Counter0 Overflow + 4 + + + VAL_0x05 + Timer/Counter1 Compare Match B + 5 + + + VAL_0x06 + Timer/Counter1 Overflow + 6 + + + VAL_0x07 + Watchdog Interrupt Request + 7 + + + + + MUX5 + Analog Channel and Gain Selection Bit 5 + [3:3] + + + REFS2 + Reference Selection Bit + [4:4] + + + IPR + Input Polarity Mode + [5:5] + + + GSEL + Gain Select + [6:6] + + + BIN + Bipolar Input Mode + [7:7] + + + + + ADMUX + The ADC multiplexer Selection Register + 0x6 + + + MUX + Analog Channel and Gain Selection Bits + [4:0] + + + 0 + 31 + + + + + ADLAR + Left Adjust Result + [5:5] + + + REFS + Reference Selection Bits + [7:6] + + + 0 + 3 + + + REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 + + + + + DIDR0 + Digital Input Disable Register 0 + 0x0 + + + ADC0D + ADC0 Digital input Disable + [0:0] + + + ADC1D + ADC1 Digital input Disable + [1:1] + + + ADC2D + ADC2 Digital input Disable + [2:2] + + + AREFD + AREF Digital Input Disable + [3:3] + + + ADC3D + ADC3 Digital input Disable + [4:4] + + + ADC4D + ADC4 Digital input Disable + [5:5] + + + ADC5D + ADC5 Digital input Disable + [6:6] + + + ADC6D + ADC6 Digital input Disable + [7:7] + + + + + DIDR1 + Digital Input Disable Register 1 + 0x1 + + + ADC7D + ADC7 Digital input Disable + [4:4] + + + ADC8D + ADC8 Digital input Disable + [5:5] + + + ADC9D + ADC9 Digital input Disable + [6:6] + + + ADC10D + ADC10 Digital input Disable + [7:7] + + + + + + + BOOT_LOAD + Bootloader + 0x57 + + + SPMCSR + Store Program Memory Control Register + 0x0 + read-only + + + SPMEN + Store Program Memory Enable + [0:0] + + + PGERS + Page Erase + [1:1] + + + PGWRT + Page Write + [2:2] + + + RFLB + Read fuse and lock bits + [3:3] + + + CTPB + Clear temporary page buffer + [4:4] + + + + + + + CPU + CPU Registers + 0x2A + + RESET + External Reset, Power-on Reset and Watchdog Reset + 0 + + + INT0 + External Interrupt 0 + 1 + + + PCINT + Pin Change Interrupt + 2 + + + TIMER1_COMPA + Timer/Counter1 Compare Match 1A + 3 + + + TIMER1_COMPB + Timer/Counter1 Compare Match 1B + 4 + + + TIMER1_OVF + Timer/Counter1 Overflow + 5 + + + TIMER0_OVF + Timer/Counter0 Overflow + 6 + + + USI_START + USI Start + 7 + + + USI_OVF + USI Overflow + 8 + + + EE_RDY + EEPROM Ready + 9 + + + ANA_COMP + Analog Comparator + 10 + + + ADC + ADC Conversion Complete + 11 + + + WDT + Watchdog Time-Out + 12 + + + INT1 + External Interrupt 1 + 13 + + + TIMER0_COMPA + Timer/Counter0 Compare Match A + 14 + + + TIMER0_COMPB + Timer/Counter0 Compare Match B + 15 + + + TIMER0_CAPT + ADC Conversion Complete + 16 + + + TIMER1_COMPD + Timer/Counter1 Compare Match D + 17 + + + FAULT_PROTECTION + Timer/Counter1 Fault Protection + 18 + + + + CLKPR + Clock Prescale Register + 0x1E + read-only + + + CLKPS + Clock Prescaler Select Bits + [3:0] + + true + + + + VAL_0x00 + 1 + 0 + + + VAL_0x01 + 2 + 1 + + + VAL_0x02 + 4 + 2 + + + VAL_0x03 + 8 + 3 + + + VAL_0x04 + 16 + 4 + + + VAL_0x05 + 32 + 5 + + + VAL_0x06 + 64 + 6 + + + VAL_0x07 + 128 + 7 + + + VAL_0x08 + 256 + 8 + + + + + CLKPCE + Clock Prescaler Change Enable + [7:7] + + + + + DWDR + debugWire data register + 0x16 + + + 0 + 255 + + + + + GPIOR0 + General purpose register 0 + 0x0 + + + 0 + 255 + + + + + GPIOR1 + General Purpose register 1 + 0x1 + + + 0 + 255 + + + + + GPIOR2 + General Purpose IO register 2 + 0x2 + + + 0 + 255 + + + + + MCUCR + MCU Control Register + 0x2B + + + ISC0 + Interrupt Sense Control 0 bits + [1:0] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change in INTX + 1 + + + VAL_0x02 + Falling Edge of INTX + 2 + + + VAL_0x03 + Rising Edge of INTX + 3 + + + + + SM + Sleep Mode Select Bits + [4:3] + + true + + + + IDLE + Idle + 0 + + + ADC + ADC Noise Reduction (If Available) + 1 + + + PDOWN + Power Down + 2 + + + STDBY + Standby + 3 + + + + + SE + Sleep Enable + [5:5] + + + PUD + Pull-up Disable + [6:6] + + + + + MCUSR + MCU Status register + 0x2A + + + PORF + Power-On Reset Flag + [0:0] + + + EXTRF + External Reset Flag + [1:1] + + + BORF + Brown-out Reset Flag + [2:2] + + + WDRF + Watchdog Reset Flag + [3:3] + + + + + OSCCAL + Oscillator Calibration Register + 0x27 + read-only + + + OSCCAL + Oscillator Calibration + [7:0] + + + 0 + 255 + + + + + + + PLLCSR + PLL Control and status register + 0x1F + + + PLOCK + PLL Lock detector + [0:0] + + + PLLE + PLL Enable + [1:1] + + + PCKE + PCK Enable + [2:2] + + + LSM + Low speed mode + [7:7] + + + + + PRR + Power Reduction Register + 0x2C + + + PRADC + Power Reduction ADC + [0:0] + + + PRUSI + Power Reduction USI + [1:1] + + + PRTIM0 + Power Reduction Timer/Counter0 + [2:2] + + + PRTIM1 + Power Reduction Timer/Counter1 + [3:3] + + + + + + + EEPROM + EEPROM + 0x3C + + + EEAR + EEPROM Address Register Bytes + 0x2 + 16 + + + 0 + 65535 + + + + + EECR + EEPROM Control Register + 0x0 + + + EERE + EEPROM Read Enable + [0:0] + + + EEPE + EEPROM Write Enable + [1:1] + + + EEMPE + EEPROM Master Write Enable + [2:2] + + + EERIE + EEPROM Ready Interrupt Enable + [3:3] + + + EEPM + EEPROM Programming Mode Bits + [5:4] + + true + + + + VAL_0x00 + Erase and Write in one operation + 0 + + + VAL_0x01 + Erase Only + 1 + + + VAL_0x02 + Write Only + 2 + + + + + + + EEDR + EEPROM Data Register + 0x1 + + + 0 + 255 + + + + + + + EXINT + External Interrupts + 0x42 + + + GIFR + General Interrupt Flag register + 0x18 + read-only + + + PCIF + Pin Change Interrupt Flag + [5:5] + + + INTF + External Interrupt Flags + [7:6] + + + 0 + 3 + + + + + + + GIMSK + General Interrupt Mask Register + 0x19 + + + PCIE + Pin Change Interrupt Enables + [5:4] + + + 0 + 3 + + + + + INT + External Interrupt Request 1 Enable + [7:6] + + + 0 + 3 + + + + + + + MCUCR + MCU Control Register + 0x13 + + + ISC00 + Interrupt Sense Control 0 Bit 0 + [0:0] + + true + + + + VAL_0x00 + Low Level of INTX + 0 + + + VAL_0x01 + Any Logical Change of INTX + 1 + + + + + ISC01 + Interrupt Sense Control 0 Bit 1 + [1:1] + + + + + PCMSK0 + Pin Change Enable Mask 0 + 0x1 + + + 0 + 255 + + + + + PCMSK1 + Pin Change Enable Mask 1 + 0x0 + + + 0 + 255 + + + + + + + FUSE + Fuses + 0x0 + + + EXTENDED + <TBD> + 0x2 + + + SELFPRGEN + Self Programming enable + [0:0] + + + + + HIGH + <TBD> + 0x1 + + + BODLEVEL + Brown-out Detector trigger level + [2:0] + + true + + + + 2V0 + Brown-out detection at VCC=2.0 V + 0 + + + 1V9 + Brown-out detection at VCC=1.9 V + 1 + + + 2V2 + Brown-out detection at VCC=2.2 V + 2 + + + 2V3 + Brown-out detection at VCC=2.3 V + 3 + + + 4V3 + Brown-out detection at VCC=4.3 V + 4 + + + 2V7 + Brown-out detection at VCC=2.7 V + 5 + + + 1V8 + Brown-out detection at VCC=1.8 V + 6 + + + DISABLED + Brown-out detection disabled + 7 + + + + + EESAVE + Preserve EEPROM through the Chip Erase cycle + [3:3] + + + WDTON + Watch-dog Timer always on + [4:4] + + + SPIEN + Serial program downloading (SPI) enabled + [5:5] + + + DWEN + Debug Wire enable + [6:6] + + + RSTDISBL + Reset Disabled (Enable PB7 as i/o pin) + [7:7] + + + + + LOW + <TBD> + 0x0 + + + SUT_CKSEL + Select Clock source + [5:0] + + true + + + + EXTCLK_6CK_14CK_0MS + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 0 + + + PLLCLK_1KCK_14CK_8MS + PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 8 ms + 1 + + + INTRCOSC_8MHZ_6CK_14CK_0MS + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 2 + + + WDOSC_128KHZ_6CK_14CK_0MS + WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 3 + + + EXTLOFXTAL_1CK_4MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1 CK 4 ms + 4 + + + EXTCRES_0MHZ4_0MHZ9_258CK_14CK_4MS1 + Ext. Ceramic Res. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 8 + + + EXTCRES_0MHZ4_0MHZ9_1KCK_14CK_65MS + Ext. Ceramic Res. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 9 + + + EXTCRES_0MHZ9_3MHZ_258CK_14CK_4MS1 + Ext. Ceramic Res. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 10 + + + EXTCRES_0MHZ9_3MHZ_1KCK_14CK_65MS + Ext. Ceramic Res. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 11 + + + EXTCRES_3MHZ_8MHZ_258CK_14CK_4MS1 + Ext. Ceramic Res. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 12 + + + EXTCRES_3MHZ_8MHZ_1KCK_14CK_65MS + Ext. Ceramic Res. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 13 + + + EXTCRES_8MHZ_XX_258CK_14CK_4MS1 + Ext. Ceramic Res. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms + 14 + + + EXTCRES_8MHZ_XX_1KCK_14CK_65MS + Ext. Ceramic Res. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms + 15 + + + EXTCLK_6CK_14CK_4MS + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms + 16 + + + PLLCLK_16KCK_14CK_8MS + PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 8 ms + 17 + + + INTRCOSC_8MHZ_6CK_14CK_4MS + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms + 18 + + + WDOSC_128KHZ_6CK_14CK_4MS + WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms + 19 + + + EXTLOFXTAL_1CK_64MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1 CK + 64 ms + 20 + + + EXTCRES_0MHZ4_0MHZ9_258CK_14CK_65MS + Ext. Ceramic Res. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 24 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 25 + + + EXTCRES_0MHZ9_3MHZ_258CK_14CK_65MS + Ext. Ceramic Res. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 26 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 27 + + + EXTCRES_3MHZ_8MHZ_258CK_14CK_65MS + Ext. Ceramic Res. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 28 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 29 + + + EXTCRES_8MHZ_XX_258CK_14CK_65MS + Ext. Ceramic Res. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms + 30 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_0MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms + 31 + + + EXTCLK_6CK_14CK_64MS + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms + 32 + + + PLLCLK_1KCK_14CK_68MS + PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 68 ms + 33 + + + INTRCOSC_8MHZ_6CK_14CK_64MS + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms + 34 + + + WDOSC_128KHZ_6CK_14CK_64MS + WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms + 35 + + + EXTLOFXTAL_32CK_64MS + Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32 CK + 64 ms + 36 + + + EXTCRES_0MHZ4_0MHZ9_1KCK_14CK_0MS + Ext. Ceramic Res. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 40 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 41 + + + EXTCRES_0MHZ9_3MHZ_1KCK_14CK_0MS + Ext. Ceramic Res. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 42 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 43 + + + EXTCRES_3MHZ_8MHZ_1KCK_14CK_0MS + Ext. Ceramic Res. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 44 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 45 + + + EXTCRES_8MHZ_XX_1KCK_14CK_0MS + Ext. Ceramic Res. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms + 46 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms + 47 + + + PLLCLK_16KCK_14CK_68MS + PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 68 ms + 49 + + + EXTCRES_0MHZ4_0MHZ9_1KCK_14CK_4MS1 + Ext. Ceramic Res. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 56 + + + EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS + Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 57 + + + EXTCRES_0MHZ9_3MHZ_1KCK_14CK_4MS1 + Ext. Ceramic Res. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 58 + + + EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS + Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 59 + + + EXTCRES_3MHZ_8MHZ_1KCK_14CK_4MS1 + Ext. Ceramic Res. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 60 + + + EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS + Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 61 + + + EXTCRES_8MHZ_XX_1KCK_14CK_4MS1 + Ext. Ceramic Res. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms + 62 + + + EXTXOSC_8MHZ_XX_16KCK_14CK_65MS + Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms + 63 + + + + + CKOUT + Clock output on PORTB5 + [6:6] + + + CKDIV8 + Divide clock by 8 internally + [7:7] + + + + + + + LOCKBIT + Lockbits + 0x0 + + + LOCKBIT + <TBD> + 0x0 + + + LB + Memory Lock + [1:0] + + true + + + + PROG_VER_DISABLED + Further programming and verification disabled + 0 + + + PROG_DISABLED + Further programming disabled + 2 + + + NO_LOCK + No memory lock features enabled + 3 + + + + + + + + + PORTA + I/O Port + 0x39 + + + DDRA + Port A Data Direction Register + 0x1 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + PINA + Port A Input Pins + 0x0 + read-write + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + PORTA + Port A Data Register + 0x2 + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + PA4 + Pin A4 + [4:4] + + + PA5 + Pin A5 + [5:5] + + + PA6 + Pin A6 + [6:6] + + + PA7 + Pin A7 + [7:7] + + + + + + + PORTB + I/O Port + 0x36 + + + DDRB + Port B Data Direction Register + 0x1 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PINB + Port B Input Pins + 0x0 + read-write + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PORTB + Port B Data Register + 0x2 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + + + TC0 + Timer/Counter0 + 0x32 + + + OCR0A + Timer/Counter0 Output Compare Register + 0x1 + + + 0 + 255 + + + + + OCR0B + Timer/Counter0 Output Compare Register + 0x0 + + + 0 + 255 + + + + + TCCR0A + Timer/Counter Control Register A + 0x3 + + + WGM00 + Waveform Generation Mode + [0:0] + + + ACIC0 + Analog Comparator Input Capture Enable + [3:3] + + + ICES0 + Input Capture Edge Select + [4:4] + + + ICNC0 + Input Capture Noice Canceler + [5:5] + + + ICEN0 + Input Capture Mode Enable + [6:6] + + + TCW0 + Timer/Counter 0 Width + [7:7] + + + + + TCCR0B + Timer/Counter Control Register B + 0x21 + + + CS0 + Clock Select + [2:0] + + true + CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + PSR0 + Timer/Counter 0 Prescaler Reset + [3:3] + + + TSM + Timer/Counter Synchronization Mode + [4:4] + + + + + TCNT0H + Timer/Counter0 High + 0x2 + + + 0 + 255 + + + + + TCNT0L + Timer/Counter0 Low + 0x20 + + + 0 + 255 + + + + + TIFR + Timer/Counter0 Interrupt Flag register + 0x26 + read-only + + + ICF0 + Timer/Counter0 Input Capture Flag + [0:0] + + + TOV0 + Timer/Counter0 Overflow Flag + [1:1] + + + OCF0B + Timer/Counter0 Output Compare Flag 0B + [3:3] + + + OCF0A + Timer/Counter0 Output Compare Flag 0A + [4:4] + + + + + TIMSK + Timer/Counter Interrupt Mask Register + 0x27 + + + TICIE0 + Timer/Counter0 Input Capture Interrupt Enable + [0:0] + + + TOIE0 + Timer/Counter0 Overflow Interrupt Enable + [1:1] + + + OCIE0B + Timer/Counter0 Output Compare Match B Interrupt Enable + [3:3] + + + OCIE0A + Timer/Counter0 Output Compare Match A Interrupt Enable + [4:4] + + + + + + + TC1 + Timer/Counter1, 10-bit + 0x20 + + + DT1 + Timer/Counter 1 Dead Time Value + 0x24 + + + DT1L + <TBD> + [3:0] + + + 0 + 15 + + + + + DT1H + <TBD> + [7:4] + + + 0 + 15 + + + + + + + OCR1A + Output Compare Register + 0x2D + + + 0 + 255 + + + + + OCR1B + Output Compare Register + 0x2C + + + 0 + 255 + + + + + OCR1C + Output compare register + 0x2B + + + 0 + 255 + + + + + OCR1D + Output compare register + 0x2A + read-only + + + 0 + 255 + + + + + TC1H + Timer/Counter High Bits + 0x25 + + + 0 + 255 + + + + + TCCR1A + Timer/Counter Control Register A + 0x30 + + + PWM1B + Pulse Width Modulator Enable + [0:0] + + + PWM1A + Pulse Width Modulator Enable + [1:1] + + + FOC1B + Force Output Compare Match 1B + [2:2] + write-only + + FOC1A + Force Output Compare Match 1A + [3:3] + write-only + + COM1B + Compare Output Mode, Bits + [5:4] + + true + COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 + + + COM1A + Compare Output Mode, Bits + [7:6] + + true + + + + + + TCCR1B + Timer/Counter Control Register B + 0x2F + + + CS1 + Clock Select Bits + [3:0] + + true + CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_2Running, CLK/22PRESCALE_4Running, CLK/43PRESCALE_8Running, CLK/84PRESCALE_16Running, CLK/165PRESCALE_32Running, CLK/326PRESCALE_64Running, CLK/647PRESCALE_128Running, CLK/1288PRESCALE_256Running, CLK/2569PRESCALE_512Running, CLK/51210PRESCALE_1024Running, CLK/102411PRESCALE_2048Running, CLK/204812PRESCALE_4096Running, CLK/409613PRESCALE_8192Running, CLK/819214PRESCALE_16384Running, CLK/1638415 + + + DTPS1 + Dead Time Prescaler + [5:4] + + true + + DTPS1read-writeX11x (no division)0X22x1X44x2X88x3 + + + PSR1 + Timer/Counter 1 Prescaler reset + [6:6] + + + PWM1X + PWM Inversion Mode + [7:7] + + + + + TCCR1C + Timer/Counter Control Register C + 0x27 + + + PWM1D + Pulse Width Modulator D Enable + [0:0] + + + FOC1D + Force Output Compare Match 1D + [1:1] + write-only + + COM1D + Comparator D output mode + [3:2] + + true + COM1Dread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 + + + COM1B0S + COM1B0 Shadow Bit + [4:4] + + + COM1B1S + COM1B1 Shadow Bit + [5:5] + + + COM1A0S + COM1A0 Shadow Bit + [6:6] + + + COM1A1S + COM1A1 Shadow Bit + [7:7] + + + + + TCCR1D + Timer/Counter Control Register D + 0x26 + + + WGM1 + Waveform Generation Mode Bit + [1:0] + + true + WGM1read-writePWM_FASTFast PWM, Update: *TOP*, Flag: *TOP*0PWM_CORRECTPhase and Frequency Correct PWM, Update: *BOTTOM*, Flag: *BOTTOM*1PWM_SINGLE_SLOPEPWM6 / Single-slope, Update: *TOP*, Flag: *TOP*2PWM_DUAL_SLOPEPWM6 / Dual-slope, Update: *BOTTOM*, Flag: *BOTTOM*3 + + + FPF1 + Fault Protection Interrupt Flag + [2:2] + + + FPAC1 + Fault Protection Analog Comparator Enable + [3:3] + + + FPES1 + Fault Protection Edge Select + [4:4] + + + FPNC1 + Fault Protection Noise Canceler + [5:5] + + + FPEN1 + Fault Protection Mode Enable + [6:6] + + + FPIE1 + Fault Protection Interrupt Enable + [7:7] + + + + + TCCR1E + Timer/Counter1 Control Register E + 0x0 + + + OC1OE + Ouput Compare Override Enable Bits + [5:0] + + + 0 + 63 + + + + + + + TCNT1 + Timer/Counter Register + 0x2E + read-only + + + 0 + 255 + + + + + TIFR + Timer/Counter Interrupt Flag Register + 0x38 + read-only + + + TOV1 + Timer/Counter1 Overflow Flag + [2:2] + + + OCF1B + Timer/Counter1 Output Compare Flag 1B + [5:5] + + + OCF1A + Timer/Counter1 Output Compare Flag 1A + [6:6] + + + OCF1D + Timer/Counter1 Output Compare Flag 1D + [7:7] + + + + + TIMSK + Timer/Counter Interrupt Mask Register + 0x39 + + + TOIE1 + Timer/Counter1 Overflow Interrupt Enable + [2:2] + + + OCIE1B + OCIE1A: Timer/Counter1 Output Compare B Interrupt Enable + [5:5] + + + OCIE1A + OCIE1A: Timer/Counter1 Output Compare Interrupt Enable + [6:6] + + + OCIE1D + OCIE1D: Timer/Counter1 Output Compare Interrupt Enable + [7:7] + + + + + + + USI + Universal Serial Interface + 0x2D + + + USIBR + USI Buffer Register + 0x3 + read-only + + + 0 + 255 + + + + + USICR + USI Control Register + 0x0 + + + USITC + Toggle Clock Port Pin + [0:0] + write-only + + USICLK + Clock Strobe + [1:1] + write-only + + USICS + USI Clock Source Select Bits + [3:2] + + + 0 + 3 + + + USICSread-writeNO_CLOCKNo Clock/Software clock strobe0TC0Timer/Counter0 Compare Match1EXT_POSExternal, positive edge2EXT_NEGExternal, negative edge3 + + + USIWM + USI Wire Mode Bits + [5:4] + + true + + USIWMread-writeDISABLEDAll detectors disabled. Port pins operates as normal.0THREE_WIREThree-wire mode. Uses DO, DI, and USCK pins.1TWO_WIRE_SLAVETwo-wire mode (Slave). Uses SDA (DI) and SCL (USCK) pins.2TWO_WIRE_MASTERTwo-wire mode (Master). Uses SDA and SCL pins.3 + + + USIOIE + Counter Overflow Interrupt Enable + [6:6] + + + USISIE + Start Condition Interrupt Enable + [7:7] + + + + + USIDR + USI Data Register + 0x2 + + + 0 + 255 + + + + + USIPP + USI Pin Position + 0x4 + + + 0 + 255 + + + + + USISR + USI Status Register + 0x1 + read-write + + + USICNT + USI Counter Value Bits + [3:0] + + + 0 + 15 + + + + + USIDC + Data Output Collision + [4:4] + read-only + + USIPF + Stop Condition Flag + [5:5] + + + USIOIF + Counter Overflow Interrupt Flag + [6:6] + + + USISIF + Start Condition Interrupt Flag + [7:7] + + + + + + + WDT + Watchdog Timer + 0x41 + + + WDTCR + Watchdog Timer Control Register + 0x0 + read-write + + + WDE + Watch Dog Enable + [3:3] + + + WDCE + Watchdog Change Enable + [4:4] + + + WDIE + Watchdog Timeout Interrupt Enable + [6:6] + + + WDIF + Watchdog Timeout Interrupt Flag + [7:7] + + WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 + + WDPHWatchdog Timer Prescaler - High Bit[5:5] + + + + + + \ No newline at end of file diff --git a/misc/svd/attiny88.svd b/misc/svd/attiny88.svd new file mode 100644 index 0000000..85078aa --- /dev/null +++ b/misc/svd/attiny88.svd @@ -0,0 +1,2237 @@ + + Atmel + ATtiny88 + 8 + 8 + read-write + 0 + 0xff + + + AC + Analog Comparator + 0x50 + + + ACSR + Analog Comparator Control And Status Register + 0x0 + read-write + + + ACIS + Analog Comparator Interrupt Mode Select + [1:0] + + true + + ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 + + + ACIC + Analog Comparator Input Capture Enable + [2:2] + + + ACIE + Analog Comparator Interrupt Enable + [3:3] + + + ACI + Analog Comparator Interrupt Flag + [4:4] + + + ACO + Analog Compare Output + [5:5] + read-only + + ACBG + Analog Comparator Bandgap Select + [6:6] + + + ACD + Analog Comparator Disable + [7:7] + + + + + DIDR1 + Digital Input Disable Register 1 + 0x2F + + + AIN0D + AIN0 Digital Input Disable + [0:0] + + + AIN1D + AIN1 Digital Input Disable + [1:1] + + + + + + + ADC + Analog-to-Digital Converter + 0x78 + + + ADC + ADC Data Register Bytes + 0x0 + 16 + + + 0 + 65535 + + + + + ADCSRA + The ADC Control and Status register A + 0x2 + + + ADPS + ADC Prescaler Select Bits + [2:0] + + true + + ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 + + + ADIE + ADC Interrupt Enable + [3:3] + + + ADIF + ADC Interrupt Flag + [4:4] + + + ADATE + ADC Auto Trigger Enable + [5:5] + + + ADSC + ADC Start Conversion + [6:6] + + + ADEN + ADC Enable + [7:7] + + + + + ADCSRB + The ADC Control and Status register B + 0x3 + + + ADTS + ADC Auto Trigger Source bits + [2:0] + + true + + ADTSread-writeFREEFree Running mode0ACAnalog Comparator1INT0External Interrupt Request 02TC0_CMATimer/Counter0 Compare Match A3TC0_OVFTimer/Counter0 Overflow4TC1_CMBTimer/Counter1 Compare Match B5TC1_OVFTimer/Counter1 Overflow6TC1_CETimer/Counter1 Capture Event7 + + + ACME + <TBD> + [6:6] + + + + + ADMUX + The ADC multiplexer Selection Register + 0x4 + + + MUX + Analog Channel Selection Bits + [3:0] + + + 0 + 15 + + + MUXread-writeADC0ADC Single Ended Input pin 00ADC1ADC Single Ended Input pin 11ADC2ADC Single Ended Input pin 22ADC3ADC Single Ended Input pin 33ADC4ADC Single Ended Input pin 44ADC5ADC Single Ended Input pin 55ADC6ADC Single Ended Input pin 66ADC7ADC Single Ended Input pin 77TEMPSENSTemperature sensor8ADC_VBGInternal Reference (VBG)14ADC_GND0V (GND)15 + + + ADLAR + Left Adjust Result + [5:5] + + + REFS0 + Reference Selection Bit 0 + [6:6] + + true + + REFS0read-writeINTERNALInternal 1.1V Voltage Reference0AVCCAVcc Reference1 + + + + + DIDR0 + Digital Input Disable Register 0 + 0x6 + + + ADC0D + <TBD> + [0:0] + + + ADC1D + <TBD> + [1:1] + + + ADC2D + <TBD> + [2:2] + + + ADC3D + <TBD> + [3:3] + + + ADC4D + <TBD> + [4:4] + + + ADC5D + <TBD> + [5:5] + + + ADC6D + <TBD> + [6:6] + + + ADC7D + <TBD> + [7:7] + + + + + DIDR1 + Digital Input Disable Register 1 + 0x7 + + + AIN0D + <TBD> + [0:0] + + + AIN1D + <TBD> + [1:1] + + + + + + + CPU + CPU Registers + 0x32 + + RESET + External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + 0 + + + INT0 + External Interrupt Request 0 + 1 + + + INT1 + External Interrupt Request 1 + 2 + + + PCINT0 + Pin Change Interrupt Request 0 + 3 + + + PCINT1 + Pin Change Interrupt Request 1 + 4 + + + PCINT2 + Pin Change Interrupt Request 2 + 5 + + + PCINT3 + Pin Change Interrupt Request 3 + 6 + + + WDT + Watchdog Time-out Interrupt + 7 + + + TIMER1_CAPT + Timer/Counter1 Capture Event + 8 + + + TIMER1_COMPA + Timer/Counter1 Compare Match A + 9 + + + TIMER1_COMPB + Timer/Counter1 Compare Match B + 10 + + + TIMER1_OVF + Timer/Counter1 Overflow + 11 + + + TIMER0_COMPA + TimerCounter0 Compare Match A + 12 + + + TIMER0_COMPB + TimerCounter0 Compare Match B + 13 + + + TIMER0_OVF + Timer/Couner0 Overflow + 14 + + + SPI_STC + SPI Serial Transfer Complete + 15 + + + ADC + ADC Conversion Complete + 16 + + + EE_RDY + EEPROM Ready + 17 + + + ANALOG_COMP + Analog Comparator + 18 + + + TWI + Two-wire Serial Interface + 19 + + + + CLKPR + Clock Prescale Register + 0x2F + read-write + + + CLKPS + Clock Prescaler Select Bits + [3:0] + + true + + CLKPSread-writePRESCALER_1Prescaler Value 10PRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287PRESCALER_256Prescaler Value 2568 + + + CLKPCE + Clock Prescaler Change Enable + [7:7] + + + + + GPIOR0 + General Purpose I/O Register 0 + 0xC + + + 0 + 255 + + + + + GPIOR1 + General Purpose I/O Register 1 + 0x18 + + + 0 + 255 + + + + + GPIOR2 + General Purpose I/O Register 2 + 0x19 + + + 0 + 255 + + + + + MCUCR + MCU Control Register + 0x23 + + + PUD + Pull-up Disable + [4:4] + + + BODSE + BOD Sleep Enable + [5:5] + + + BODS + BOD Sleep + [6:6] + + + + + MCUSR + MCU Status Register + 0x22 + + + PORF + Power-on reset flag + [0:0] + + + EXTRF + External Reset Flag + [1:1] + + + BORF + Brown-out Reset Flag + [2:2] + + + WDRF + Watchdog Reset Flag + [3:3] + + + + + OSCCAL + Oscillator Calibration Value + 0x34 + read-write + + + OSCCAL + Oscillator Calibration + [7:0] + + + 0 + 255 + + + + + + + PORTCR + Port Configuration Register + 0x0 + read-write + + + PUDA + <TBD> + [0:0] + + + PUDB + <TBD> + [1:1] + + + PUDC + <TBD> + [2:2] + + + PUDD + <TBD> + [3:3] + + + BBMA + <TBD> + [4:4] + + + BBMB + <TBD> + [5:5] + + + BBMC + <TBD> + [6:6] + + + BBMD + <TBD> + [7:7] + + + + + PRR + Power Reduction Register + 0x32 + read-write + + + PRADC + Power Reduction ADC + [0:0] + + + PRSPI + Power Reduction Serial Peripheral Interface + [2:2] + + + PRTIM1 + Power Reduction Timer/Counter1 + [3:3] + + + PRTIM0 + Power Reduction Timer/Counter0 + [5:5] + + + PRTWI + Power Reduction TWI + [7:7] + + + + + SMCR + Sleep Mode Control Register + 0x21 + + + SE + Sleep Enable + [0:0] + + + SM + Sleep Mode + [2:1] + + true + + SMread-writeIDLEIdle0ADCADC Noise Reduction1PDOWNPower-down2 + + + + + SPH + Stack Pointer High + 0x2C + + + 0 + 255 + + + + + SPL + Stack Pointer Low + 0x2B + + + 0 + 255 + + + + + SPMCSR + Store Program Memory Control Register + 0x25 + + + SELFPRGEN + Self Programming Enable + [0:0] + + + PGERS + Page Erase + [1:1] + + + PGWRT + Page Write + [2:2] + + + RFLB + Read Fuse and Lock Bits + [3:3] + + + CTPB + Clear Temporary Page Buffer + [4:4] + + + RWWSB + Read-While-Write Section Busy + [6:6] + + + + + + + EEPROM + EEPROM + 0x3F + + + EEARL + EEPROM Address Register Low Byte + 0x2 + + + 0 + 255 + + + + + EECR + EEPROM Control Register + 0x0 + + + EERE + EEPROM Read Enable + [0:0] + + + EEPE + EEPROM Write Enable + [1:1] + + + EEMPE + EEPROM Master Write Enable + [2:2] + + + EERIE + EEPROM Ready Interrupt Enable + [3:3] + + + EEPM + EEPROM Programming Mode Bits + [5:4] + + true + + EEPMread-writeATOMICAtomic (erase and write in one operation)0ERASEErase only1WRITEWrite only2 + + + + + EEDR + EEPROM Data Register + 0x1 + + + 0 + 255 + + + + + + + EXINT + External Interrupts + 0x3B + + + EICRA + External Interrupt Control Register + 0x2E + + + ISC0 + External Interrupt Sense Control 0 Bits + [1:0] + + true + + ISC0read-writeLOWThe low level of INTx generates an interrupt request0TOGGLEAny logical change on INTx generates an interrupt request1FALLINGThe falling edge of INTx generates an interrupt request2RISINGThe rising edge of INTx generates an interrupt request3 + + + ISC1 + External Interrupt Sense Control 1 Bits + [3:2] + + true + + + + + + + EIFR + External Interrupt Flag Register + 0x1 + read-only + + + INTF + External Interrupt Flags + [1:0] + + + 0 + 3 + + + + + + + EIMSK + External Interrupt Mask Register + 0x2 + + + INT + External Interrupt Request 1 Enable + [1:0] + + + 0 + 3 + + + + + + + PCICR + Pin Change Interrupt Control Register + 0x2D + + + PCIE + <TBD> + [3:0] + + + 0 + 15 + + + + + + + PCIFR + Pin Change Interrupt Flag Register + 0x0 + read-only + + + PCIF + Pin Change Interrupt Flags + [3:0] + + + 0 + 15 + + + + + + + PCMSK0 + Pin Change Mask Register 0 + 0x30 + + + PCINT + Pin Change Enable Masks + [7:0] + + + 0 + 255 + + + + + + + PCMSK1 + Pin Change Mask Register 1 + 0x31 + + + PCINT + Pin Change Enable Masks + [7:0] + + + 0 + 255 + + + + + + + PCMSK2 + Pin Change Mask Register 2 + 0x32 + + + PCINT + Pin Change Enable Masks + [7:0] + + + 0 + 255 + + + + + + + PCMSK3 + Pin Change Mask Register 3 + 0x2F + + + PCINT + Pin Change Enable Masks + [3:0] + + + 0 + 15 + + + + + + + + + FUSE + Fuses + 0x0 + + + EXTENDED + <TBD> + 0x2 + + + SELFPRGEN + Self Programming enable + [0:0] + + + + + HIGH + <TBD> + 0x1 + + + BODLEVEL + Brown-out Detector trigger level + [2:0] + + true + + + + 4V3 + Brown-out detection at VCC=4.3 V + 4 + + + 2V7 + Brown-out detection at VCC=2.7 V + 5 + + + 1V8 + Brown-out detection at VCC=1.8 V + 6 + + + DISABLED + Brown-out detection disabled + 7 + + + + + EESAVE + Preserve EEPROM through the Chip Erase cycle + [3:3] + + + WDTON + Watch-dog Timer always on + [4:4] + + + SPIEN + Serial program downloading (SPI) enabled + [5:5] + + + DWEN + Debug Wire enable + [6:6] + + + RSTDISBL + Reset Disabled (Enable PC6 as i/o pin) + [7:7] + + + + + LOW + <TBD> + 0x0 + + + SUT_CKSEL + Select Clock Source + [5:0] + + true + + + + EXTCLK_6CK_14CK_0MS + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 12 + + + INTRCOSC_8MHZ_6CK_14CK_0MS + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 14 + + + INTRCOSC_128KHZ_6CK_14CK_0MS + Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms + 15 + + + EXTCLK_6CK_14CK_4MS1 + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + 28 + + + INTRCOSC_8MHZ_6CK_14CK_4MS1 + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + 30 + + + INTRCOSC_128KHZ_6CK_14CK_4MS1 + Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms + 31 + + + EXTCLK_6CK_14CK_65MS + Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + 44 + + + INTRCOSC_8MHZ_6CK_14CK_65MS_DEFAULT + Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; default value + 46 + + + INTRCOSC_128KHZ_6CK_14CK_65MS + Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms + 47 + + + + + CKOUT + Clock output on PORTB0 + [6:6] + + + CKDIV8 + Divide clock by 8 internally + [7:7] + + + + + + + LOCKBIT + Lockbits + 0x0 + + + LOCKBIT + <TBD> + 0x0 + + + LB + Memory Lock + [1:0] + + true + + + + PROG_VER_DISABLED + Further programming and verification disabled + 0 + + + PROG_DISABLED + Further programming disabled + 2 + + + NO_LOCK + No memory lock features enabled + 3 + + + + + + + + + PORTA + I/O Port + 0x2C + + + DDRA + Port A Data Direction Register + 0x1 + read-write + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + + + PINA + Port A Input Pins + 0x0 + read-write + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + + + PORTA + Port A Data Register + 0x2 + read-write + + + PA0 + Pin A0 + [0:0] + + + PA1 + Pin A1 + [1:1] + + + PA2 + Pin A2 + [2:2] + + + PA3 + Pin A3 + [3:3] + + + + + + + PORTB + I/O Port + 0x23 + + + DDRB + Port B Data Direction Register + 0x1 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PINB + Port B Input Pins + 0x0 + read-write + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + PORTB + Port B Data Register + 0x2 + + + PB0 + Pin B0 + [0:0] + + + PB1 + Pin B1 + [1:1] + + + PB2 + Pin B2 + [2:2] + + + PB3 + Pin B3 + [3:3] + + + PB4 + Pin B4 + [4:4] + + + PB5 + Pin B5 + [5:5] + + + PB6 + Pin B6 + [6:6] + + + PB7 + Pin B7 + [7:7] + + + + + + + PORTC + I/O Port + 0x26 + + + DDRC + Port C Data Direction Register + 0x1 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + PINC + Port C Input Pins + 0x0 + read-write + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + PORTC + Port C Data Register + 0x2 + + + PC0 + Pin C0 + [0:0] + + + PC1 + Pin C1 + [1:1] + + + PC2 + Pin C2 + [2:2] + + + PC3 + Pin C3 + [3:3] + + + PC4 + Pin C4 + [4:4] + + + PC5 + Pin C5 + [5:5] + + + PC6 + Pin C6 + [6:6] + + + PC7 + Pin C7 + [7:7] + + + + + + + PORTD + I/O Port + 0x29 + + + DDRD + Port D Data Direction Register + 0x1 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PIND + Port D Input Pins + 0x0 + read-write + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + PORTD + Port D Data Register + 0x2 + + + PD0 + Pin D0 + [0:0] + + + PD1 + Pin D1 + [1:1] + + + PD2 + Pin D2 + [2:2] + + + PD3 + Pin D3 + [3:3] + + + PD4 + Pin D4 + [4:4] + + + PD5 + Pin D5 + [5:5] + + + PD6 + Pin D6 + [6:6] + + + PD7 + Pin D7 + [7:7] + + + + + + + SPI + Serial Peripheral Interface + 0x4C + + + SPCR + SPI Control Register + 0x0 + + + SPR + SPI Clock Rate Selects + [1:0] + + true + + SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 + + + CPHA + Clock Phase + [2:2] + + + CPOL + Clock polarity + [3:3] + + + MSTR + Master/Slave Select + [4:4] + + + DORD + Data Order + [5:5] + + + SPE + SPI Enable + [6:6] + + + SPIE + SPI Interrupt Enable + [7:7] + + + + + SPDR + SPI Data Register + 0x2 + + + 0 + 255 + + + + + SPSR + SPI Status Register + 0x1 + read-write + + + SPI2X + Double SPI Speed Bit + [0:0] + read-write + + WCOL + Write Collision Flag + [6:6] + read-only + + SPIF + SPI Interrupt Flag + [7:7] + read-only + + + + + + TC0 + Timer/Counter, 8-bit + 0x35 + + + GTCCR + General Timer/Counter Control Register + 0xE + + + PSRSYNC + Prescaler Reset Timer/Counter1 and Timer/Counter0 + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + OCR0A + Timer/Counter0 Output Compare Register + 0x12 + + + 0 + 255 + + + + + OCR0B + Timer/Counter0 Output Compare Register + 0x13 + + + 0 + 255 + + + + + TCCR0A + Timer/Counter Control Register A + 0x10 + + + CS0 + Clock Select + [2:0] + + true + + CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + CTC0 + Clear Timer on Compare Match + [3:3] + + + + + TCNT0 + Timer/Counter0 + 0x11 + + + 0 + 255 + + + + + TIFR0 + Timer/Counter0 Interrupt Flag register + 0x0 + read-only + + + TOV0 + Timer/Counter0 Overflow Flag + [0:0] + + + OCF0A + Timer/Counter0 Output Compare Flag 0A + [1:1] + + + OCF0B + Timer/Counter0 Output Compare Flag 0B + [2:2] + + + + + TIMSK0 + Timer/Counter0 Interrupt Mask Register + 0x39 + + + TOIE0 + Timer/Counter0 Overflow Interrupt Enable + [0:0] + + + OCIE0A + Timer/Counter0 Output Compare Match A Interrupt Enable + [1:1] + + + OCIE0B + Timer/Counter0 Output Compare Match B Interrupt Enable + [2:2] + + + + + + + TC1 + Timer/Counter1, 16-bit, PWM + 0x36 + + + GTCCR + General Timer/Counter Control Register + 0xD + + + PSRSYNC + Prescaler Reset Timer/Counter1 and Timer/Counter0 + [0:0] + + + TSM + Timer/Counter Synchronization Mode + [7:7] + + + + + ICR1 + Timer/Counter1 Input Capture Register Bytes + 0x50 + 16 + + + 0 + 65535 + + + + + OCR1A + Timer/Counter1 Output Compare Register Bytes + 0x52 + 16 + + + 0 + 65535 + + + + + OCR1B + Timer/Counter1 Output Compare Register Bytes + 0x54 + 16 + + + 0 + 65535 + + + + + TCCR1A + Timer/Counter1 Control Register A + 0x4A + + + WGM1 + Waveform Generation Mode + [1:0] + + + 0 + 3 + + + + + COM1B + Compare Output Mode 1B, bits + [5:4] + + true + COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 + + + COM1A + Compare Output Mode 1A, bits + [7:6] + + true + + + + + + TCCR1B + Timer/Counter1 Control Register B + 0x4B + + + CS1 + Prescaler source of Timer/Counter 1 + [2:0] + + true + CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 + + + WGM1 + Waveform Generation Mode + [4:3] + + + 0 + 3 + + + + + ICES1 + Input Capture 1 Edge Select + [6:6] + + + ICNC1 + Input Capture 1 Noise Canceler + [7:7] + + + + + TCCR1C + Timer/Counter1 Control Register C + 0x4C + + + FOC1B + <TBD> + [6:6] + write-only + + FOC1A + <TBD> + [7:7] + write-only + + + + TCNT1 + Timer/Counter1 Bytes + 0x4E + 16 + + + 0 + 65535 + + + + + TIFR1 + Timer/Counter Interrupt Flag register + 0x0 + read-write + + + TOV1 + Timer/Counter1 Overflow Flag + [0:0] + + + OCF1A + Output Compare Flag 1A + [1:1] + + + OCF1B + Output Compare Flag 1B + [2:2] + + + ICF1 + Input Capture Flag 1 + [5:5] + + + + + TIMSK1 + Timer/Counter Interrupt Mask Register + 0x39 + + + TOIE1 + Timer/Counter1 Overflow Interrupt Enable + [0:0] + + + OCIE1A + Timer/Counter1 Output CompareA Match Interrupt Enable + [1:1] + + + OCIE1B + Timer/Counter1 Output CompareB Match Interrupt Enable + [2:2] + + + ICIE1 + Timer/Counter1 Input Capture Interrupt Enable + [5:5] + + + + + + + TWI + Two Wire Serial Interface + 0xB8 + + + TWAMR + TWI (Slave) Address Mask Register + 0x5 + + + TWAM + TWI (Slave) Address Mask Bits + [7:1] + + + 0 + 127 + + + + + + + TWAR + TWI (Slave) Address register + 0x2 + + + TWGCE + TWI General Call Recognition Enable Bit + [0:0] + + + TWA + TWI (Slave) Address register Bits + [7:1] + + + 0 + 127 + + + + + + + TWBR + TWI Bit Rate register + 0x0 + + + 0 + 255 + + + + + TWCR + TWI Control Register + 0x4 + read-write + + TWIE + TWI Interrupt Enable + [0:0] + + + TWEN + TWI Enable Bit + [2:2] + + + TWWC + TWI Write Collition Flag + [3:3] + read-only + + TWSTO + TWI Stop Condition Bit + [4:4] + + + TWSTA + TWI Start Condition Bit + [5:5] + + + TWEA + TWI Enable Acknowledge Bit + [6:6] + + + TWINT + TWI Interrupt Flag + [7:7] + + + + + TWDR + TWI Data register + 0x3 + + + 0 + 255 + + + + + TWHSR + TWHSR + 0x6 + + + TWHS + <TBD> + [0:0] + + + + + TWSR + TWI Status Register + 0x1 + + + TWPS + TWI Prescaler + [1:0] + + true + + TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 + + + TWS + TWI Status + [7:3] + read-only + + 0 + 31 + + + + + + + + + WDT + Watchdog Timer + 0x60 + + + WDTCSR + Watchdog Timer Control Register + 0x0 + read-write + + + WDE + Watch Dog Enable + [3:3] + + + WDCE + Watchdog Change Enable + [4:4] + + + WDIE + Watchdog Timeout Interrupt Enable + [6:6] + + + WDIF + Watchdog Timeout Interrupt Flag + [7:7] + + WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 + + WDPHWatchdog Timer Prescaler - High Bit[5:5] + + + + + + \ No newline at end of file From fd5a81cc08f529da88eb8364660fa75d20969262 Mon Sep 17 00:00:00 2001 From: unknown Date: Tue, 1 Nov 2022 00:38:35 +0100 Subject: [PATCH 02/11] Basis for supporting Move38 boards --- builder/frameworks/arduino.py | 8 ++++++++ builder/main.py | 5 ++++- platform.json | 5 +++++ 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/builder/frameworks/arduino.py b/builder/frameworks/arduino.py index 83444cf..2152010 100644 --- a/builder/frameworks/arduino.py +++ b/builder/frameworks/arduino.py @@ -131,6 +131,14 @@ def get_bootloader_size(): ) # +# Expand linker script to its full path +# Add specia linker options +# +if build_core in ("blinklib"): + ldscript = board.get("build.ldscript") + env.Replace(LDSCRIPT_PATH=join(FRAMEWORK_DIR, "linkscripts", ldscript)) + env.Append(LINKFLAGS=["-mrelax", "-nostartfiles"]) +# # Take into account bootloader size # diff --git a/builder/main.py b/builder/main.py index c8ac00b..946c968 100644 --- a/builder/main.py +++ b/builder/main.py @@ -107,6 +107,8 @@ def _rpi_sysgpio(path, value): PROGSUFFIX=".elf", ) +builtinbase = int(env.BoardConfig().get("build", {}).get("builtinbase", "0"), 16) + env.Append( BUILDERS=dict( ElfToEep=Builder( @@ -133,7 +135,8 @@ def _rpi_sysgpio(path, value): ElfToHex=Builder( action=env.VerboseAction( " ".join( - ["$OBJCOPY", "-O", "ihex", "-R", ".eeprom", "$SOURCES", "$TARGET"] + ["$OBJCOPY", "-O", "ihex", "-R", ".eeprom", "$SOURCES", "$TARGET"] if builtinbase == 0 else \ + ["$OBJCOPY", "--change-addresses", hex(builtinbase), "-O", "ihex", "-R", ".eepromm", "$SOURCES", "$TARGET"] ), "Building $TARGET", ), diff --git a/platform.json b/platform.json index 172bccb..08f78ab 100644 --- a/platform.json +++ b/platform.json @@ -49,6 +49,11 @@ "owner": "platformio", "version": "~2.0.3" }, + "framework-arduino-avr-blinklib": { + "type": "framework", + "optional": true, + "version": "https://github.com/maxgerhardt/pio-blinks-core.git" + }, "framework-arduino-avr-core13": { "type": "framework", "optional": true, From a8853bd4230774a2e42df1fb2ce0cf6cc4bb41d6 Mon Sep 17 00:00:00 2001 From: unknown Date: Tue, 1 Nov 2022 12:10:30 +0100 Subject: [PATCH 03/11] Make bootloader file available --- builder/frameworks/arduino.py | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/builder/frameworks/arduino.py b/builder/frameworks/arduino.py index 2152010..4201039 100644 --- a/builder/frameworks/arduino.py +++ b/builder/frameworks/arduino.py @@ -132,12 +132,17 @@ def get_bootloader_size(): # # Expand linker script to its full path -# Add specia linker options +# Add special linker options +# Make bootloader file available (needs to be flashed in one go) # if build_core in ("blinklib"): ldscript = board.get("build.ldscript") env.Replace(LDSCRIPT_PATH=join(FRAMEWORK_DIR, "linkscripts", ldscript)) - env.Append(LINKFLAGS=["-mrelax", "-nostartfiles"]) + env.Append( + LINKFLAGS=["-mrelax", "-nostartfiles"], + BOOTLOADER_FILE=join(FRAMEWORK_DIR, "bootloaders", board.get("bootloader.file")) + ) + # # Take into account bootloader size # From 08864c13faab34a3145b315762ab78feeeb5d0bc Mon Sep 17 00:00:00 2001 From: unknown Date: Tue, 1 Nov 2022 12:32:54 +0100 Subject: [PATCH 04/11] Cleanup, add all boards, add example to CI --- .github/workflows/examples.yml | 1 + boards/move38_blink.json | 38 ++++++++++++++++++++++++++++++ boards/move38_blink328.json | 38 ++++++++++++++++++++++++++++++ boards/move38_blinkmax.json | 38 ++++++++++++++++++++++++++++++ boards/move38_blinknfc.json | 38 ++++++++++++++++++++++++++++++ builder/frameworks/arduino.py | 3 ++- examples/arduino-move38-colorwheel | 1 + 7 files changed, 156 insertions(+), 1 deletion(-) create mode 100644 boards/move38_blink.json create mode 100644 boards/move38_blink328.json create mode 100644 boards/move38_blinkmax.json create mode 100644 boards/move38_blinknfc.json create mode 160000 examples/arduino-move38-colorwheel diff --git a/.github/workflows/examples.yml b/.github/workflows/examples.yml index cd4fa45..07b64bf 100644 --- a/.github/workflows/examples.yml +++ b/.github/workflows/examples.yml @@ -12,6 +12,7 @@ jobs: - "examples/arduino-blink" - "examples/arduino-external-libs" - "examples/arduino-internal-libs" + - "examples/arduino-move38-colorwheel" - "examples/arduino-own-src_dir" - "examples/assembly-blink" - "examples/digitstump-mouse" diff --git a/boards/move38_blink.json b/boards/move38_blink.json new file mode 100644 index 0000000..af813bc --- /dev/null +++ b/boards/move38_blink.json @@ -0,0 +1,38 @@ +{ + "build": { + "core": "blinklib", + "extra_flags": "-DARDUINO_AVR_BLINK_168", + "f_cpu": "8000000L", + "mcu": "atmega168pb", + "variant": "standard", + "ldscript": "avr5-atmega168pb.xn", + "builtinbase": "0x1700" + }, + "bootloader": { + "file": "BlinkBIOS-168PB.hex", + "lfuse": "0x62", + "hfuse": "0xDF", + "efuse": "0xf8" + }, + "debug": { + "simavr_target": "atmega168p" + }, + "fuses" : { + "lfuse": "0x62", + "hfuse": "0xDF", + "efuse": "0xf8" + }, + "frameworks": [ + "arduino" + ], + "name": "Blink", + "upload": { + "maximum_ram_size": 1024, + "maximum_size": 5888, + "protocol": "usbtiny", + "require_upload_port": false, + "speed": 115200 + }, + "url": "https://move38.com/", + "vendor": "Move38" +} \ No newline at end of file diff --git a/boards/move38_blink328.json b/boards/move38_blink328.json new file mode 100644 index 0000000..f6ee229 --- /dev/null +++ b/boards/move38_blink328.json @@ -0,0 +1,38 @@ +{ + "build": { + "core": "blinklib", + "extra_flags": "-DARDUINO_AVR_BLINK_328", + "f_cpu": "8000000L", + "mcu": "atmega328pb", + "variant": "standard", + "ldscript": "avr5-atmega328.xn", + "builtinbase": "0x3900" + }, + "bootloader": { + "file": "BlinkBIOS-328PB.hex", + "lfuse": "0x62", + "hfuse": "0xD8", + "efuse": "0xff" + }, + "debug": { + "simavr_target": "atmega328p" + }, + "fuses" : { + "lfuse": "0x62", + "hfuse": "0xD8", + "efuse": "0xff" + }, + "frameworks": [ + "arduino" + ], + "name": "Blink328", + "upload": { + "maximum_ram_size": 1024, + "maximum_size": 5888, + "protocol": "usbtiny", + "require_upload_port": false, + "speed": 115200 + }, + "url": "https://move38.com/", + "vendor": "Move38" +} \ No newline at end of file diff --git a/boards/move38_blinkmax.json b/boards/move38_blinkmax.json new file mode 100644 index 0000000..360042c --- /dev/null +++ b/boards/move38_blinkmax.json @@ -0,0 +1,38 @@ +{ + "build": { + "core": "blinklib", + "extra_flags": "-DARDUINO_AVR_BLINK_328", + "f_cpu": "8000000L", + "mcu": "atmega328pb", + "variant": "standard", + "ldscript": "avr5-atmega328.xn", + "builtinbase": "0x3900" + }, + "bootloader": { + "file": "BlinkBIOS-328PB-MAX.hex", + "lfuse": "0x62", + "hfuse": "0xD8", + "efuse": "0xff" + }, + "debug": { + "simavr_target": "atmega328p" + }, + "fuses" : { + "lfuse": "0x62", + "hfuse": "0xD8", + "efuse": "0xff" + }, + "frameworks": [ + "arduino" + ], + "name": "BlinkMAX", + "upload": { + "maximum_ram_size": 2048, + "maximum_size": 7936, + "protocol": "usbtiny", + "require_upload_port": false, + "speed": 115200 + }, + "url": "https://move38.com/", + "vendor": "Move38" +} \ No newline at end of file diff --git a/boards/move38_blinknfc.json b/boards/move38_blinknfc.json new file mode 100644 index 0000000..8f26fc8 --- /dev/null +++ b/boards/move38_blinknfc.json @@ -0,0 +1,38 @@ +{ + "build": { + "core": "blinklib", + "extra_flags": "-DARDUINO_AVR_BLINK_328", + "f_cpu": "8000000L", + "mcu": "atmega328pb", + "variant": "standard", + "ldscript": "avr5-atmega328.xn", + "builtinbase": "0x3900" + }, + "bootloader": { + "file": "BlinkBIOS-328PB-MAX-NFC.hex", + "lfuse": "0x62", + "hfuse": "0xD8", + "efuse": "0xff" + }, + "debug": { + "simavr_target": "atmega328p" + }, + "fuses" : { + "lfuse": "0x62", + "hfuse": "0xD8", + "efuse": "0xff" + }, + "frameworks": [ + "arduino" + ], + "name": "BlinkNFC", + "upload": { + "maximum_ram_size": 2048, + "maximum_size": 7936, + "protocol": "usbtiny", + "require_upload_port": false, + "speed": 115200 + }, + "url": "https://move38.com/", + "vendor": "Move38" +} \ No newline at end of file diff --git a/builder/frameworks/arduino.py b/builder/frameworks/arduino.py index 4201039..9ecba0f 100644 --- a/builder/frameworks/arduino.py +++ b/builder/frameworks/arduino.py @@ -133,7 +133,8 @@ def get_bootloader_size(): # # Expand linker script to its full path # Add special linker options -# Make bootloader file available (needs to be flashed in one go) +# Make bootloader file available as env variable +# (needs to be flashed in one go) # if build_core in ("blinklib"): ldscript = board.get("build.ldscript") diff --git a/examples/arduino-move38-colorwheel b/examples/arduino-move38-colorwheel new file mode 160000 index 0000000..0169d91 --- /dev/null +++ b/examples/arduino-move38-colorwheel @@ -0,0 +1 @@ +Subproject commit 0169d9110cbfa3359bfe323074b8e573d69db525 From af20e96c7152bc3228af05d6207da29757ddce0c Mon Sep 17 00:00:00 2001 From: unknown Date: Tue, 1 Nov 2022 12:34:59 +0100 Subject: [PATCH 05/11] Readd as proper folder --- examples/arduino-move38-colorwheel | 1 - examples/arduino-move38-colorwheel/.gitignore | 2 + examples/arduino-move38-colorwheel/README.md | Bin 0 -> 38 bytes .../arduino-move38-colorwheel/include/README | 39 +++++++++++++++ examples/arduino-move38-colorwheel/lib/README | 46 ++++++++++++++++++ .../arduino-move38-colorwheel/platformio.ini | 37 ++++++++++++++ .../arduino-move38-colorwheel/src/main.cpp | 30 ++++++++++++ .../arduino-move38-colorwheel/test/README | 11 +++++ 8 files changed, 165 insertions(+), 1 deletion(-) delete mode 160000 examples/arduino-move38-colorwheel create mode 100644 examples/arduino-move38-colorwheel/.gitignore create mode 100644 examples/arduino-move38-colorwheel/README.md create mode 100644 examples/arduino-move38-colorwheel/include/README create mode 100644 examples/arduino-move38-colorwheel/lib/README create mode 100644 examples/arduino-move38-colorwheel/platformio.ini create mode 100644 examples/arduino-move38-colorwheel/src/main.cpp create mode 100644 examples/arduino-move38-colorwheel/test/README diff --git a/examples/arduino-move38-colorwheel b/examples/arduino-move38-colorwheel deleted file mode 160000 index 0169d91..0000000 --- a/examples/arduino-move38-colorwheel +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 0169d9110cbfa3359bfe323074b8e573d69db525 diff --git a/examples/arduino-move38-colorwheel/.gitignore b/examples/arduino-move38-colorwheel/.gitignore new file mode 100644 index 0000000..3b8da3a --- /dev/null +++ b/examples/arduino-move38-colorwheel/.gitignore @@ -0,0 +1,2 @@ +.pio +.vscode \ No newline at end of file diff --git a/examples/arduino-move38-colorwheel/README.md b/examples/arduino-move38-colorwheel/README.md new file mode 100644 index 0000000000000000000000000000000000000000..9827b30ef9346684f98b12bdf6dd48d960a25461 GIT binary patch literal 38 pcmezWPnki1p@1QiA)i5)As0xNF&Hyg0NEuBsSL$Hl9z#t0RXjT2X_Df literal 0 HcmV?d00001 diff --git a/examples/arduino-move38-colorwheel/include/README b/examples/arduino-move38-colorwheel/include/README new file mode 100644 index 0000000..194dcd4 --- /dev/null +++ b/examples/arduino-move38-colorwheel/include/README @@ -0,0 +1,39 @@ + +This directory is intended for project header files. + +A header file is a file containing C declarations and macro definitions +to be shared between several project source files. You request the use of a +header file in your project source file (C, C++, etc) located in `src` folder +by including it, with the C preprocessing directive `#include'. + +```src/main.c + +#include "header.h" + +int main (void) +{ + ... +} +``` + +Including a header file produces the same results as copying the header file +into each source file that needs it. Such copying would be time-consuming +and error-prone. With a header file, the related declarations appear +in only one place. If they need to be changed, they can be changed in one +place, and programs that include the header file will automatically use the +new version when next recompiled. The header file eliminates the labor of +finding and changing all the copies as well as the risk that a failure to +find one copy will result in inconsistencies within a program. + +In C, the usual convention is to give header files names that end with `.h'. +It is most portable to use only letters, digits, dashes, and underscores in +header file names, and at most one dot. + +Read more about using header files in official GCC documentation: + +* Include Syntax +* Include Operation +* Once-Only Headers +* Computed Includes + +https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html diff --git a/examples/arduino-move38-colorwheel/lib/README b/examples/arduino-move38-colorwheel/lib/README new file mode 100644 index 0000000..6debab1 --- /dev/null +++ b/examples/arduino-move38-colorwheel/lib/README @@ -0,0 +1,46 @@ + +This directory is intended for project specific (private) libraries. +PlatformIO will compile them to static libraries and link into executable file. + +The source code of each library should be placed in a an own separate directory +("lib/your_library_name/[here are source files]"). + +For example, see a structure of the following two libraries `Foo` and `Bar`: + +|--lib +| | +| |--Bar +| | |--docs +| | |--examples +| | |--src +| | |- Bar.c +| | |- Bar.h +| | |- library.json (optional, custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html +| | +| |--Foo +| | |- Foo.c +| | |- Foo.h +| | +| |- README --> THIS FILE +| +|- platformio.ini +|--src + |- main.c + +and a contents of `src/main.c`: +``` +#include +#include + +int main (void) +{ + ... +} + +``` + +PlatformIO Library Dependency Finder will find automatically dependent +libraries scanning project source files. + +More information about PlatformIO Library Dependency Finder +- https://docs.platformio.org/page/librarymanager/ldf.html diff --git a/examples/arduino-move38-colorwheel/platformio.ini b/examples/arduino-move38-colorwheel/platformio.ini new file mode 100644 index 0000000..cae66c1 --- /dev/null +++ b/examples/arduino-move38-colorwheel/platformio.ini @@ -0,0 +1,37 @@ +; PlatformIO Project Configuration File +; +; Build options: build flags, source filter +; Upload options: custom upload port, speed and extra flags +; Library options: dependencies, extra library storages +; Advanced options: extra scripting +; +; Please visit documentation for the other options and examples +; https://docs.platformio.org/page/projectconf.html + +[env] +; global settings +platform = atmelavr +framework = arduino +; use USBtinyISP as programmer +; burn bootloader and firmware at the same time +upload_protocol = custom +upload_flags = + -C + ${platformio.packages_dir}/tool-avrdude/avrdude.conf + -p + $BOARD_MCU + -c + usbtiny +upload_command = avrdude $UPLOAD_FLAGS -U flash:w:$SOURCE:i -Uflash:w:"$BOOTLOADER_FILE":i + +[env:move38_blink] +board = move38_blink + +[env:move38_blink328] +board = move38_blink328 + +[env:move38_blinkmax] +board = move38_blinkmax + +[env:move38_blinknfc] +board = move38_blinknfc diff --git a/examples/arduino-move38-colorwheel/src/main.cpp b/examples/arduino-move38-colorwheel/src/main.cpp new file mode 100644 index 0000000..c35f3ee --- /dev/null +++ b/examples/arduino-move38-colorwheel/src/main.cpp @@ -0,0 +1,30 @@ +#include +// Spin around in goovy HSB color space +// HSB stands for Hue, Saturation, and Brightness +// https://en.wikipedia.org/wiki/HSL_and_HSV + +void setup() { + // No setup needed for this simple example! +} + +byte hue=0; + +Timer nextStep; + +void loop() { + + if (nextStep.isExpired()) { + + // Spin the hue while keeping color saturation and brightness at max + setColor( makeColorHSB( hue , 255 , 255 ) ); + + // Becuase we are using an 8-bit byte for the `hue` variable, + // this will automatically roll over from 255 back down to 0 + // (255 is 11111111 in binary, and 11111111 + 00000001 = 00000000) + hue++; + + nextStep.set(10); // Step to (slightly) different color 100 times per second - whole cycle will take 255 steps *10ms = ~2.5 seconds. + + } + +} diff --git a/examples/arduino-move38-colorwheel/test/README b/examples/arduino-move38-colorwheel/test/README new file mode 100644 index 0000000..9b1e87b --- /dev/null +++ b/examples/arduino-move38-colorwheel/test/README @@ -0,0 +1,11 @@ + +This directory is intended for PlatformIO Test Runner and project tests. + +Unit Testing is a software testing method by which individual units of +source code, sets of one or more MCU program modules together with associated +control data, usage procedures, and operating procedures, are tested to +determine whether they are fit for use. Unit testing finds problems early +in the development cycle. + +More information about PlatformIO Unit Testing: +- https://docs.platformio.org/en/latest/advanced/unit-testing/index.html From ec8578e63c382cc5d0297ac55cfebe1bc4e82097 Mon Sep 17 00:00:00 2001 From: unknown Date: Tue, 1 Nov 2022 12:35:51 +0100 Subject: [PATCH 06/11] Add README --- examples/arduino-move38-colorwheel/README.md | Bin 38 -> 1416 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/examples/arduino-move38-colorwheel/README.md b/examples/arduino-move38-colorwheel/README.md index 9827b30ef9346684f98b12bdf6dd48d960a25461..7385647a68fc0a71c3c08caf8cedfd5ef30a35d3 100644 GIT binary patch literal 1416 zcmcJPPjAye5XI+=)bC&k4&@L>kRA{cm!?Q?B0}OqRTX1z5*Pnd>=59?1HU(okxc?p zB+$y<_0G)Bdv9j_so&#(Ke=u)oBzvC>}K8}~@8wcs8N`?cNi zmEw115A4N18#+zT6N|}uP493KHAFqPDI>#{@)ff;W|m`# zJ#vL#Lyi@krg)2az^1cGq8>Y@r;h0g>kd=}bK-hj^A7fzM|%ws0ec79-!n!;=2+I) zf_)*rbe{meW7t=F?=2OI9arf{4|xdxcz43-LN8Pa=r%+qyi>C0j#kMX$e@Mif z9eJxB5iz;fLkLuvuYSJzcC4YIAF-Pfaj5+okmg=N0UGYU!Ly@<{36Sq|ePFilWJKGI4R+78Yc zo Date: Tue, 1 Nov 2022 12:38:43 +0100 Subject: [PATCH 07/11] Update README --- examples/arduino-move38-colorwheel/README.md | Bin 1416 -> 2554 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/examples/arduino-move38-colorwheel/README.md b/examples/arduino-move38-colorwheel/README.md index 7385647a68fc0a71c3c08caf8cedfd5ef30a35d3..0084edfe6cc1c1c30de580feb198d0161a055364 100644 GIT binary patch literal 2554 zcmcJR+iDX55QgVk@EsN^c)+CCdLe=rwkr0b2do9LNV_K6bTucEjkP|!`u#Jz$!-#h z1!ZYBne+T}%CDbqZDd!LSiw87&o;B%`qt(15$_cG1)PZuY|jo|BDJYyE-{8avM+q= zAa~d9*o%Mm$eRA1SR1dWcpu`oAfi6cpQ79KSTp-%59|`@!p3Mlw@scdybj;m(3+X$ zaN4ffLvDspE0V|IEJeC)yZ|41Phh%N`Rn zb2yjqGW(AHz-2PxTNit;l%7$cw#PN_NLTYv{7q^L>xy1cr9?MDGv$8=@3}`SZ0d2h z?FXE3neDb``0Z$62>vgHBd~SNC zF01;AzJbOr6iKTd2|BsgLlLMl*KS{Z+r&`X_n>yrSjB!F9!>peiBQ+4VTi95QI8y} zZF|NyWuh8SsH5@|wpA{Qd#5%>t5c%b#^j>NCyrBH_rxn$_0)yuJiw2T&fLqYenLzw zP?3zVQiWzUJ9Yc@*rv#6dUK{c=Pe|M0`3MNK+$TS7Fteo>nZJRE>~F}Et-dpaz~ z%W{_|B{lYQV*6-n_ozb^sXA!lbEXaY63^P3lAb|tO32S6XgkO(YS*M}+ZL8rCHJxY zVGaGj-Y~yacG116t7auGM((|$4wBEP{klxsb1S+@szvM*O{TC4O>H@Oi;J;GrU@HD z*=lpBo9~x%5!xyA6FVm7!u?;f(T>ZVCbUCWNW}#AKuvpEGcmEp(6#kbxSF=ua|tzF z-oJ5Olwl6{zE|?RF`Z|`s@>d!caAN^ryVCv;S%U*^TtJz*CC%Hb8V5+x&OFwv-#u- zm9Vq!uKevy)K=K^7^63fHPz|@vJT(+rPTx|*Jae2_au% delta 7 Ocmew*+`+w}gB1V`NCMsf From eca782b302669ff95dfa9c8474448441443b7345 Mon Sep 17 00:00:00 2001 From: unknown Date: Tue, 1 Nov 2022 12:40:05 +0100 Subject: [PATCH 08/11] Update README --- examples/arduino-move38-colorwheel/README.md | Bin 2554 -> 2846 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/examples/arduino-move38-colorwheel/README.md b/examples/arduino-move38-colorwheel/README.md index 0084edfe6cc1c1c30de580feb198d0161a055364..f9af0af182e2b8d5cd503b34da1b7d9318461b60 100644 GIT binary patch delta 200 zcmew*JWp)H8CJ&V$){PRCr@D%5zS@DXDDMxWiV#2V9;Yo2J&(lG$%i0J*cU`P{NSG zPy`eyWk?6IApBGy9nDYx7S96eOJ*pU%+DezsK8LnP|lDE)RPQUo61l$`89iBa3(_@ zP$U(ozlb3b$jStomdBtEq*H*R`aqkD!FGapdO&?8K-+T|lu^xR&;^Po0##-MvF7Hb HY@y5mr!6e% delta 20 ccmbOy_Dguf8P>_?SfwTlu^rfaiamrG09-`~2><{9 From 796f6d6076abd4b3afe303489acfe43e9d4acc2b Mon Sep 17 00:00:00 2001 From: unknown Date: Tue, 1 Nov 2022 12:45:05 +0100 Subject: [PATCH 09/11] Less error-prone conversion --- builder/main.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/builder/main.py b/builder/main.py index 946c968..d5ddb28 100644 --- a/builder/main.py +++ b/builder/main.py @@ -107,7 +107,8 @@ def _rpi_sysgpio(path, value): PROGSUFFIX=".elf", ) -builtinbase = int(env.BoardConfig().get("build", {}).get("builtinbase", "0"), 16) +# Some Arduino cores need to relocate their firmware to a different address +builtinbase = env.BoardConfig().get("build", {}).get("builtinbase", "") env.Append( BUILDERS=dict( @@ -135,8 +136,8 @@ def _rpi_sysgpio(path, value): ElfToHex=Builder( action=env.VerboseAction( " ".join( - ["$OBJCOPY", "-O", "ihex", "-R", ".eeprom", "$SOURCES", "$TARGET"] if builtinbase == 0 else \ - ["$OBJCOPY", "--change-addresses", hex(builtinbase), "-O", "ihex", "-R", ".eepromm", "$SOURCES", "$TARGET"] + ["$OBJCOPY", "-O", "ihex", "-R", ".eeprom", "$SOURCES", "$TARGET"] if builtinbase == "" else \ + ["$OBJCOPY", "--change-addresses", builtinbase, "-O", "ihex", "-R", ".eeprom", "$SOURCES", "$TARGET"] ), "Building $TARGET", ), From e1851c35dbdfcec656fc38374e55aab5f64ea49a Mon Sep 17 00:00:00 2001 From: unknown Date: Tue, 1 Nov 2022 12:46:22 +0100 Subject: [PATCH 10/11] Remove SVD files again, not relevant now --- misc/svd/atmega1280.svd | 6463 ------------- misc/svd/atmega168.svd | 3030 ------ misc/svd/atmega2560.svd | 6318 ------------- misc/svd/atmega328p.svd | 3040 ------ misc/svd/atmega328pb.svd | 4127 --------- misc/svd/atmega32u4.svd | 4649 ---------- misc/svd/atmega4809.svd | 18369 ------------------------------------- misc/svd/atmega48p.svd | 2944 ------ misc/svd/atmega64.svd | 4326 --------- misc/svd/atmega644.svd | 3479 ------- misc/svd/atmega8.svd | 2775 ------ misc/svd/attiny84.svd | 1627 ---- misc/svd/attiny841.svd | 3309 ------- misc/svd/attiny85.svd | 1792 ---- misc/svd/attiny861.svd | 2354 ----- misc/svd/attiny88.svd | 2237 ----- 16 files changed, 70839 deletions(-) delete mode 100644 misc/svd/atmega1280.svd delete mode 100644 misc/svd/atmega168.svd delete mode 100644 misc/svd/atmega2560.svd delete mode 100644 misc/svd/atmega328p.svd delete mode 100644 misc/svd/atmega328pb.svd delete mode 100644 misc/svd/atmega32u4.svd delete mode 100644 misc/svd/atmega4809.svd delete mode 100644 misc/svd/atmega48p.svd delete mode 100644 misc/svd/atmega64.svd delete mode 100644 misc/svd/atmega644.svd delete mode 100644 misc/svd/atmega8.svd delete mode 100644 misc/svd/attiny84.svd delete mode 100644 misc/svd/attiny841.svd delete mode 100644 misc/svd/attiny85.svd delete mode 100644 misc/svd/attiny861.svd delete mode 100644 misc/svd/attiny88.svd diff --git a/misc/svd/atmega1280.svd b/misc/svd/atmega1280.svd deleted file mode 100644 index 1ba49c2..0000000 --- a/misc/svd/atmega1280.svd +++ /dev/null @@ -1,6463 +0,0 @@ - - Atmel - ATmega1280 - 8 - 8 - read-write - 0 - 0xff - - - AC - Analog Comparator - 0x50 - - - ACSR - Analog Comparator Control And Status Register - 0x0 - read-write - - - ACIS - Analog Comparator Interrupt Mode Select - [1:0] - - true - - ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 - - - ACIC - Analog Comparator Input Capture Enable - [2:2] - - - ACIE - Analog Comparator Interrupt Enable - [3:3] - - - ACI - Analog Comparator Interrupt Flag - [4:4] - - - ACO - Analog Compare Output - [5:5] - read-only - - ACBG - Analog Comparator Bandgap Select - [6:6] - - - ACD - Analog Comparator Disable - [7:7] - - - - - ADCSRB - ADC Control and Status Register B - 0x2B - - - ACME - Analog Comparator Multiplexer Enable - [6:6] - - - - - DIDR1 - Digital Input Disable Register 1 - 0x2F - - - AIN0D - AIN0 Digital Input Disable - [0:0] - - - AIN1D - AIN1 Digital Input Disable - [1:1] - - - - - - - ADC - Analog-to-Digital Converter - 0x78 - - - ADC - ADC Data Register Bytes - 0x0 - 16 - - - 0 - 65535 - - - - - ADCSRA - The ADC Control and Status register A - 0x2 - read-write - - - ADPS - ADC Prescaler Select Bits - [2:0] - - true - - ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 - - - ADIE - ADC Interrupt Enable - [3:3] - - - ADIF - ADC Interrupt Flag - [4:4] - - - ADATE - ADC Auto Trigger Enable - [5:5] - - - ADSC - ADC Start Conversion - [6:6] - - - ADEN - ADC Enable - [7:7] - - - - - ADCSRB - The ADC Control and Status register B - 0x3 - - - ADTS - ADC Auto Trigger Source bits - [2:0] - - true - - - - VAL_0x00 - Free Running mode - 0 - - - VAL_0x01 - Analog Comparator - 1 - - - VAL_0x02 - External Interrupt Request 0 - 2 - - - VAL_0x03 - Timer/Counter0 Compare Match A - 3 - - - VAL_0x04 - Timer/Counter0 Overflow - 4 - - - VAL_0x05 - Timer/Counter1 Compare Match B - 5 - - - VAL_0x06 - Timer/Counter1 Overflow - 6 - - - VAL_0x07 - Timer/Counter1 Capture Event - 7 - - - - - MUX5 - Analog Channel and Gain Selection Bits - [3:3] - - - ACME - <TBD> - [6:6] - - - - - ADMUX - The ADC multiplexer Selection Register - 0x4 - - - MUX - Analog Channel and Gain Selection Bits - [4:0] - - - 0 - 31 - - - - - ADLAR - Left Adjust Result - [5:5] - - - REFS - Reference Selection Bits - [7:6] - - true - - REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 - - - - - DIDR0 - Digital Input Disable Register - 0x6 - - - ADC0D - <TBD> - [0:0] - - - ADC1D - <TBD> - [1:1] - - - ADC2D - <TBD> - [2:2] - - - ADC3D - <TBD> - [3:3] - - - ADC4D - <TBD> - [4:4] - - - ADC5D - <TBD> - [5:5] - - - ADC6D - <TBD> - [6:6] - - - ADC7D - <TBD> - [7:7] - - - - - DIDR2 - Digital Input Disable Register - 0x5 - - - ADC8D - <TBD> - [0:0] - - - ADC9D - <TBD> - [1:1] - - - ADC10D - <TBD> - [2:2] - - - ADC11D - <TBD> - [3:3] - - - ADC12D - <TBD> - [4:4] - - - ADC13D - <TBD> - [5:5] - - - ADC14D - <TBD> - [6:6] - - - ADC15D - <TBD> - [7:7] - - - - - - - BOOT_LOAD - Bootloader - 0x57 - - - SPMCSR - Store Program Memory Control Register - 0x0 - - - SPMEN - Store Program Memory Enable - [0:0] - - - PGERS - Page Erase - [1:1] - - - PGWRT - Page Write - [2:2] - - - BLBSET - Boot Lock Bit Set - [3:3] - - - RWWSRE - Read While Write section read enable - [4:4] - - - SIGRD - Signature Row Read - [5:5] - - - RWWSB - Read While Write Section Busy - [6:6] - - - SPMIE - SPM Interrupt Enable - [7:7] - - - - - - - CPU - CPU Registers - 0x3E - - RESET - External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. - 0 - - - INT0 - External Interrupt Request 0 - 1 - - - INT1 - External Interrupt Request 1 - 2 - - - INT2 - External Interrupt Request 2 - 3 - - - INT3 - External Interrupt Request 3 - 4 - - - INT4 - External Interrupt Request 4 - 5 - - - INT5 - External Interrupt Request 5 - 6 - - - INT6 - External Interrupt Request 6 - 7 - - - INT7 - External Interrupt Request 7 - 8 - - - PCINT0 - Pin Change Interrupt Request 0 - 9 - - - PCINT1 - Pin Change Interrupt Request 1 - 10 - - - PCINT2 - Pin Change Interrupt Request 2 - 11 - - - WDT - Watchdog Time-out Interrupt - 12 - - - TIMER2_COMPA - Timer/Counter2 Compare Match A - 13 - - - TIMER2_COMPB - Timer/Counter2 Compare Match B - 14 - - - TIMER2_OVF - Timer/Counter2 Overflow - 15 - - - TIMER1_CAPT - Timer/Counter1 Capture Event - 16 - - - TIMER1_COMPA - Timer/Counter1 Compare Match A - 17 - - - TIMER1_COMPB - Timer/Counter1 Compare Match B - 18 - - - TIMER1_COMPC - Timer/Counter1 Compare Match C - 19 - - - TIMER1_OVF - Timer/Counter1 Overflow - 20 - - - TIMER0_COMPA - Timer/Counter0 Compare Match A - 21 - - - TIMER0_COMPB - Timer/Counter0 Compare Match B - 22 - - - TIMER0_OVF - Timer/Counter0 Overflow - 23 - - - SPI_STC - SPI Serial Transfer Complete - 24 - - - USART0_RX - USART0, Rx Complete - 25 - - - USART0_UDRE - USART0 Data register Empty - 26 - - - USART0_TX - USART0, Tx Complete - 27 - - - ANALOG_COMP - Analog Comparator - 28 - - - ADC - ADC Conversion Complete - 29 - - - EE_READY - EEPROM Ready - 30 - - - TIMER3_CAPT - Timer/Counter3 Capture Event - 31 - - - TIMER3_COMPA - Timer/Counter3 Compare Match A - 32 - - - TIMER3_COMPB - Timer/Counter3 Compare Match B - 33 - - - TIMER3_COMPC - Timer/Counter3 Compare Match C - 34 - - - TIMER3_OVF - Timer/Counter3 Overflow - 35 - - - USART1_RX - USART1, Rx Complete - 36 - - - USART1_UDRE - USART1 Data register Empty - 37 - - - USART1_TX - USART1, Tx Complete - 38 - - - TWI - 2-wire Serial Interface - 39 - - - SPM_READY - Store Program Memory Read - 40 - - - TIMER4_CAPT - Timer/Counter4 Capture Event - 41 - - - TIMER4_COMPA - Timer/Counter4 Compare Match A - 42 - - - TIMER4_COMPB - Timer/Counter4 Compare Match B - 43 - - - TIMER4_COMPC - Timer/Counter4 Compare Match C - 44 - - - TIMER4_OVF - Timer/Counter4 Overflow - 45 - - - TIMER5_CAPT - Timer/Counter5 Capture Event - 46 - - - TIMER5_COMPA - Timer/Counter5 Compare Match A - 47 - - - TIMER5_COMPB - Timer/Counter5 Compare Match B - 48 - - - TIMER5_COMPC - Timer/Counter5 Compare Match C - 49 - - - TIMER5_OVF - Timer/Counter5 Overflow - 50 - - - USART2_RX - USART2, Rx Complete - 51 - - - USART2_UDRE - USART2 Data register Empty - 52 - - - USART2_TX - USART2, Tx Complete - 53 - - - USART3_RX - USART3, Rx Complete - 54 - - - USART3_UDRE - USART3 Data register Empty - 55 - - - USART3_TX - USART3, Tx Complete - 56 - - - - CLKPR - <TBD> - 0x23 - - - CLKPS - <TBD> - [3:0] - - true - - - - VAL_0x00 - 1 - 0 - - - VAL_0x01 - 2 - 1 - - - VAL_0x02 - 4 - 2 - - - VAL_0x03 - 8 - 3 - - - VAL_0x04 - 16 - 4 - - - VAL_0x05 - 32 - 5 - - - VAL_0x06 - 64 - 6 - - - VAL_0x07 - 128 - 7 - - - VAL_0x08 - 256 - 8 - - - - - CLKPCE - <TBD> - [7:7] - - - - - EIND - Extended Indirect Register - 0x1E - - - 0 - 255 - - - - - GPIOR0 - General Purpose IO Register 0 - 0x0 - - - GPIOR00 - General Purpose IO Register 0 bit 0 - [0:0] - - - GPIOR01 - General Purpose IO Register 0 bit 1 - [1:1] - - - GPIOR02 - General Purpose IO Register 0 bit 2 - [2:2] - - - GPIOR03 - General Purpose IO Register 0 bit 3 - [3:3] - - - GPIOR04 - General Purpose IO Register 0 bit 4 - [4:4] - - - GPIOR05 - General Purpose IO Register 0 bit 5 - [5:5] - - - GPIOR06 - General Purpose IO Register 0 bit 6 - [6:6] - - - GPIOR07 - General Purpose IO Register 0 bit 7 - [7:7] - - - - - GPIOR1 - General Purpose IO Register 1 - 0xC - - - GPIOR - General Purpose IO Register 1 bis - [7:0] - - - 0 - 255 - - - - - - - GPIOR2 - General Purpose IO Register 2 - 0xD - - - GPIOR - General Purpose IO Register 2 bis - [7:0] - - - 0 - 255 - - - - - - - MCUCR - MCU Control Register - 0x17 - - - IVCE - Interrupt Vector Change Enable - [0:0] - - - IVSEL - Interrupt Vector Select - [1:1] - - - PUD - Pull-up disable - [4:4] - - - JTD - JTAG Interface Disable - [7:7] - - - - - MCUSR - MCU Status Register - 0x16 - read-only - - - PORF - Power-on reset flag - [0:0] - - - EXTRF - External Reset Flag - [1:1] - - - BORF - Brown-out Reset Flag - [2:2] - - - WDRF - Watchdog Reset Flag - [3:3] - - - JTRF - JTAG Reset Flag - [4:4] - - - - - OSCCAL - Oscillator Calibration Value - 0x28 - - - OSCCAL - Oscillator Calibration - [7:0] - - - 0 - 255 - - - - - - - PRR0 - Power Reduction Register0 - 0x26 - - - PRADC - Power Reduction ADC - [0:0] - - - PRUSART0 - Power Reduction USART0 - [1:1] - - - PRSPI - Power Reduction Serial Peripheral Interface - [2:2] - - - PRTIM1 - Power Reduction Timer/Counter1 - [3:3] - - - PRTIM0 - Power Reduction Timer/Counter0 - [5:5] - - - PRTIM2 - Power Reduction Timer/Counter2 - [6:6] - - - PRTWI - Power Reduction TWI - [7:7] - - - - - PRR1 - Power Reduction Register1 - 0x27 - - - PRUSART1 - Power Reduction USART1 - [0:0] - - - PRUSART2 - Power Reduction USART2 - [1:1] - - - PRUSART3 - Power Reduction USART3 - [2:2] - - - PRTIM3 - Power Reduction Timer/Counter3 - [3:3] - - - PRTIM4 - Power Reduction Timer/Counter4 - [4:4] - - - PRTIM5 - Power Reduction Timer/Counter5 - [5:5] - - - - - RAMPZ - RAM Page Z Select Register - 0x1D - - - 0 - 255 - - - - - SMCR - Sleep Mode Control Register - 0x15 - - - SE - Sleep Enable - [0:0] - - - SM - Sleep Mode Select bits - [3:1] - - true - - - - IDLE - Idle - 0 - - - ADC - ADC Noise Reduction (If Available) - 1 - - - PDOWN - Power Down - 2 - - - PSAVE - Power Save - 3 - - - VAL_0x04 - Reserved - 4 - - - VAL_0x05 - Reserved - 5 - - - STDBY - Standby - 6 - - - ESTDBY - Extended Standby - 7 - - - - - - - XMCRA - External Memory Control Register A - 0x36 - - - SRW0 - Wait state select bit lower page - [1:0] - - true - - - - VAL_0x00 - No wait-states - 0 - - - VAL_0x01 - Wait one cycle during read/write strobe - 1 - - - VAL_0x02 - Wait two cycles during read/write strobe - 2 - - - VAL_0x03 - Wait two cycles during read/write and wait one cycle before driving out new address - 3 - - - - - SRW1 - Wait state select bit upper page - [3:2] - - true - - - - VAL_0x00 - No wait-states - 0 - - - VAL_0x01 - Wait one cycle during read/write strobe - 1 - - - VAL_0x02 - Wait two cycles during read/write strobe - 2 - - - VAL_0x03 - Wait two cycles during read/write and wait one cycle before driving out new address - 3 - - - - - SRL - Wait state page limit - [6:4] - - true - - - - VAL_0x00 - LS = N/A, US = 0x1100 - 0xFFFF - 0 - - - VAL_0x01 - LS = 0x2200 - 0x1FFF, US = 0x2000 - 0xFFFF - 1 - - - VAL_0x02 - LS = 0x2200 - 0x3FFF, US = 0x4000 - 0xFFFF - 2 - - - VAL_0x03 - LS = 0x2200 - 0x5FFF, US = 0x6000 - 0xFFFF - 3 - - - VAL_0x04 - LS = 0x2200 - 0x7FFF, US = 0x8000 - 0xFFFF - 4 - - - VAL_0x05 - LS = 0x2200 - 0x9FFF, US = 0xA000 - 0xFFFF - 5 - - - VAL_0x06 - LS = 0x2200 - 0xBFFF, US = 0xC000 - 0xFFFF - 6 - - - VAL_0x07 - LS = 0x2200 - 0xDFFF, US = 0xE000 - 0xFFFF - 7 - - - - - SRE - External SRAM Enable - [7:7] - - - - - XMCRB - External Memory Control Register B - 0x37 - - - XMM - External Memory High Mask - [2:0] - - - 0 - 7 - - - - - XMBK - External Memory Bus Keeper Enable - [7:7] - - - - - - - EEPROM - EEPROM - 0x3F - - - EEAR - EEPROM Address Register Low Bytes - 0x2 - 16 - - - 0 - 65535 - - - - - EECR - EEPROM Control Register - 0x0 - - - EERE - EEPROM Read Enable - [0:0] - - - EEPE - EEPROM Write Enable - [1:1] - - - EEMPE - EEPROM Master Write Enable - [2:2] - - - EERIE - EEPROM Ready Interrupt Enable - [3:3] - - - EEPM - EEPROM Programming Mode Bits - [5:4] - - true - - - - VAL_0x00 - Erase and Write in one operation - 0 - - - VAL_0x01 - Erase Only - 1 - - - VAL_0x02 - Write Only - 2 - - - - - - - EEDR - EEPROM Data Register - 0x1 - - - 0 - 255 - - - - - - - EXINT - External Interrupts - 0x3B - - - EICRA - External Interrupt Control Register A - 0x2E - - - ISC0 - External Interrupt Sense Control Bit - [1:0] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC1 - External Interrupt Sense Control Bit - [3:2] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC2 - External Interrupt Sense Control Bit - [5:4] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC3 - External Interrupt Sense Control Bit - [7:6] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - - - EICRB - External Interrupt Control Register B - 0x2F - - - ISC4 - External Interrupt 7-4 Sense Control Bit - [1:0] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC5 - External Interrupt 7-4 Sense Control Bit - [3:2] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC6 - External Interrupt 7-4 Sense Control Bit - [5:4] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC7 - External Interrupt 7-4 Sense Control Bit - [7:6] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - - - EIFR - External Interrupt Flag Register - 0x1 - read-only - - - INTF - External Interrupt Flags - [7:0] - - - 0 - 255 - - - - - - - EIMSK - External Interrupt Mask Register - 0x2 - - - INT - External Interrupt Request 7 Enable - [7:0] - - - 0 - 255 - - - - - - - PCICR - Pin Change Interrupt Control Register - 0x2D - - - PCIE - Pin Change Interrupt Enables - [2:0] - - - 0 - 7 - - - - - - - PCIFR - Pin Change Interrupt Flag Register - 0x0 - read-only - - - PCIF - Pin Change Interrupt Flags - [2:0] - - - 0 - 7 - - - - - - - PCMSK0 - Pin Change Mask Register 0 - 0x30 - - - PCINT - Pin Change Enable bits - [7:0] - - - 0 - 255 - - - - - - - PCMSK1 - Pin Change Mask Register 1 - 0x31 - - - PCINT - Pin Change Enable bits - [7:0] - - - 0 - 255 - - - - - - - PCMSK2 - Pin Change Mask Register 2 - 0x32 - - - PCINT - Pin Change Enable bits - [7:0] - - - 0 - 255 - - - - - - - - - FUSE - Fuses - 0x0 - - - EXTENDED - <TBD> - 0x2 - - - BODLEVEL - Brown-out Detector trigger level - [2:0] - - true - - - - 4V3 - Brown-out detection at VCC=4.3 V - 4 - - - 2V7 - Brown-out detection at VCC=2.7 V - 5 - - - 1V8 - Brown-out detection at VCC=1.8 V - 6 - - - DISABLED - Brown-out detection disabled - 7 - - - - - - - HIGH - <TBD> - 0x1 - - - BOOTRST - Boot Reset vector Enabled - [0:0] - - - BOOTSZ - Select Boot Size - [2:1] - - true - - - - 4096W_F000 - Boot Flash size=4096 words start address=$F000 - 0 - - - 2048W_F800 - Boot Flash size=2048 words start address=$F800 - 1 - - - 1024W_FC00 - Boot Flash size=1024 words start address=$FC00 - 2 - - - 512W_FE00 - Boot Flash size=512 words start address=$FE00 - 3 - - - - - EESAVE - Preserve EEPROM through the Chip Erase cycle - [3:3] - - - WDTON - Watchdog timer always on - [4:4] - - - SPIEN - Serial program downloading (SPI) enabled - [5:5] - - - JTAGEN - JTAG Interface Enabled - [6:6] - - - OCDEN - On-Chip Debug Enabled - [7:7] - - - - - LOW - <TBD> - 0x0 - - - SUT_CKSEL - Select Clock Source - [5:0] - - true - - - - EXTCLK_6CK_0MS - Ext. Clock; Start-up time: 6 CK + 0 ms - 0 - - - INTRCOSC_6CK_0MS - Int. RC Osc.; Start-up time: 6 CK + 0 ms - 2 - - - INTRCOSC_128KHZ_6CK_0MS - Int. 128kHz RC Osc.; Start-up time: 6 CK + 0 ms - 3 - - - EXTLOFXTAL_1KCK_0MS - Ext. Low-Freq. Crystal; Start-up time: 1K CK + 0 ms - 4 - - - EXTLOFXTAL_32KCK_0MS - Ext. Low-Freq. Crystal; Start-up time: 32K CK + 0 ms - 5 - - - FSOSC_258CK_4MS1_CRES_FASTPWR - Full Swing Oscillator; Start-up time: 258 CK + 4.1 ms; Ceramic res.; fast rising power - 6 - - - FSOSC_1KCK_65MS_CRES_SLOWPWR - Full Swing Oscillator; Start-up time: 1K CK + 65 ms; Ceramic res.; slowly rising power - 7 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 258 CK + 4.1 ms - 8 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 65 ms - 9 - - - EXTXOSC_0MHZ9_3MHZ_258CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 258 CK + 4.1 ms - 10 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 65 ms - 11 - - - EXTXOSC_3MHZ_8MHZ_258CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 258 CK + 4.1 ms - 12 - - - EXTXOSC_3MHZ_8MHZ_1KCK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 65 ms - 13 - - - EXTXOSC_8MHZ_XX_258CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time: 258 CK + 4.1 ms - 14 - - - EXTXOSC_8MHZ_XX_1KCK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 65 ms - 15 - - - EXTCLK_6CK_4MS1 - Ext. Clock; Start-up time: 6 CK + 4.1 ms - 16 - - - INTRCOSC_6CK_4MS1 - Int. RC Osc.; Start-up time: 6 CK + 4.1 ms - 18 - - - INTRCOSC_128KHZ_6CK_4MS - Int. 128kHz RC Osc.; Start-up time: 6 CK + 4 ms - 19 - - - EXTLOFXTAL_1KCK_4MS1 - Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4.1 ms - 20 - - - EXTLOFXTAL_32KCK_4MS1 - Ext. Low-Freq. Crystal; Start-up time: 32K CK + 4.1 ms - 21 - - - FSOSC_258CK_65MS_CRES_SLOWPWR - Full Swing Oscillator; Start-up time: 258 CK + 65 ms; Ceramic res.; slowly rising power - 22 - - - FSOSC_16KCK_0MS_XOSC_BODEN - Full Swing Oscillator; Start-up time: 16K CK + 0 ms; Crystal Osc.; BOD enabled - 23 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 258 CK + 65 ms - 24 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 0 ms - 25 - - - EXTXOSC_0MHZ9_3MHZ_258CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 258 CK + 65 ms - 26 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 0 ms - 27 - - - EXTXOSC_3MHZ_8MHZ_258CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 258 CK + 65 ms - 28 - - - EXTXOSC_3MHZ_8MHZ_16KCK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 0 ms - 29 - - - EXTXOSC_8MHZ_XX_258CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 258 CK + 65 ms - 30 - - - EXTXOSC_8MHZ_XX_16KCK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 0 ms - 31 - - - EXTCLK_6CK_65MS - Ext. Clock; Start-up time: 6 CK + 65 ms - 32 - - - INTRCOSC_6CK_65MS - Int. RC Osc.; Start-up time: 6 CK + 65 ms - 34 - - - INTRCOSC_128KHZ_6CK_64MS - Int. 128kHz RC Osc.; Start-up time: 6 CK + 64 ms - 35 - - - EXTLOFXTAL_1KCK_65MS - Ext. Low-Freq. Crystal; Start-up time: 1K CK + 65 ms - 36 - - - EXTLOFXTAL_32KCK_65MS - Ext. Low-Freq. Crystal; Start-up time: 32K CK + 65 ms - 37 - - - FSOSC_1KCK_0MS_CRES_BODEN - Full Swing Oscillator; Start-up time: 1K CK + 0 ms; Ceramic res.; BOD enable - 38 - - - FSOSC_16KCK_4MS1_XOSC_FASTPWR - Full Swing Oscillator; Start-up time: 16K CK + 4.1 ms; Crystal Osc.; fast rising power - 39 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 0 ms - 40 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 4.1 ms - 41 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 0 ms - 42 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 4.1 ms - 43 - - - EXTXOSC_3MHZ_8MHZ_1KCK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 0 ms - 44 - - - EXTXOSC_3MHZ_8MHZ_16KCK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 4.1 ms - 45 - - - EXTXOSC_8MHZ_XX_1KCK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 0 ms - 46 - - - EXTXOSC_8MHZ_XX_16KCK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 4.1 ms - 47 - - - FSOSC_1KCK_4MS1_CRES_FASTPWR - Full Swing Oscillator; Start-up time: 1K CK + 4.1 ms; Ceramic res.; fast rising power - 54 - - - FSOSC_16KCK_65MS_XOSC_SLOWPWR - Full Swing Oscillator; Start-up time: 16K CK + 65 ms; Crystal Osc.; slowly rising power - 55 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 4.1 ms - 56 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 65 ms - 57 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 4.1 ms - 58 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 65 ms - 59 - - - EXTXOSC_3MHZ_8MHZ_1KCK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 4.1 ms - 60 - - - EXTXOSC_3MHZ_8MHZ_16KCK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 65 ms - 61 - - - EXTXOSC_8MHZ_XX_1KCK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 4.1 ms - 62 - - - EXTXOSC_8MHZ_XX_16KCK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 65 ms - 63 - - - - - CKOUT - Clock output on PORTE7 - [6:6] - - - CKDIV8 - Divide clock by 8 internally - [7:7] - - - - - - - JTAG - JTAG Interface - 0x51 - - - MCUCR - MCU Control Register - 0x4 - - - JTD - JTAG Interface Disable - [7:7] - - - - - MCUSR - MCU Status Register - 0x3 - read-only - - - JTRF - JTAG Reset Flag - [4:4] - - - - - OCDR - On-Chip Debug Related Register in I/O Memory - 0x0 - - - 0 - 255 - - - - - - - LOCKBIT - Lockbits - 0x0 - - - LOCKBIT - <TBD> - 0x0 - - - LB - Memory Lock - [1:0] - - true - - - - PROG_VER_DISABLED - Further programming and verification disabled - 0 - - - PROG_DISABLED - Further programming disabled - 2 - - - NO_LOCK - No memory lock features enabled - 3 - - - - - BLB0 - Boot Loader Protection Mode - [3:2] - - true - - - - LPM_SPM_DISABLE - LPM and SPM prohibited in Application Section - 0 - - - LPM_DISABLE - LPM prohibited in Application Section - 1 - - - SPM_DISABLE - SPM prohibited in Application Section - 2 - - - NO_LOCK - No lock on SPM and LPM in Application Section - 3 - - - - - BLB1 - Boot Loader Protection Mode - [5:4] - - true - - - - LPM_SPM_DISABLE - LPM and SPM prohibited in Boot Section - 0 - - - LPM_DISABLE - LPM prohibited in Boot Section - 1 - - - SPM_DISABLE - SPM prohibited in Boot Section - 2 - - - NO_LOCK - No lock on SPM and LPM in Boot Section - 3 - - - - - - - - - PORTA - I/O Port - 0x20 - - - DDRA - Port A Data Direction Register - 0x1 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - PINA - Port A Input Pins - 0x0 - read-write - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - PORTA - Port A Data Register - 0x2 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - - - PORTB - I/O Port - 0x23 - - - DDRB - Port B Data Direction Register - 0x1 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PINB - Port B Input Pins - 0x0 - read-write - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PORTB - Port B Data Register - 0x2 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - - - PORTC - I/O Port - 0x26 - - - DDRC - Port C Data Direction Register - 0x1 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - PINC - Port C Input Pins - 0x0 - read-write - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - PORTC - Port C Data Register - 0x2 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - - - PORTD - I/O Port - 0x29 - - - DDRD - Port D Data Direction Register - 0x1 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PIND - Port D Input Pins - 0x0 - read-write - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PORTD - Port D Data Register - 0x2 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - - - PORTE - I/O Port - 0x2C - - - DDRE - Data Direction Register, Port E - 0x1 - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - PE4 - Pin E4 - [4:4] - - - PE5 - Pin E5 - [5:5] - - - PE6 - Pin E6 - [6:6] - - - PE7 - Pin E7 - [7:7] - - - - - PINE - Input Pins, Port E - 0x0 - read-write - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - PE4 - Pin E4 - [4:4] - - - PE5 - Pin E5 - [5:5] - - - PE6 - Pin E6 - [6:6] - - - PE7 - Pin E7 - [7:7] - - - - - PORTE - Data Register, Port E - 0x2 - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - PE4 - Pin E4 - [4:4] - - - PE5 - Pin E5 - [5:5] - - - PE6 - Pin E6 - [6:6] - - - PE7 - Pin E7 - [7:7] - - - - - - - PORTF - I/O Port - 0x2F - - - DDRF - Data Direction Register, Port F - 0x1 - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF2 - Pin F2 - [2:2] - - - PF3 - Pin F3 - [3:3] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - PF7 - Pin F7 - [7:7] - - - - - PINF - Input Pins, Port F - 0x0 - read-write - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF2 - Pin F2 - [2:2] - - - PF3 - Pin F3 - [3:3] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - PF7 - Pin F7 - [7:7] - - - - - PORTF - Data Register, Port F - 0x2 - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF2 - Pin F2 - [2:2] - - - PF3 - Pin F3 - [3:3] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - PF7 - Pin F7 - [7:7] - - - - - - - PORTG - I/O Port - 0x32 - - - DDRG - Data Direction Register, Port G - 0x1 - - - PG0 - Pin G0 - [0:0] - - - PG1 - Pin G1 - [1:1] - - - PG2 - Pin G2 - [2:2] - - - PG3 - Pin G3 - [3:3] - - - PG4 - Pin G4 - [4:4] - - - PG5 - Pin G5 - [5:5] - - - PG6 - Pin G6 - [6:6] - - - PG7 - Pin G7 - [7:7] - - - - - PING - Input Pins, Port G - 0x0 - read-write - - PG0 - Pin G0 - [0:0] - - - PG1 - Pin G1 - [1:1] - - - PG2 - Pin G2 - [2:2] - - - PG3 - Pin G3 - [3:3] - - - PG4 - Pin G4 - [4:4] - - - PG5 - Pin G5 - [5:5] - - - PG6 - Pin G6 - [6:6] - - - PG7 - Pin G7 - [7:7] - - - - - PORTG - Data Register, Port G - 0x2 - - - PG0 - Pin G0 - [0:0] - - - PG1 - Pin G1 - [1:1] - - - PG2 - Pin G2 - [2:2] - - - PG3 - Pin G3 - [3:3] - - - PG4 - Pin G4 - [4:4] - - - PG5 - Pin G5 - [5:5] - - - PG6 - Pin G6 - [6:6] - - - PG7 - Pin G7 - [7:7] - - - - - - - PORTH - I/O Port - 0x100 - - - DDRH - PORT H Data Direction Register - 0x1 - - - PH0 - Pin H0 - [0:0] - - - PH1 - Pin H1 - [1:1] - - - PH2 - Pin H2 - [2:2] - - - PH3 - Pin H3 - [3:3] - - - PH4 - Pin H4 - [4:4] - - - PH5 - Pin H5 - [5:5] - - - PH6 - Pin H6 - [6:6] - - - PH7 - Pin H7 - [7:7] - - - - - PINH - PORT H Input Pins - 0x0 - read-write - - PH0 - Pin H0 - [0:0] - - - PH1 - Pin H1 - [1:1] - - - PH2 - Pin H2 - [2:2] - - - PH3 - Pin H3 - [3:3] - - - PH4 - Pin H4 - [4:4] - - - PH5 - Pin H5 - [5:5] - - - PH6 - Pin H6 - [6:6] - - - PH7 - Pin H7 - [7:7] - - - - - PORTH - PORT H Data Register - 0x2 - - - PH0 - Pin H0 - [0:0] - - - PH1 - Pin H1 - [1:1] - - - PH2 - Pin H2 - [2:2] - - - PH3 - Pin H3 - [3:3] - - - PH4 - Pin H4 - [4:4] - - - PH5 - Pin H5 - [5:5] - - - PH6 - Pin H6 - [6:6] - - - PH7 - Pin H7 - [7:7] - - - - - - - PORTJ - I/O Port - 0x103 - - - DDRJ - PORT J Data Direction Register - 0x1 - - - PJ0 - Pin J0 - [0:0] - - - PJ1 - Pin J1 - [1:1] - - - PJ2 - Pin J2 - [2:2] - - - PJ3 - Pin J3 - [3:3] - - - PJ4 - Pin J4 - [4:4] - - - PJ5 - Pin J5 - [5:5] - - - PJ6 - Pin J6 - [6:6] - - - PJ7 - Pin J7 - [7:7] - - - - - PINJ - PORT J Input Pins - 0x0 - read-write - - PJ0 - Pin J0 - [0:0] - - - PJ1 - Pin J1 - [1:1] - - - PJ2 - Pin J2 - [2:2] - - - PJ3 - Pin J3 - [3:3] - - - PJ4 - Pin J4 - [4:4] - - - PJ5 - Pin J5 - [5:5] - - - PJ6 - Pin J6 - [6:6] - - - PJ7 - Pin J7 - [7:7] - - - - - PORTJ - PORT J Data Register - 0x2 - - - PJ0 - Pin J0 - [0:0] - - - PJ1 - Pin J1 - [1:1] - - - PJ2 - Pin J2 - [2:2] - - - PJ3 - Pin J3 - [3:3] - - - PJ4 - Pin J4 - [4:4] - - - PJ5 - Pin J5 - [5:5] - - - PJ6 - Pin J6 - [6:6] - - - PJ7 - Pin J7 - [7:7] - - - - - - - PORTK - I/O Port - 0x106 - - - DDRK - PORT K Data Direction Register - 0x1 - - - PK0 - Pin K0 - [0:0] - - - PK1 - Pin K1 - [1:1] - - - PK2 - Pin K2 - [2:2] - - - PK3 - Pin K3 - [3:3] - - - PK4 - Pin K4 - [4:4] - - - PK5 - Pin K5 - [5:5] - - - PK6 - Pin K6 - [6:6] - - - PK7 - Pin K7 - [7:7] - - - - - PINK - PORT K Input Pins - 0x0 - read-write - - PK0 - Pin K0 - [0:0] - - - PK1 - Pin K1 - [1:1] - - - PK2 - Pin K2 - [2:2] - - - PK3 - Pin K3 - [3:3] - - - PK4 - Pin K4 - [4:4] - - - PK5 - Pin K5 - [5:5] - - - PK6 - Pin K6 - [6:6] - - - PK7 - Pin K7 - [7:7] - - - - - PORTK - PORT K Data Register - 0x2 - - - PK0 - Pin K0 - [0:0] - - - PK1 - Pin K1 - [1:1] - - - PK2 - Pin K2 - [2:2] - - - PK3 - Pin K3 - [3:3] - - - PK4 - Pin K4 - [4:4] - - - PK5 - Pin K5 - [5:5] - - - PK6 - Pin K6 - [6:6] - - - PK7 - Pin K7 - [7:7] - - - - - - - PORTL - I/O Port - 0x109 - - - DDRL - PORT L Data Direction Register - 0x1 - - - PL0 - Pin L0 - [0:0] - - - PL1 - Pin L1 - [1:1] - - - PL2 - Pin L2 - [2:2] - - - PL3 - Pin L3 - [3:3] - - - PL4 - Pin L4 - [4:4] - - - PL5 - Pin L5 - [5:5] - - - PL6 - Pin L6 - [6:6] - - - PL7 - Pin L7 - [7:7] - - - - - PINL - PORT L Input Pins - 0x0 - read-write - - PL0 - Pin L0 - [0:0] - - - PL1 - Pin L1 - [1:1] - - - PL2 - Pin L2 - [2:2] - - - PL3 - Pin L3 - [3:3] - - - PL4 - Pin L4 - [4:4] - - - PL5 - Pin L5 - [5:5] - - - PL6 - Pin L6 - [6:6] - - - PL7 - Pin L7 - [7:7] - - - - - PORTL - PORT L Data Register - 0x2 - - - PL0 - Pin L0 - [0:0] - - - PL1 - Pin L1 - [1:1] - - - PL2 - Pin L2 - [2:2] - - - PL3 - Pin L3 - [3:3] - - - PL4 - Pin L4 - [4:4] - - - PL5 - Pin L5 - [5:5] - - - PL6 - Pin L6 - [6:6] - - - PL7 - Pin L7 - [7:7] - - - - - - - SPI - Serial Peripheral Interface - 0x4C - - - SPCR - SPI Control Register - 0x0 - - - SPR - SPI Clock Rate Selects - [1:0] - - true - - SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 - - - CPHA - Clock Phase - [2:2] - - - CPOL - Clock polarity - [3:3] - - - MSTR - Master/Slave Select - [4:4] - - - DORD - Data Order - [5:5] - - - SPE - SPI Enable - [6:6] - - - SPIE - SPI Interrupt Enable - [7:7] - - - - - SPDR - SPI Data Register - 0x2 - - - 0 - 255 - - - - - SPSR - SPI Status Register - 0x1 - read-write - - - SPI2X - Double SPI Speed Bit - [0:0] - read-write - - WCOL - Write Collision Flag - [6:6] - read-only - - SPIF - SPI Interrupt Flag - [7:7] - read-only - - - - - - TC0 - Timer/Counter, 8-bit - 0x35 - - - GTCCR - General Timer/Counter Control Register - 0xE - - - PSRSYNC - Prescaler Reset Timer/Counter1 and Timer/Counter0 - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - OCR0A - Timer/Counter0 Output Compare Register - 0x12 - - - 0 - 255 - - - - - OCR0B - Timer/Counter0 Output Compare Register - 0x13 - - - 0 - 255 - - - - - TCCR0A - Timer/Counter Control Register A - 0xF - - - WGM0 - Waveform Generation Mode - [1:0] - - - 0 - 3 - - - - - COM0B - Compare Output Mode, Fast PWm - [5:4] - - - 0 - 3 - - - - - COM0A - Compare Output Mode, Phase Correct PWM Mode - [7:6] - - - 0 - 3 - - - - - - - TCCR0B - Timer/Counter Control Register B - 0x10 - - - CS0 - Clock Select - [2:0] - - true - - - - VAL_0x00 - No Clock Source (Stopped) - 0 - - - VAL_0x01 - Running, No Prescaling - 1 - - - VAL_0x02 - Running, CLK/8 - 2 - - - VAL_0x03 - Running, CLK/64 - 3 - - - VAL_0x04 - Running, CLK/256 - 4 - - - VAL_0x05 - Running, CLK/1024 - 5 - - - VAL_0x06 - Running, ExtClk Tx Falling Edge - 6 - - - VAL_0x07 - Running, ExtClk Tx Rising Edge - 7 - - - - - WGM02 - <TBD> - [3:3] - - - FOC0B - Force Output Compare B - [6:6] - - - FOC0A - Force Output Compare A - [7:7] - - - - - TCNT0 - Timer/Counter0 - 0x11 - - - 0 - 255 - - - - - TIFR0 - Timer/Counter0 Interrupt Flag register - 0x0 - read-only - - - TOV0 - Timer/Counter0 Overflow Flag - [0:0] - - - OCF0A - Timer/Counter0 Output Compare Flag 0A - [1:1] - - - OCF0B - Timer/Counter0 Output Compare Flag 0B - [2:2] - - - - - TIMSK0 - Timer/Counter0 Interrupt Mask Register - 0x39 - - - TOIE0 - Timer/Counter0 Overflow Interrupt Enable - [0:0] - - - OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable - [2:2] - - - - - - - TC1 - Timer/Counter, 16-bit - 0x36 - - - ICR1 - Timer/Counter1 Input Capture Register Bytes - 0x50 - 16 - - - 0 - 65535 - - - - - OCR1A - Timer/Counter1 Output Compare Register A Bytes - 0x52 - 16 - - - 0 - 65535 - - - - - OCR1B - Timer/Counter1 Output Compare Register B Bytes - 0x54 - 16 - - - 0 - 65535 - - - - - OCR1C - Timer/Counter1 Output Compare Register C Bytes - 0x56 - 16 - - - 0 - 65535 - - - - - TCCR1A - Timer/Counter1 Control Register A - 0x4A - - - WGM1 - Waveform Generation Mode - [1:0] - - - 0 - 3 - - - - - COM1C - Compare Output Mode 1C, bits - [3:2] - - - 0 - 3 - - - - - COM1B - Compare Output Mode 1B, bits - [5:4] - - - 0 - 3 - - - - - COM1A - Compare Output Mode 1A, bits - [7:6] - - - 0 - 3 - - - - - - - TCCR1B - Timer/Counter1 Control Register B - 0x4B - - - CS1 - Prescaler source of Timer/Counter 1 - [2:0] - - true - - - - VAL_0x00 - No Clock Source (Stopped) - 0 - - - VAL_0x01 - Running, No Prescaling - 1 - - - VAL_0x02 - Running, CLK/8 - 2 - - - VAL_0x03 - Running, CLK/64 - 3 - - - VAL_0x04 - Running, CLK/256 - 4 - - - VAL_0x05 - Running, CLK/1024 - 5 - - - VAL_0x06 - Running, ExtClk Tx Falling Edge - 6 - - - VAL_0x07 - Running, ExtClk Tx Rising Edge - 7 - - - - - WGM1 - Waveform Generation Mode - [4:3] - - - 0 - 3 - - - - - ICES1 - Input Capture 1 Edge Select - [6:6] - - - ICNC1 - Input Capture 1 Noise Canceler - [7:7] - - - - - TCCR1C - Timer/Counter 1 Control Register C - 0x4C - - - FOC1C - Force Output Compare 1C - [5:5] - - - FOC1B - Force Output Compare 1B - [6:6] - - - FOC1A - Force Output Compare 1A - [7:7] - - - - - TCNT1 - Timer/Counter1 Bytes - 0x4E - 16 - - - 0 - 65535 - - - - - TIFR1 - Timer/Counter1 Interrupt Flag register - 0x0 - read-only - - - TOV1 - Timer/Counter1 Overflow Flag - [0:0] - - - OCF1A - Output Compare Flag 1A - [1:1] - - - OCF1B - Output Compare Flag 1B - [2:2] - - - OCF1C - Output Compare Flag 1C - [3:3] - - - ICF1 - Input Capture Flag 1 - [5:5] - - - - - TIMSK1 - Timer/Counter1 Interrupt Mask Register - 0x39 - - - TOIE1 - Timer/Counter1 Overflow Interrupt Enable - [0:0] - - - OCIE1A - Timer/Counter1 Output Compare A Match Interrupt Enable - [1:1] - - - OCIE1B - Timer/Counter1 Output Compare B Match Interrupt Enable - [2:2] - - - OCIE1C - Timer/Counter1 Output Compare C Match Interrupt Enable - [3:3] - - - ICIE1 - Timer/Counter1 Input Capture Interrupt Enable - [5:5] - - - - - - - TC2 - Timer/Counter, 8-bit Async - 0x37 - - - ASSR - Asynchronous Status Register - 0x7F - - - TCR2BUB - Timer/Counter Control Register2 Update Busy - [0:0] - - - TCR2AUB - Timer/Counter Control Register2 Update Busy - [1:1] - - - OCR2BUB - Output Compare Register 2 Update Busy - [2:2] - - - OCR2AUB - Output Compare Register2 Update Busy - [3:3] - - - TCN2UB - Timer/Counter2 Update Busy - [4:4] - - - AS2 - Asynchronous Timer/Counter2 - [5:5] - - - EXCLK - Enable External Clock Input - [6:6] - - - - - GTCCR - General Timer Counter Control register - 0xC - - - PSRASY - Prescaler Reset Timer/Counter2 - [1:1] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - OCR2A - Timer/Counter2 Output Compare Register A - 0x7C - - - 0 - 255 - - - - - OCR2B - Timer/Counter2 Output Compare Register B - 0x7D - - - 0 - 255 - - - - - TCCR2A - Timer/Counter2 Control Register A - 0x79 - - - WGM2 - Waveform Genration Mode - [1:0] - - - 0 - 3 - - - - - COM2B - Compare Output Mode bits - [5:4] - - - 0 - 3 - - - - - COM2A - Compare Output Mode bits - [7:6] - - - 0 - 3 - - - - - - - TCCR2B - Timer/Counter2 Control Register B - 0x7A - - - CS2 - Clock Select bits - [2:0] - - true - - - - VAL_0x00 - No Clock Source (Stopped) - 0 - - - VAL_0x01 - Running, No Prescaling - 1 - - - VAL_0x02 - Running, CLK/8 - 2 - - - VAL_0x03 - Running, CLK/32 - 3 - - - VAL_0x04 - Running, CLK/64 - 4 - - - VAL_0x05 - Running, CLK/128 - 5 - - - VAL_0x06 - Running, CLK/256 - 6 - - - VAL_0x07 - Running, CLK/1024 - 7 - - - - - WGM22 - Waveform Generation Mode - [3:3] - - - FOC2B - Force Output Compare B - [6:6] - - - FOC2A - Force Output Compare A - [7:7] - - - - - TCNT2 - Timer/Counter2 - 0x7B - - - 0 - 255 - - - - - TIFR2 - Timer/Counter Interrupt Flag Register - 0x0 - read-only - - - TOV2 - Timer/Counter2 Overflow Flag - [0:0] - - - OCF2A - Output Compare Flag 2A - [1:1] - - - OCF2B - Output Compare Flag 2B - [2:2] - - - - - TIMSK2 - Timer/Counter Interrupt Mask register - 0x39 - - - TOIE2 - Timer/Counter2 Overflow Interrupt Enable - [0:0] - - - OCIE2A - Timer/Counter2 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE2B - Timer/Counter2 Output Compare Match B Interrupt Enable - [2:2] - - - - - - - TC3 - Timer/Counter, 16-bit - 0x38 - - - ICR3 - Timer/Counter3 Input Capture Register Bytes - 0x5E - 16 - - - 0 - 65535 - - - - - OCR3A - Timer/Counter3 Output Compare Register A Bytes - 0x60 - 16 - - - 0 - 65535 - - - - - OCR3B - Timer/Counter3 Output Compare Register B Bytes - 0x62 - 16 - - - 0 - 65535 - - - - - OCR3C - Timer/Counter3 Output Compare Register B Bytes - 0x64 - 16 - - - 0 - 65535 - - - - - TCCR3A - Timer/Counter3 Control Register A - 0x58 - - - WGM3 - Waveform Generation Mode - [1:0] - - - 0 - 3 - - - - - COM3C - Compare Output Mode 3C, bits - [3:2] - - - 0 - 3 - - - - - COM3B - Compare Output Mode 3B, bits - [5:4] - - - 0 - 3 - - - - - COM3A - Compare Output Mode 1A, bits - [7:6] - - - 0 - 3 - - - - - - - TCCR3B - Timer/Counter3 Control Register B - 0x59 - - - CS3 - Prescaler source of Timer/Counter 3 - [2:0] - - true - - - - VAL_0x00 - No Clock Source (Stopped) - 0 - - - VAL_0x01 - Running, No Prescaling - 1 - - - VAL_0x02 - Running, CLK/8 - 2 - - - VAL_0x03 - Running, CLK/64 - 3 - - - VAL_0x04 - Running, CLK/256 - 4 - - - VAL_0x05 - Running, CLK/1024 - 5 - - - VAL_0x06 - Running, ExtClk Tx Falling Edge - 6 - - - VAL_0x07 - Running, ExtClk Tx Rising Edge - 7 - - - - - WGM3 - Waveform Generation Mode - [4:3] - - - 0 - 3 - - - - - ICES3 - Input Capture 3 Edge Select - [6:6] - - - ICNC3 - Input Capture 3 Noise Canceler - [7:7] - - - - - TCCR3C - Timer/Counter 3 Control Register C - 0x5A - - - FOC3C - Force Output Compare 3C - [5:5] - - - FOC3B - Force Output Compare 3B - [6:6] - - - FOC3A - Force Output Compare 3A - [7:7] - - - - - TCNT3 - Timer/Counter3 Bytes - 0x5C - 16 - - - 0 - 65535 - - - - - TIFR3 - Timer/Counter3 Interrupt Flag register - 0x0 - read-only - - - TOV3 - Timer/Counter3 Overflow Flag - [0:0] - - - OCF3A - Output Compare Flag 3A - [1:1] - - - OCF3B - Output Compare Flag 3B - [2:2] - - - OCF3C - Output Compare Flag 3C - [3:3] - - - ICF3 - Input Capture Flag 3 - [5:5] - - - - - TIMSK3 - Timer/Counter3 Interrupt Mask Register - 0x39 - - - TOIE3 - Timer/Counter3 Overflow Interrupt Enable - [0:0] - - - OCIE3A - Timer/Counter3 Output Compare A Match Interrupt Enable - [1:1] - - - OCIE3B - Timer/Counter3 Output Compare B Match Interrupt Enable - [2:2] - - - OCIE3C - Timer/Counter3 Output Compare C Match Interrupt Enable - [3:3] - - - ICIE3 - Timer/Counter3 Input Capture Interrupt Enable - [5:5] - - - - - - - TC4 - Timer/Counter, 16-bit - 0x39 - - - ICR4 - Timer/Counter4 Input Capture Register Bytes - 0x6D - 16 - - - 0 - 65535 - - - - - OCR4A - Timer/Counter4 Output Compare Register A Bytes - 0x6F - 16 - - - 0 - 65535 - - - - - OCR4B - Timer/Counter4 Output Compare Register B Bytes - 0x71 - 16 - - - 0 - 65535 - - - - - OCR4C - Timer/Counter4 Output Compare Register B Bytes - 0x73 - 16 - - - 0 - 65535 - - - - - TCCR4A - Timer/Counter4 Control Register A - 0x67 - - - WGM4 - Waveform Generation Mode - [1:0] - - - 0 - 3 - - - - - COM4C - Compare Output Mode 4C, bits - [3:2] - - - 0 - 3 - - - - - COM4B - Compare Output Mode 4B, bits - [5:4] - - - 0 - 3 - - - - - COM4A - Compare Output Mode 1A, bits - [7:6] - - - 0 - 3 - - - - - - - TCCR4B - Timer/Counter4 Control Register B - 0x68 - - - CS4 - Prescaler source of Timer/Counter 4 - [2:0] - - true - - - - VAL_0x00 - No Clock Source (Stopped) - 0 - - - VAL_0x01 - Running, No Prescaling - 1 - - - VAL_0x02 - Running, CLK/8 - 2 - - - VAL_0x03 - Running, CLK/64 - 3 - - - VAL_0x04 - Running, CLK/256 - 4 - - - VAL_0x05 - Running, CLK/1024 - 5 - - - VAL_0x06 - Running, ExtClk Tx Falling Edge - 6 - - - VAL_0x07 - Running, ExtClk Tx Rising Edge - 7 - - - - - WGM4 - Waveform Generation Mode - [4:3] - - - 0 - 3 - - - - - ICES4 - Input Capture 4 Edge Select - [6:6] - - - ICNC4 - Input Capture 4 Noise Canceler - [7:7] - - - - - TCCR4C - Timer/Counter 4 Control Register C - 0x69 - - - FOC4C - Force Output Compare 4C - [5:5] - - - FOC4B - Force Output Compare 4B - [6:6] - - - FOC4A - Force Output Compare 4A - [7:7] - - - - - TCNT4 - Timer/Counter4 Bytes - 0x6B - 16 - - - 0 - 65535 - - - - - TIFR4 - Timer/Counter4 Interrupt Flag register - 0x0 - - - TOV4 - Timer/Counter4 Overflow Flag - [0:0] - - - OCF4A - Output Compare Flag 4A - [1:1] - - - OCF4B - Output Compare Flag 4B - [2:2] - - - OCF4C - Output Compare Flag 4C - [3:3] - - - ICF4 - Input Capture Flag 4 - [5:5] - - - - - TIMSK4 - Timer/Counter4 Interrupt Mask Register - 0x39 - - - TOIE4 - Timer/Counter4 Overflow Interrupt Enable - [0:0] - - - OCIE4A - Timer/Counter4 Output Compare A Match Interrupt Enable - [1:1] - - - OCIE4B - Timer/Counter4 Output Compare B Match Interrupt Enable - [2:2] - - - OCIE4C - Timer/Counter4 Output Compare C Match Interrupt Enable - [3:3] - - - ICIE4 - Timer/Counter4 Input Capture Interrupt Enable - [5:5] - - - - - - - TC5 - Timer/Counter, 16-bit - 0x3A - - - ICR5 - Timer/Counter5 Input Capture Register Bytes - 0xEC - 16 - - - 0 - 65535 - - - - - OCR5A - Timer/Counter5 Output Compare Register A Bytes - 0xEE - 16 - - - 0 - 65535 - - - - - OCR5B - Timer/Counter5 Output Compare Register B Bytes - 0xF0 - 16 - - - 0 - 65535 - - - - - OCR5C - Timer/Counter5 Output Compare Register B Bytes - 0xF2 - 16 - - - 0 - 65535 - - - - - TCCR5A - Timer/Counter5 Control Register A - 0xE6 - - - WGM5 - Waveform Generation Mode - [1:0] - - - 0 - 3 - - - - - COM5C - Compare Output Mode 5C, bits - [3:2] - - - 0 - 3 - - - - - COM5B - Compare Output Mode 5B, bits - [5:4] - - - 0 - 3 - - - - - COM5A - Compare Output Mode 1A, bits - [7:6] - - - 0 - 3 - - - - - - - TCCR5B - Timer/Counter5 Control Register B - 0xE7 - - - CS5 - Prescaler source of Timer/Counter 5 - [2:0] - - true - - - - VAL_0x00 - No Clock Source (Stopped) - 0 - - - VAL_0x01 - Running, No Prescaling - 1 - - - VAL_0x02 - Running, CLK/8 - 2 - - - VAL_0x03 - Running, CLK/64 - 3 - - - VAL_0x04 - Running, CLK/256 - 4 - - - VAL_0x05 - Running, CLK/1024 - 5 - - - VAL_0x06 - Running, ExtClk Tx Falling Edge - 6 - - - VAL_0x07 - Running, ExtClk Tx Rising Edge - 7 - - - - - WGM5 - Waveform Generation Mode - [4:3] - - - 0 - 3 - - - - - ICES5 - Input Capture 5 Edge Select - [6:6] - - - ICNC5 - Input Capture 5 Noise Canceler - [7:7] - - - - - TCCR5C - Timer/Counter 5 Control Register C - 0xE8 - - - FOC5C - Force Output Compare 5C - [5:5] - - - FOC5B - Force Output Compare 5B - [6:6] - - - FOC5A - Force Output Compare 5A - [7:7] - - - - - TCNT5 - Timer/Counter5 Bytes - 0xEA - 16 - - - 0 - 65535 - - - - - TIFR5 - Timer/Counter5 Interrupt Flag register - 0x0 - - - TOV5 - Timer/Counter5 Overflow Flag - [0:0] - - - OCF5A - Output Compare Flag 5A - [1:1] - - - OCF5B - Output Compare Flag 5B - [2:2] - - - OCF5C - Output Compare Flag 5C - [3:3] - - - ICF5 - Input Capture Flag 5 - [5:5] - - - - - TIMSK5 - Timer/Counter5 Interrupt Mask Register - 0x39 - - - TOIE5 - Timer/Counter5 Overflow Interrupt Enable - [0:0] - - - OCIE5A - Timer/Counter5 Output Compare A Match Interrupt Enable - [1:1] - - - OCIE5B - Timer/Counter5 Output Compare B Match Interrupt Enable - [2:2] - - - OCIE5C - Timer/Counter5 Output Compare C Match Interrupt Enable - [3:3] - - - ICIE5 - Timer/Counter5 Input Capture Interrupt Enable - [5:5] - - - - - - - TWI - Two Wire Serial Interface - 0xB8 - - - TWAMR - TWI (Slave) Address Mask Register - 0x5 - - - TWAM - TWI (Slave) Address Mask Bits - [7:1] - - - 0 - 127 - - - - - - - TWAR - TWI (Slave) Address register - 0x2 - - - TWGCE - TWI General Call Recognition Enable Bit - [0:0] - - - TWA - TWI (Slave) Address register Bits - [7:1] - - - 0 - 127 - - - - - - - TWBR - TWI Bit Rate register - 0x0 - - - 0 - 255 - - - - - TWCR - TWI Control Register - 0x4 - read-write - - - TWIE - TWI Interrupt Enable - [0:0] - - - TWEN - TWI Enable Bit - [2:2] - - - TWWC - TWI Write Collition Flag - [3:3] - read-only - - TWSTO - TWI Stop Condition Bit - [4:4] - - - TWSTA - TWI Start Condition Bit - [5:5] - - - TWEA - TWI Enable Acknowledge Bit - [6:6] - - - TWINT - TWI Interrupt Flag - [7:7] - - - - - TWDR - TWI Data register - 0x3 - - - 0 - 255 - - - - - TWSR - TWI Status Register - 0x1 - - - TWPS - TWI Prescaler - [1:0] - - true - - TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 - - - TWS - TWI Status - [7:3] - read-only - - 0 - 31 - - - - - - - - - USART0 - USART - 0xC0 - - - UBRR0 - USART Baud Rate Register Bytes - 0x4 - 16 - - - 0 - 65535 - - - - - UCSR0A - USART Control and Status Register A - 0x0 - read-write - - - MPCM0 - Multi-processor Communication Mode - [0:0] - - - U2X0 - Double the USART transmission speed - [1:1] - - - UPE0 - Parity Error - [2:2] - read-only - - DOR0 - Data overRun - [3:3] - read-only - - FE0 - Framing Error - [4:4] - read-only - - UDRE0 - USART Data Register Empty - [5:5] - read-only - - TXC0 - USART Transmit Complete - [6:6] - - - RXC0 - USART Receive Complete - [7:7] - read-only - - - - UCSR0B - USART Control and Status Register B - 0x1 - - - TXB80 - Transmit Data Bit 8 - [0:0] - - - RXB80 - Receive Data Bit 8 - [1:1] - read-only - - UCSZ02 - Character Size - [2:2] - - - TXEN0 - Transmitter Enable - [3:3] - - - RXEN0 - Receiver Enable - [4:4] - - - UDRIE0 - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE0 - TX Complete Interrupt Enable - [6:6] - - - RXCIE0 - RX Complete Interrupt Enable - [7:7] - - - - - UCSR0C - USART Control and Status Register C - 0x2 - - - UCPOL0 - Clock Polarity - [0:0] - UCPOL0read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 - - - UCSZ0 - Character Size - [2:1] - - - 0 - 3 - - - UCSZ0read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 - - - USBS0 - Stop Bit Select - [3:3] - - true - - USBS0read-writeSTOP11-bit0STOP22-bit1 - - - UPM0 - Parity Mode Bits - [5:4] - - true - - UPM0read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 - - - UMSEL0 - USART Mode Select - [7:6] - - true - - UMSEL0read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 - - - - - UDR0 - USART I/O Data Register - 0x6 - - - 0 - 255 - - - - - - - USART1 - USART - 0xC8 - - - UBRR1 - USART Baud Rate Register Bytes - 0x4 - 16 - - - 0 - 65535 - - - - - UCSR1A - USART Control and Status Register A - 0x0 - read-write - - - MPCM1 - Multi-processor Communication Mode - [0:0] - - - U2X1 - Double the USART transmission speed - [1:1] - - - UPE1 - Parity Error - [2:2] - read-only - - DOR1 - Data overRun - [3:3] - read-only - - FE1 - Framing Error - [4:4] - read-only - - UDRE1 - USART Data Register Empty - [5:5] - read-only - - TXC1 - USART Transmit Complete - [6:6] - - - RXC1 - USART Receive Complete - [7:7] - read-only - - - - UCSR1B - USART Control and Status Register B - 0x1 - - - TXB81 - Transmit Data Bit 8 - [0:0] - - - RXB81 - Receive Data Bit 8 - [1:1] - read-only - - UCSZ12 - Character Size - [2:2] - - - TXEN1 - Transmitter Enable - [3:3] - - - RXEN1 - Receiver Enable - [4:4] - - - UDRIE1 - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE1 - TX Complete Interrupt Enable - [6:6] - - - RXCIE1 - RX Complete Interrupt Enable - [7:7] - - - - - UCSR1C - USART Control and Status Register C - 0x2 - - - UCPOL1 - Clock Polarity - [0:0] - UCPOL1read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 - - - UCSZ1 - Character Size - [2:1] - - - 0 - 3 - - - UCSZ1read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 - - - USBS1 - Stop Bit Select - [3:3] - - true - - USBS1read-writeSTOP11-bit0STOP22-bit1 - - - UPM1 - Parity Mode Bits - [5:4] - - true - - UPM1read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 - - - UMSEL1 - USART Mode Select - [7:6] - - true - - UMSEL1read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 - - - - - UDR1 - USART I/O Data Register - 0x6 - - - 0 - 255 - - - - - - - USART2 - USART - 0xD0 - - - UBRR2 - USART Baud Rate Register Bytes - 0x4 - 16 - - - 0 - 65535 - - - - - UCSR2A - USART Control and Status Register A - 0x0 - read-write - - - MPCM2 - Multi-processor Communication Mode - [0:0] - - - U2X2 - Double the USART transmission speed - [1:1] - - - UPE2 - Parity Error - [2:2] - read-only - - DOR2 - Data overRun - [3:3] - read-only - - FE2 - Framing Error - [4:4] - read-only - - UDRE2 - USART Data Register Empty - [5:5] - read-only - - TXC2 - USART Transmit Complete - [6:6] - - - RXC2 - USART Receive Complete - [7:7] - read-only - - - - UCSR2B - USART Control and Status Register B - 0x1 - - - TXB82 - Transmit Data Bit 8 - [0:0] - - - RXB82 - Receive Data Bit 8 - [1:1] - read-only - - UCSZ22 - Character Size - [2:2] - - - TXEN2 - Transmitter Enable - [3:3] - - - RXEN2 - Receiver Enable - [4:4] - - - UDRIE2 - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE2 - TX Complete Interrupt Enable - [6:6] - - - RXCIE2 - RX Complete Interrupt Enable - [7:7] - - - - - UCSR2C - USART Control and Status Register C - 0x2 - - - UCPOL2 - Clock Polarity - [0:0] - UCPOL2read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 - - - UCSZ2 - Character Size - [2:1] - - - 0 - 3 - - - UCSZ2read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 - - - USBS2 - Stop Bit Select - [3:3] - - true - - USBS2read-writeSTOP11-bit0STOP22-bit1 - - - UPM2 - Parity Mode Bits - [5:4] - - true - - UPM2read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 - - - UMSEL2 - USART Mode Select - [7:6] - - true - - UMSEL2read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 - - - - - UDR2 - USART I/O Data Register - 0x6 - - - 0 - 255 - - - - - - - USART3 - USART - 0x130 - - - UBRR3 - USART Baud Rate Register Bytes - 0x4 - 16 - - - 0 - 65535 - - - - - UCSR3A - USART Control and Status Register A - 0x0 - read-write - - - MPCM3 - Multi-processor Communication Mode - [0:0] - - - U2X3 - Double the USART transmission speed - [1:1] - - - UPE3 - Parity Error - [2:2] - read-only - - DOR3 - Data overRun - [3:3] - read-only - - FE3 - Framing Error - [4:4] - read-only - - UDRE3 - USART Data Register Empty - [5:5] - read-only - - TXC3 - USART Transmit Complete - [6:6] - - - RXC3 - USART Receive Complete - [7:7] - read-only - - - - UCSR3B - USART Control and Status Register B - 0x1 - - - TXB83 - Transmit Data Bit 8 - [0:0] - - - RXB83 - Receive Data Bit 8 - [1:1] - read-only - - UCSZ32 - Character Size - [2:2] - - - TXEN3 - Transmitter Enable - [3:3] - - - RXEN3 - Receiver Enable - [4:4] - - - UDRIE3 - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE3 - TX Complete Interrupt Enable - [6:6] - - - RXCIE3 - RX Complete Interrupt Enable - [7:7] - - - - - UCSR3C - USART Control and Status Register C - 0x2 - - - UCPOL3 - Clock Polarity - [0:0] - UCPOL3read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 - - - UCSZ3 - Character Size - [2:1] - - - 0 - 3 - - - UCSZ3read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 - - - USBS3 - Stop Bit Select - [3:3] - - true - - USBS3read-writeSTOP11-bit0STOP22-bit1 - - - UPM3 - Parity Mode Bits - [5:4] - - true - - UPM3read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 - - - UMSEL3 - USART Mode Select - [7:6] - - true - - UMSEL3read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 - - - - - UDR3 - USART I/O Data Register - 0x6 - - - 0 - 255 - - - - - - - WDT - Watchdog Timer - 0x60 - - - WDTCSR - Watchdog Timer Control Register - 0x0 - read-write - - - WDE - Watch Dog Enable - [3:3] - - - WDCE - Watchdog Change Enable - [4:4] - - - WDIE - Watchdog Timeout Interrupt Enable - [6:6] - - - WDIF - Watchdog Timeout Interrupt Flag - [7:7] - - WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 - - WDPHWatchdog Timer Prescaler - High Bit[5:5] - - - - - - \ No newline at end of file diff --git a/misc/svd/atmega168.svd b/misc/svd/atmega168.svd deleted file mode 100644 index d8e32bf..0000000 --- a/misc/svd/atmega168.svd +++ /dev/null @@ -1,3030 +0,0 @@ - - Atmel - ATmega168 - 8 - 8 - read-write - 0 - 0xff - - - AC - Analog Comparator - 0x50 - - - ACSR - Analog Comparator Control And Status Register - 0x0 - read-write - - - ACIS - Analog Comparator Interrupt Mode Select - [1:0] - - true - - ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 - - - ACIC - Analog Comparator Input Capture Enable - [2:2] - - - ACIE - Analog Comparator Interrupt Enable - [3:3] - - - ACI - Analog Comparator Interrupt Flag - [4:4] - - - ACO - Analog Compare Output - [5:5] - read-only - - ACBG - Analog Comparator Bandgap Select - [6:6] - - - ACD - Analog Comparator Disable - [7:7] - - - - - DIDR1 - Digital Input Disable Register 1 - 0x2F - - - AIN0D - AIN0 Digital Input Disable - [0:0] - - - AIN1D - AIN1 Digital Input Disable - [1:1] - - - - - - - ADC - Analog-to-Digital Converter - 0x78 - - - ADC - ADC Data Register Bytes - 0x0 - 16 - - - 0 - 65535 - - - - - ADCSRA - The ADC Control and Status register A - 0x2 - read-write - - - ADPS - ADC Prescaler Select Bits - [2:0] - - true - - ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 - - - ADIE - ADC Interrupt Enable - [3:3] - - - ADIF - ADC Interrupt Flag - [4:4] - - - ADATE - ADC Auto Trigger Enable - [5:5] - - - ADSC - ADC Start Conversion - [6:6] - - - ADEN - ADC Enable - [7:7] - - - - - ADCSRB - The ADC Control and Status register B - 0x3 - - - ADTS - ADC Auto Trigger Source bits - [2:0] - - true - - - - VAL_0x00 - Free Running mode - 0 - - - VAL_0x01 - Analog Comparator - 1 - - - VAL_0x02 - External Interrupt Request 0 - 2 - - - VAL_0x03 - Timer/Counter0 Compare Match A - 3 - - - VAL_0x04 - Timer/Counter0 Overflow - 4 - - - VAL_0x05 - Timer/Counter1 Compare Match B - 5 - - - VAL_0x06 - Timer/Counter1 Overflow - 6 - - - VAL_0x07 - Timer/Counter1 Capture Event - 7 - - - - - ACME - <TBD> - [6:6] - - - - - ADMUX - The ADC multiplexer Selection Register - 0x4 - - - MUX - Analog Channel Selection Bits - [3:0] - - true - - - - ADC0 - ADC Single Ended Input pin 0 - 0 - - - ADC1 - ADC Single Ended Input pin 1 - 1 - - - ADC2 - ADC Single Ended Input pin 2 - 2 - - - ADC3 - ADC Single Ended Input pin 3 - 3 - - - ADC4 - ADC Single Ended Input pin 4 - 4 - - - ADC5 - ADC Single Ended Input pin 5 - 5 - - - ADC6 - ADC Single Ended Input pin 6 - 6 - - - ADC7 - ADC Single Ended Input pin 7 - 7 - - - ADC_VBG - Internal Reference (VBG) - 14 - - - ADC_GND - 0V (GND) - 15 - - - - - ADLAR - Left Adjust Result - [5:5] - - - REFS - Reference Selection Bits - [7:6] - - true - - REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 - - - - - DIDR0 - Digital Input Disable Register - 0x6 - - - ADC0D - <TBD> - [0:0] - - - ADC1D - <TBD> - [1:1] - - - ADC2D - <TBD> - [2:2] - - - ADC3D - <TBD> - [3:3] - - - ADC4D - <TBD> - [4:4] - - - ADC5D - <TBD> - [5:5] - - - - - - - CPU - CPU Registers - 0x3E - - RESET - External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset - 0 - - - INT0 - External Interrupt Request 0 - 1 - - - INT1 - External Interrupt Request 1 - 2 - - - PCINT0 - Pin Change Interrupt Request 0 - 3 - - - PCINT1 - Pin Change Interrupt Request 0 - 4 - - - PCINT2 - Pin Change Interrupt Request 1 - 5 - - - WDT - Watchdog Time-out Interrupt - 6 - - - TIMER2_COMPA - Timer/Counter2 Compare Match A - 7 - - - TIMER2_COMPB - Timer/Counter2 Compare Match A - 8 - - - TIMER2_OVF - Timer/Counter2 Overflow - 9 - - - TIMER1_CAPT - Timer/Counter1 Capture Event - 10 - - - TIMER1_COMPA - Timer/Counter1 Compare Match A - 11 - - - TIMER1_COMPB - Timer/Counter1 Compare Match B - 12 - - - TIMER1_OVF - Timer/Counter1 Overflow - 13 - - - TIMER0_COMPA - TimerCounter0 Compare Match A - 14 - - - TIMER0_COMPB - TimerCounter0 Compare Match B - 15 - - - TIMER0_OVF - Timer/Couner0 Overflow - 16 - - - SPI_STC - SPI Serial Transfer Complete - 17 - - - USART_RX - USART Rx Complete - 18 - - - USART_UDRE - USART, Data Register Empty - 19 - - - USART_TX - USART Tx Complete - 20 - - - ADC - ADC Conversion Complete - 21 - - - EE_READY - EEPROM Ready - 22 - - - ANALOG_COMP - Analog Comparator - 23 - - - TWI - Two-wire Serial Interface - 24 - - - SPM_READY - Store Program Memory Read - 25 - - - - CLKPR - Clock Prescale Register - 0x23 - read-only - - - CLKPS - Clock Prescaler Select Bits - [3:0] - - true - - - - VAL_0x00 - 1 - 0 - - - VAL_0x01 - 2 - 1 - - - VAL_0x02 - 4 - 2 - - - VAL_0x03 - 8 - 3 - - - VAL_0x04 - 16 - 4 - - - VAL_0x05 - 32 - 5 - - - VAL_0x06 - 64 - 6 - - - VAL_0x07 - 128 - 7 - - - VAL_0x08 - 256 - 8 - - - - - CLKPCE - Clock Prescaler Change Enable - [7:7] - - - - - GPIOR0 - General Purpose I/O Register 0 - 0x0 - - - 0 - 255 - - - - - GPIOR1 - General Purpose I/O Register 1 - 0xC - - - 0 - 255 - - - - - GPIOR2 - General Purpose I/O Register 2 - 0xD - - - 0 - 255 - - - - - MCUCR - MCU Control Register - 0x17 - - - IVCE - Interrupt Vector Change Enable - [0:0] - - - IVSEL - Interrupt Vector Select - [1:1] - - - PUD - Pull-up Disable - [4:4] - - - - - MCUSR - MCU Status Register - 0x16 - - - PORF - Power-on reset flag - [0:0] - - - EXTRF - External Reset Flag - [1:1] - - - BORF - Brown-out Reset Flag - [2:2] - - - WDRF - Watchdog Reset Flag - [3:3] - - - - - OSCCAL - Oscillator Calibration Value - 0x28 - read-only - - - OSCCAL - Oscillator Calibration - [7:0] - - - 0 - 255 - - - - - - - PRR - Power Reduction Register - 0x26 - read-only - - - PRADC - Power Reduction ADC - [0:0] - - - PRUSART0 - Power Reduction USART - [1:1] - - - PRSPI - Power Reduction Serial Peripheral Interface - [2:2] - - - PRTIM1 - Power Reduction Timer/Counter1 - [3:3] - - - PRTIM0 - Power Reduction Timer/Counter0 - [5:5] - - - PRTIM2 - Power Reduction Timer/Counter2 - [6:6] - - - PRTWI - Power Reduction TWI - [7:7] - - - - - SMCR - Sleep Mode Control Register - 0x15 - - - SE - Sleep Enable - [0:0] - - - SM - Sleep Mode - [3:1] - - true - - - - IDLE - Idle - 0 - - - ADC - ADC Noise Reduction (If Available) - 1 - - - PDOWN - Power Down - 2 - - - PSAVE - Power Save - 3 - - - VAL_0x04 - Reserved - 4 - - - VAL_0x05 - Reserved - 5 - - - STDBY - Standby - 6 - - - VAL_0x07 - Reserved - 7 - - - - - - - SPMCSR - Store Program Memory Control and Status Register - 0x19 - - - SELFPRGEN - Self Programming Enable - [0:0] - - - PGERS - Page Erase - [1:1] - - - PGWRT - Page Write - [2:2] - - - BLBSET - Boot Lock Bit Set - [3:3] - - - RWWSRE - Read-While-Write section read enable - [4:4] - - - RWWSB - Read-While-Write Section Busy - [6:6] - - - SPMIE - SPM Interrupt Enable - [7:7] - - - - - - - EEPROM - EEPROM - 0x3F - - - EEAR - EEPROM Address Register Bytes - 0x2 - 16 - - - 0 - 65535 - - - - - EECR - EEPROM Control Register - 0x0 - - - EERE - EEPROM Read Enable - [0:0] - - - EEPE - EEPROM Write Enable - [1:1] - - - EEMPE - EEPROM Master Write Enable - [2:2] - - - EERIE - EEPROM Ready Interrupt Enable - [3:3] - - - EEPM - EEPROM Programming Mode Bits - [5:4] - - true - - - - VAL_0x00 - Erase and Write in one operation - 0 - - - VAL_0x01 - Erase Only - 1 - - - VAL_0x02 - Write Only - 2 - - - - - - - EEDR - EEPROM Data Register - 0x1 - - - 0 - 255 - - - - - - - EXINT - External Interrupts - 0x3B - - - EICRA - External Interrupt Control Register - 0x2E - - - ISC0 - External Interrupt Sense Control 0 Bits - [1:0] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC1 - External Interrupt Sense Control 1 Bits - [3:2] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - - - EIFR - External Interrupt Flag Register - 0x1 - read-only - - - INTF - External Interrupt Flags - [1:0] - - - 0 - 3 - - - - - - - EIMSK - External Interrupt Mask Register - 0x2 - - - INT - External Interrupt Request 1 Enable - [1:0] - - - 0 - 3 - - - - - - - PCICR - Pin Change Interrupt Control Register - 0x2D - - - PCIE - Pin Change Interrupt Enables - [2:0] - - - 0 - 7 - - - - - - - PCIFR - Pin Change Interrupt Flag Register - 0x0 - read-only - - - PCIF - Pin Change Interrupt Flags - [2:0] - - - 0 - 7 - - - - - - - PCMSK0 - Pin Change Mask Register 0 - 0x30 - - - PCINT - Pin Change Enable Masks - [7:0] - - - 0 - 255 - - - - - - - PCMSK1 - Pin Change Mask Register 1 - 0x31 - - - PCINT - Pin Change Enable Masks - [6:0] - - - 0 - 127 - - - - - - - PCMSK2 - Pin Change Mask Register 2 - 0x32 - - - PCINT - Pin Change Enable Masks - [7:0] - - - 0 - 255 - - - - - - - - - FUSE - Fuses - 0x0 - - - EXTENDED - <TBD> - 0x2 - - - BOOTRST - Boot Reset vector Enabled - [0:0] - - - BOOTSZ - Select boot size - [2:1] - - true - - - - 1024W_1C00 - Boot Flash size=1024 words start address=$1C00 - 0 - - - 512W_1E00 - Boot Flash size=512 words start address=$1E00 - 1 - - - 256W_1F00 - Boot Flash size=256 words start address=$1F00 - 2 - - - 128W_1F80 - Boot Flash size=128 words start address=$1F80 - 3 - - - - - - - HIGH - <TBD> - 0x1 - - - BODLEVEL - Brown-out Detector trigger level - [2:0] - - true - - - - 4V3 - Brown-out detection at VCC=4.3 V - 4 - - - 2V7 - Brown-out detection at VCC=2.7 V - 5 - - - 1V8 - Brown-out detection at VCC=1.8 V - 6 - - - DISABLED - Brown-out detection disabled - 7 - - - - - EESAVE - Preserve EEPROM through the Chip Erase cycle - [3:3] - - - WDTON - Watch-dog Timer always on - [4:4] - - - SPIEN - Serial program downloading (SPI) enabled - [5:5] - - - DWEN - Debug Wire enable - [6:6] - - - RSTDISBL - Reset Disabled (Enable PC6 as i/o pin) - [7:7] - - - - - LOW - <TBD> - 0x0 - - - SUT_CKSEL - Select Clock Source - [5:0] - - true - - - - EXTCLK_6CK_14CK_0MS - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 0 - - - INTRCOSC_8MHZ_6CK_14CK_0MS - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 2 - - - INTRCOSC_128KHZ_6CK_14CK_0MS - Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 3 - - - EXTLOFXTAL_1KCK_14CK_0MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms - 4 - - - EXTLOFXTAL_32KCK_14CK_0MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms - 5 - - - EXTFSXTAL_258CK_14CK_4MS1 - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 6 - - - EXTFSXTAL_1KCK_14CK_65MS - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 7 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 8 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 9 - - - EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 10 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 11 - - - EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 12 - - - EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 13 - - - EXTXOSC_8MHZ_XX_258CK_14CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 14 - - - EXTXOSC_8MHZ_XX_1KCK_14CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 15 - - - EXTCLK_6CK_14CK_4MS1 - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - 16 - - - INTRCOSC_8MHZ_6CK_14CK_4MS1 - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - 18 - - - INTRCOSC_128KHZ_6CK_14CK_4MS1 - Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - 19 - - - EXTLOFXTAL_1KCK_14CK_4MS1 - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms - 20 - - - EXTLOFXTAL_32KCK_14CK_4MS1 - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms - 21 - - - EXTFSXTAL_258CK_14CK_65MS - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 22 - - - EXTFSXTAL_16KCK_14CK_0MS - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 23 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 24 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 25 - - - EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 26 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 27 - - - EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 28 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 29 - - - EXTXOSC_8MHZ_XX_258CK_14CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 30 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 31 - - - EXTCLK_6CK_14CK_65MS - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms - 32 - - - INTRCOSC_8MHZ_6CK_14CK_65MS - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms - 34 - - - INTRCOSC_128KHZ_6CK_14CK_65MS - Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms - 35 - - - EXTLOFXTAL_1KCK_14CK_65MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms - 36 - - - EXTLOFXTAL_32KCK_14CK_65MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms - 37 - - - EXTFSXTAL_1KCK_14CK_0MS - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 38 - - - EXTFSXTAL_16KCK_14CK_4MS1 - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 39 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 40 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 41 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 42 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 43 - - - EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 44 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 45 - - - EXTXOSC_8MHZ_XX_1KCK_14CK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 46 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 47 - - - EXTFSXTAL_1KCK_14CK_4MS1 - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 54 - - - EXTFSXTAL_16KCK_14CK_65MS - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 55 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 56 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 57 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 58 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 59 - - - EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 60 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 61 - - - EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 62 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 63 - - - - - CKOUT - Clock output on PORTB0 - [6:6] - - - CKDIV8 - Divide clock by 8 internally - [7:7] - - - - - - - LOCKBIT - Lockbits - 0x0 - - - LOCKBIT - <TBD> - 0x0 - - - LB - Memory Lock - [1:0] - - true - - - - PROG_VER_DISABLED - Further programming and verification disabled - 0 - - - PROG_DISABLED - Further programming disabled - 2 - - - NO_LOCK - No memory lock features enabled - 3 - - - - - BLB0 - Boot Loader Protection Mode - [3:2] - - true - - - - LPM_SPM_DISABLE - LPM and SPM prohibited in Application Section - 0 - - - LPM_DISABLE - LPM prohibited in Application Section - 1 - - - SPM_DISABLE - SPM prohibited in Application Section - 2 - - - NO_LOCK - No lock on SPM and LPM in Application Section - 3 - - - - - BLB1 - Boot Loader Protection Mode - [5:4] - - true - - - - LPM_SPM_DISABLE - LPM and SPM prohibited in Boot Section - 0 - - - LPM_DISABLE - LPM prohibited in Boot Section - 1 - - - SPM_DISABLE - SPM prohibited in Boot Section - 2 - - - NO_LOCK - No lock on SPM and LPM in Boot Section - 3 - - - - - - - - - PORTB - I/O Port - 0x23 - - - DDRB - Port B Data Direction Register - 0x1 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PINB - Port B Input Pins - 0x0 - read-write - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PORTB - Port B Data Register - 0x2 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - - - PORTC - I/O Port - 0x26 - - - DDRC - Port C Data Direction Register - 0x1 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - - - PINC - Port C Input Pins - 0x0 - read-write - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - - - PORTC - Port C Data Register - 0x2 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - - - - - PORTD - I/O Port - 0x29 - - - DDRD - Port D Data Direction Register - 0x1 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PIND - Port D Input Pins - 0x0 - read-write - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PORTD - Port D Data Register - 0x2 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - - - SPI - Serial Peripheral Interface - 0x4C - - - SPCR - SPI Control Register - 0x0 - - - SPR - SPI Clock Rate Selects - [1:0] - - true - - SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 - - - CPHA - Clock Phase - [2:2] - - - CPOL - Clock polarity - [3:3] - - - MSTR - Master/Slave Select - [4:4] - - - DORD - Data Order - [5:5] - - - SPE - SPI Enable - [6:6] - - - SPIE - SPI Interrupt Enable - [7:7] - - - - - SPDR - SPI Data Register - 0x2 - - - 0 - 255 - - - - - SPSR - SPI Status Register - 0x1 - read-write - - - SPI2X - Double SPI Speed Bit - [0:0] - read-write - - WCOL - Write Collision Flag - [6:6] - read-only - - SPIF - SPI Interrupt Flag - [7:7] - read-only - - - - - - TC0 - Timer/Counter, 8-bit - 0x35 - - - GTCCR - General Timer/Counter Control Register - 0xE - - - PSRSYNC - Prescaler Reset Timer/Counter1 and Timer/Counter0 - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - OCR0A - Timer/Counter0 Output Compare Register - 0x12 - - - 0 - 255 - - - - - OCR0B - Timer/Counter0 Output Compare Register - 0x13 - - - 0 - 255 - - - - - TCCR0A - Timer/Counter Control Register A - 0xF - - - WGM0 - Waveform Generation Mode - [1:0] - - true - WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 - - - COM0B - Compare Output B Mode - [5:4] - - true - COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 - - - COM0A - Compare Output A Mode - [7:6] - - true - - - - - - TCCR0B - Timer/Counter Control Register B - 0x10 - - - CS0 - Clock Select - [2:0] - - true - - CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM02 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) - [3:3] - - - FOC0B - Force Output Compare B - [6:6] - write-only - - FOC0A - Force Output Compare A - [7:7] - write-only - - - - TCNT0 - Timer/Counter0 - 0x11 - - - 0 - 255 - - - - - TIFR0 - Timer/Counter0 Interrupt Flag register - 0x0 - read-write - - - TOV0 - Timer/Counter0 Overflow Flag - [0:0] - - - OCF0A - Timer/Counter0 Output Compare Flag 0A - [1:1] - - - OCF0B - Timer/Counter0 Output Compare Flag 0B - [2:2] - - - - - TIMSK0 - Timer/Counter0 Interrupt Mask Register - 0x39 - - - TOIE0 - Timer/Counter0 Overflow Interrupt Enable - [0:0] - - - OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable - [2:2] - - - - - - - TC1 - Timer/Counter, 16-bit - 0x36 - - - GTCCR - General Timer/Counter Control Register - 0xD - - - PSRSYNC - Prescaler Reset Timer/Counter1 and Timer/Counter0 - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - ICR1 - Timer/Counter1 Input Capture Register Bytes - 0x50 - 16 - - - 0 - 65535 - - - - - OCR1A - Timer/Counter1 Output Compare Register Bytes - 0x52 - 16 - - - 0 - 65535 - - - - - OCR1B - Timer/Counter1 Output Compare Register Bytes - 0x54 - 16 - - - 0 - 65535 - - - - - TCCR1A - Timer/Counter1 Control Register A - 0x4A - - - WGM1 - Waveform Generation Mode - [1:0] - - - 0 - 3 - - - - - COM1B - Compare Output Mode 1B, bits - [5:4] - - true - COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM1A - Compare Output Mode 1A, bits - [7:6] - - true - - - - - - TCCR1B - Timer/Counter1 Control Register B - 0x4B - - - CS1 - Prescaler source of Timer/Counter 1 - [2:0] - - true - CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM1 - Waveform Generation Mode - [4:3] - - - 0 - 3 - - - - - ICES1 - Input Capture 1 Edge Select - [6:6] - - - ICNC1 - Input Capture 1 Noise Canceler - [7:7] - - - - - TCCR1C - Timer/Counter1 Control Register C - 0x4C - - - FOC1B - <TBD> - [6:6] - write-only - - FOC1A - <TBD> - [7:7] - write-only - - - - TCNT1 - Timer/Counter1 Bytes - 0x4E - 16 - - - 0 - 65535 - - - - - TIFR1 - Timer/Counter Interrupt Flag register - 0x0 - read-write - - - TOV1 - Timer/Counter1 Overflow Flag - [0:0] - - - OCF1A - Output Compare Flag 1A - [1:1] - - - OCF1B - Output Compare Flag 1B - [2:2] - - - ICF1 - Input Capture Flag 1 - [5:5] - - - - - TIMSK1 - Timer/Counter Interrupt Mask Register - 0x39 - - - TOIE1 - Timer/Counter1 Overflow Interrupt Enable - [0:0] - - - OCIE1A - Timer/Counter1 Output CompareA Match Interrupt Enable - [1:1] - - - OCIE1B - Timer/Counter1 Output CompareB Match Interrupt Enable - [2:2] - - - ICIE1 - Timer/Counter1 Input Capture Interrupt Enable - [5:5] - - - - - - - TC2 - Timer/Counter, 8-bit Async - 0x37 - - - ASSR - Asynchronous Status Register - 0x7F - - - TCR2BUB - Timer/Counter Control Register2 Update Busy - [0:0] - - - TCR2AUB - Timer/Counter Control Register2 Update Busy - [1:1] - - - OCR2BUB - Output Compare Register 2 Update Busy - [2:2] - - - OCR2AUB - Output Compare Register2 Update Busy - [3:3] - - - TCN2UB - Timer/Counter2 Update Busy - [4:4] - - - AS2 - Asynchronous Timer/Counter2 - [5:5] - - - EXCLK - Enable External Clock Input - [6:6] - - - - - GTCCR - General Timer Counter Control register - 0xC - - - PSRASY - Prescaler Reset Timer/Counter2 - [1:1] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - OCR2A - Timer/Counter2 Output Compare Register A - 0x7C - - - 0 - 255 - - - - - OCR2B - Timer/Counter2 Output Compare Register B - 0x7D - - - 0 - 255 - - - - - TCCR2A - Timer/Counter2 Control Register A - 0x79 - - - WGM2 - Waveform Genration Mode - [1:0] - - true - WGM2read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 - - - COM2B - Compare Output B Mode - [5:4] - - true - COM2Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 - - - COM2A - Compare Output A Mode - [7:6] - - true - - - - - - TCCR2B - Timer/Counter2 Control Register B - 0x7A - - - CS2 - Clock Select bits - [2:0] - - true - - CS2read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_32Running, CLK/323PRESCALE_64Running, CLK/644PRESCALE_128Running, CLK/1285PRESCALE_256Running, CLK/2566PRESCALE_1024Running, CLK/10247 - - - WGM22 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) - [3:3] - - - FOC2B - Force Output Compare B - [6:6] - write-only - - FOC2A - Force Output Compare A - [7:7] - write-only - - - - TCNT2 - Timer/Counter2 - 0x7B - - - 0 - 255 - - - - - TIFR2 - Timer/Counter Interrupt Flag Register - 0x0 - read-write - - - TOV2 - Timer/Counter2 Overflow Flag - [0:0] - - - OCF2A - Output Compare Flag 2A - [1:1] - - - OCF2B - Output Compare Flag 2B - [2:2] - - - - - TIMSK2 - Timer/Counter Interrupt Mask register - 0x39 - - - TOIE2 - Timer/Counter2 Overflow Interrupt Enable - [0:0] - - - OCIE2A - Timer/Counter2 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE2B - Timer/Counter2 Output Compare Match B Interrupt Enable - [2:2] - - - - - - - TWI - Two Wire Serial Interface - 0xB8 - - - TWAMR - TWI (Slave) Address Mask Register - 0x5 - - - TWAM - TWI (Slave) Address Mask Bits - [7:1] - - - 0 - 127 - - - - - - - TWAR - TWI (Slave) Address register - 0x2 - - - TWGCE - TWI General Call Recognition Enable Bit - [0:0] - - - TWA - TWI (Slave) Address register Bits - [7:1] - - - 0 - 127 - - - - - - - TWBR - TWI Bit Rate register - 0x0 - - - 0 - 255 - - - - - TWCR - TWI Control Register - 0x4 - read-write - - - TWIE - TWI Interrupt Enable - [0:0] - - - TWEN - TWI Enable Bit - [2:2] - - - TWWC - TWI Write Collition Flag - [3:3] - read-only - - TWSTO - TWI Stop Condition Bit - [4:4] - - - TWSTA - TWI Start Condition Bit - [5:5] - - - TWEA - TWI Enable Acknowledge Bit - [6:6] - - - TWINT - TWI Interrupt Flag - [7:7] - - - - - TWDR - TWI Data register - 0x3 - - - 0 - 255 - - - - - TWSR - TWI Status Register - 0x1 - - - TWPS - TWI Prescaler - [1:0] - - true - - TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 - - - TWS - TWI Status - [7:3] - read-only - - 0 - 31 - - - - - - - - - USART0 - USART - 0xC0 - - - UBRR0 - USART Baud Rate Register Bytes - 0x4 - 16 - - - 0 - 65535 - - - - - UCSR0A - USART Control and Status Register A - 0x0 - read-write - - - MPCM0 - Multi-processor Communication Mode - [0:0] - - - U2X0 - Double the USART transmission speed - [1:1] - - - UPE0 - Parity Error - [2:2] - read-only - - DOR0 - Data overRun - [3:3] - read-only - - FE0 - Framing Error - [4:4] - read-only - - UDRE0 - USART Data Register Empty - [5:5] - read-only - - TXC0 - USART Transmit Complete - [6:6] - - - RXC0 - USART Receive Complete - [7:7] - read-only - - - - UCSR0B - USART Control and Status Register B - 0x1 - - - TXB80 - Transmit Data Bit 8 - [0:0] - - - RXB80 - Receive Data Bit 8 - [1:1] - read-only - - UCSZ02 - Character Size - together with UCSZ0 in UCSR0C - [2:2] - - - TXEN0 - Transmitter Enable - [3:3] - - - RXEN0 - Receiver Enable - [4:4] - - - UDRIE0 - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE0 - TX Complete Interrupt Enable - [6:6] - - - RXCIE0 - RX Complete Interrupt Enable - [7:7] - - - - - UCSR0C - USART Control and Status Register C - 0x2 - - - UCPOL0 - Clock Polarity - [0:0] - UCPOL0read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 - - - UCSZ0 - Character Size - together with UCSZ2 in UCSR0B - [2:1] - - - 0 - 3 - - - UCSZ0read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 - - - USBS0 - Stop Bit Select - [3:3] - - true - - USBS0read-writeSTOP11-bit0STOP22-bit1 - - - UPM0 - Parity Mode Bits - [5:4] - - true - - UPM0read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 - - - UMSEL0 - USART Mode Select - [7:6] - - true - - UMSEL0read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 - - - - - UDR0 - USART I/O Data Register - 0x6 - - - 0 - 255 - - - - - - - WDT - Watchdog Timer - 0x60 - - - WDTCSR - Watchdog Timer Control Register - 0x0 - read-write - - - WDE - Watch Dog Enable - [3:3] - - - WDCE - Watchdog Change Enable - [4:4] - - - WDIE - Watchdog Timeout Interrupt Enable - [6:6] - - - WDIF - Watchdog Timeout Interrupt Flag - [7:7] - - WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 - - WDPHWatchdog Timer Prescaler - High Bit[5:5] - - - - - - \ No newline at end of file diff --git a/misc/svd/atmega2560.svd b/misc/svd/atmega2560.svd deleted file mode 100644 index 57369c3..0000000 --- a/misc/svd/atmega2560.svd +++ /dev/null @@ -1,6318 +0,0 @@ - - Atmel - ATmega2560 - 8 - 8 - read-write - 0 - 0xff - - - AC - Analog Comparator - 0x50 - - - ACSR - Analog Comparator Control And Status Register - 0x0 - read-write - - - ACIS - Analog Comparator Interrupt Mode Select - [1:0] - - true - - ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 - - - ACIC - Analog Comparator Input Capture Enable - [2:2] - - - ACIE - Analog Comparator Interrupt Enable - [3:3] - - - ACI - Analog Comparator Interrupt Flag - [4:4] - - - ACO - Analog Compare Output - [5:5] - read-only - - ACBG - Analog Comparator Bandgap Select - [6:6] - - - ACD - Analog Comparator Disable - [7:7] - - - - - ADCSRB - ADC Control and Status Register B - 0x2B - - - ACME - Analog Comparator Multiplexer Enable - [6:6] - - - - - DIDR1 - Digital Input Disable Register 1 - 0x2F - - - AIN0D - AIN0 Digital Input Disable - [0:0] - - - AIN1D - AIN1 Digital Input Disable - [1:1] - - - - - - - ADC - Analog-to-Digital Converter - 0x78 - - - ADC - ADC Data Register Bytes - 0x0 - 16 - - - 0 - 65535 - - - - - ADCSRA - The ADC Control and Status register A - 0x2 - read-write - - - ADPS - ADC Prescaler Select Bits - [2:0] - - true - - ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 - - - ADIE - ADC Interrupt Enable - [3:3] - - - ADIF - ADC Interrupt Flag - [4:4] - - - ADATE - ADC Auto Trigger Enable - [5:5] - - - ADSC - ADC Start Conversion - [6:6] - - - ADEN - ADC Enable - [7:7] - - - - - ADCSRB - The ADC Control and Status register B - 0x3 - - - ADTS - ADC Auto Trigger Source bits - [2:0] - - true - - - - VAL_0x00 - Free Running mode - 0 - - - VAL_0x01 - Analog Comparator - 1 - - - VAL_0x02 - External Interrupt Request 0 - 2 - - - VAL_0x03 - Timer/Counter0 Compare Match A - 3 - - - VAL_0x04 - Timer/Counter0 Overflow - 4 - - - VAL_0x05 - Timer/Counter1 Compare Match B - 5 - - - VAL_0x06 - Timer/Counter1 Overflow - 6 - - - VAL_0x07 - Timer/Counter1 Capture Event - 7 - - - - - MUX5 - Analog Channel and Gain Selection Bits - [3:3] - - - ACME - <TBD> - [6:6] - - - - - ADMUX - The ADC multiplexer Selection Register - 0x4 - - - MUX - Analog Channel and Gain Selection Bits - [4:0] - - true - - - - ADC0 - ADC Single Ended Input pin 0 - 0 - - - ADC1 - ADC Single Ended Input pin 1 - 1 - - - ADC2 - ADC Single Ended Input pin 2 - 2 - - - ADC3 - ADC Single Ended Input pin 3 - 3 - - - ADC4 - ADC Single Ended Input pin 4 - 4 - - - ADC5 - ADC Single Ended Input pin 5 - 5 - - - ADC6 - ADC Single Ended Input pin 6 - 6 - - - ADC7 - ADC Single Ended Input pin 7 - 7 - - - ADC0_ADC0_10X - ADC Differential Inputs Postive pin 0 Negative pin 0 10x Gain - 8 - - - ADC1_ADC0_10X - ADC Differential Inputs Postive pin 1 Negative pin 0 10x Gain - 9 - - - ADC0_ADC0_200x - ADC Differential Inputs Postive pin 0 Negative pin 0 200x Gain - 10 - - - ADC1_ADC0_200X - ADC Differential Inputs Postive pin 1 Negative pin 0 200x Gain - 11 - - - ADC2_ADC2_10X - ADC Differential Inputs Postive pin 2 Negative pin 2 10x Gain - 12 - - - ADC3_ADC2_10X - ADC Differential Inputs Postive pin 3 Negative pin 2 10x Gain - 13 - - - ADC2_ADC2_200X - ADC Differential Inputs Postive pin 2 Negative pin 2 200x Gain - 14 - - - ADC3_ADC2_200X - ADC Differential Inputs Postive pin 3 Negative pin 2 200x Gain - 15 - - - ADC0_ADC1_1X - ADC Differential Inputs Postive pin 0 Negative pin 1 1x Gain - 16 - - - ADC1_ADC1_1X - ADC Differential Inputs Postive pin 1 Negative pin 1 1x Gain - 17 - - - ADC2_ADC1_1X - ADC Differential Inputs Postive pin 2 Negative pin 1 1x Gain - 18 - - - ADC3_ADC1_1X - ADC Differential Inputs Postive pin 3 Negative pin 1 1x Gain - 19 - - - ADC4_ADC1_1X - ADC Differential Inputs Postive pin 4 Negative pin 1 1x Gain - 20 - - - ADC5_ADC1_1X - ADC Differential Inputs Postive pin 5 Negative pin 1 1x Gain - 21 - - - ADC6_ADC1_1X - ADC Differential Inputs Postive pin 6 Negative pin 1 1x Gain - 22 - - - ADC7_ADC1_1X - ADC Differential Inputs Postive pin 7 Negative pin 1 1x Gain - 23 - - - ADC0_ADC2_1X - ADC Differential Inputs Postive pin 0 Negative pin 2 1x Gain - 24 - - - ADC1_ADC2_1X - ADC Differential Inputs Postive pin 1 Negative pin 2 1x Gain - 25 - - - ADC2_ADC2_1X - ADC Differential Inputs Postive pin 2 Negative pin 2 1x Gain - 26 - - - ADC3_ADC2_1X - ADC Differential Inputs Postive pin 3 Negative pin 2 1x Gain - 27 - - - ADC4_ADC2_1X - ADC Differential Inputs Postive pin 4 Negative pin 2 1x Gain - 28 - - - ADC5_ADC2_1X - ADC Differential Inputs Postive pin 5 Negative pin 2 1x Gain - 29 - - - ADC_VBG - Internal Reference (VBG) - 30 - - - ADC_GND - 0V (GND) - 31 - - - - - ADLAR - Left Adjust Result - [5:5] - - - REFS - Reference Selection Bits - [7:6] - - true - - REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 - - - - - DIDR0 - Digital Input Disable Register - 0x6 - - - ADC0D - <TBD> - [0:0] - - - ADC1D - <TBD> - [1:1] - - - ADC2D - <TBD> - [2:2] - - - ADC3D - <TBD> - [3:3] - - - ADC4D - <TBD> - [4:4] - - - ADC5D - <TBD> - [5:5] - - - ADC6D - <TBD> - [6:6] - - - ADC7D - <TBD> - [7:7] - - - - - DIDR2 - Digital Input Disable Register - 0x5 - - - ADC8D - <TBD> - [0:0] - - - ADC9D - <TBD> - [1:1] - - - ADC10D - <TBD> - [2:2] - - - ADC11D - <TBD> - [3:3] - - - ADC12D - <TBD> - [4:4] - - - ADC13D - <TBD> - [5:5] - - - ADC14D - <TBD> - [6:6] - - - ADC15D - <TBD> - [7:7] - - - - - - - BOOT_LOAD - Bootloader - 0x57 - - - SPMCSR - Store Program Memory Control Register - 0x0 - - - SPMEN - Store Program Memory Enable - [0:0] - - - PGERS - Page Erase - [1:1] - - - PGWRT - Page Write - [2:2] - - - BLBSET - Boot Lock Bit Set - [3:3] - - - RWWSRE - Read While Write section read enable - [4:4] - - - SIGRD - Signature Row Read - [5:5] - - - RWWSB - Read While Write Section Busy - [6:6] - - - SPMIE - SPM Interrupt Enable - [7:7] - - - - - - - CPU - CPU Registers - 0x3E - - RESET - External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. - 0 - - - INT0 - External Interrupt Request 0 - 1 - - - INT1 - External Interrupt Request 1 - 2 - - - INT2 - External Interrupt Request 2 - 3 - - - INT3 - External Interrupt Request 3 - 4 - - - INT4 - External Interrupt Request 4 - 5 - - - INT5 - External Interrupt Request 5 - 6 - - - INT6 - External Interrupt Request 6 - 7 - - - INT7 - External Interrupt Request 7 - 8 - - - PCINT0 - Pin Change Interrupt Request 0 - 9 - - - PCINT1 - Pin Change Interrupt Request 1 - 10 - - - PCINT2 - Pin Change Interrupt Request 2 - 11 - - - WDT - Watchdog Time-out Interrupt - 12 - - - TIMER2_COMPA - Timer/Counter2 Compare Match A - 13 - - - TIMER2_COMPB - Timer/Counter2 Compare Match B - 14 - - - TIMER2_OVF - Timer/Counter2 Overflow - 15 - - - TIMER1_CAPT - Timer/Counter1 Capture Event - 16 - - - TIMER1_COMPA - Timer/Counter1 Compare Match A - 17 - - - TIMER1_COMPB - Timer/Counter1 Compare Match B - 18 - - - TIMER1_COMPC - Timer/Counter1 Compare Match C - 19 - - - TIMER1_OVF - Timer/Counter1 Overflow - 20 - - - TIMER0_COMPA - Timer/Counter0 Compare Match A - 21 - - - TIMER0_COMPB - Timer/Counter0 Compare Match B - 22 - - - TIMER0_OVF - Timer/Counter0 Overflow - 23 - - - SPI_STC - SPI Serial Transfer Complete - 24 - - - USART0_RX - USART0, Rx Complete - 25 - - - USART0_UDRE - USART0 Data register Empty - 26 - - - USART0_TX - USART0, Tx Complete - 27 - - - ANALOG_COMP - Analog Comparator - 28 - - - ADC - ADC Conversion Complete - 29 - - - EE_READY - EEPROM Ready - 30 - - - TIMER3_CAPT - Timer/Counter3 Capture Event - 31 - - - TIMER3_COMPA - Timer/Counter3 Compare Match A - 32 - - - TIMER3_COMPB - Timer/Counter3 Compare Match B - 33 - - - TIMER3_COMPC - Timer/Counter3 Compare Match C - 34 - - - TIMER3_OVF - Timer/Counter3 Overflow - 35 - - - USART1_RX - USART1, Rx Complete - 36 - - - USART1_UDRE - USART1 Data register Empty - 37 - - - USART1_TX - USART1, Tx Complete - 38 - - - TWI - 2-wire Serial Interface - 39 - - - SPM_READY - Store Program Memory Read - 40 - - - TIMER4_CAPT - Timer/Counter4 Capture Event - 41 - - - TIMER4_COMPA - Timer/Counter4 Compare Match A - 42 - - - TIMER4_COMPB - Timer/Counter4 Compare Match B - 43 - - - TIMER4_COMPC - Timer/Counter4 Compare Match C - 44 - - - TIMER4_OVF - Timer/Counter4 Overflow - 45 - - - TIMER5_CAPT - Timer/Counter5 Capture Event - 46 - - - TIMER5_COMPA - Timer/Counter5 Compare Match A - 47 - - - TIMER5_COMPB - Timer/Counter5 Compare Match B - 48 - - - TIMER5_COMPC - Timer/Counter5 Compare Match C - 49 - - - TIMER5_OVF - Timer/Counter5 Overflow - 50 - - - USART2_RX - USART2, Rx Complete - 51 - - - USART2_UDRE - USART2 Data register Empty - 52 - - - USART2_TX - USART2, Tx Complete - 53 - - - USART3_RX - USART3, Rx Complete - 54 - - - USART3_UDRE - USART3 Data register Empty - 55 - - - USART3_TX - USART3, Tx Complete - 56 - - - - CLKPR - <TBD> - 0x23 - - - CLKPS - <TBD> - [3:0] - - true - - - - VAL_0x00 - 1 - 0 - - - VAL_0x01 - 2 - 1 - - - VAL_0x02 - 4 - 2 - - - VAL_0x03 - 8 - 3 - - - VAL_0x04 - 16 - 4 - - - VAL_0x05 - 32 - 5 - - - VAL_0x06 - 64 - 6 - - - VAL_0x07 - 128 - 7 - - - VAL_0x08 - 256 - 8 - - - - - CLKPCE - <TBD> - [7:7] - - - - - EIND - Extended Indirect Register - 0x1E - - - 0 - 255 - - - - - GPIOR0 - General Purpose IO Register 0 - 0x0 - - - GPIOR00 - General Purpose IO Register 0 bit 0 - [0:0] - - - GPIOR01 - General Purpose IO Register 0 bit 1 - [1:1] - - - GPIOR02 - General Purpose IO Register 0 bit 2 - [2:2] - - - GPIOR03 - General Purpose IO Register 0 bit 3 - [3:3] - - - GPIOR04 - General Purpose IO Register 0 bit 4 - [4:4] - - - GPIOR05 - General Purpose IO Register 0 bit 5 - [5:5] - - - GPIOR06 - General Purpose IO Register 0 bit 6 - [6:6] - - - GPIOR07 - General Purpose IO Register 0 bit 7 - [7:7] - - - - - GPIOR1 - General Purpose IO Register 1 - 0xC - - - GPIOR - General Purpose IO Register 1 bis - [7:0] - - - 0 - 255 - - - - - - - GPIOR2 - General Purpose IO Register 2 - 0xD - - - GPIOR - General Purpose IO Register 2 bis - [7:0] - - - 0 - 255 - - - - - - - MCUCR - MCU Control Register - 0x17 - - - IVCE - Interrupt Vector Change Enable - [0:0] - - - IVSEL - Interrupt Vector Select - [1:1] - - - PUD - Pull-up disable - [4:4] - - - JTD - JTAG Interface Disable - [7:7] - - - - - MCUSR - MCU Status Register - 0x16 - read-only - - - PORF - Power-on reset flag - [0:0] - - - EXTRF - External Reset Flag - [1:1] - - - BORF - Brown-out Reset Flag - [2:2] - - - WDRF - Watchdog Reset Flag - [3:3] - - - JTRF - JTAG Reset Flag - [4:4] - - - - - OSCCAL - Oscillator Calibration Value - 0x28 - - - OSCCAL - Oscillator Calibration - [7:0] - - - 0 - 255 - - - - - - - PRR0 - Power Reduction Register0 - 0x26 - - - PRADC - Power Reduction ADC - [0:0] - - - PRUSART0 - Power Reduction USART0 - [1:1] - - - PRSPI - Power Reduction Serial Peripheral Interface - [2:2] - - - PRTIM1 - Power Reduction Timer/Counter1 - [3:3] - - - PRTIM0 - Power Reduction Timer/Counter0 - [5:5] - - - PRTIM2 - Power Reduction Timer/Counter2 - [6:6] - - - PRTWI - Power Reduction TWI - [7:7] - - - - - PRR1 - Power Reduction Register1 - 0x27 - - - PRUSART1 - Power Reduction USART1 - [0:0] - - - PRUSART2 - Power Reduction USART2 - [1:1] - - - PRUSART3 - Power Reduction USART3 - [2:2] - - - PRTIM3 - Power Reduction Timer/Counter3 - [3:3] - - - PRTIM4 - Power Reduction Timer/Counter4 - [4:4] - - - PRTIM5 - Power Reduction Timer/Counter5 - [5:5] - - - - - RAMPZ - RAM Page Z Select Register - 0x1D - - - 0 - 255 - - - - - SMCR - Sleep Mode Control Register - 0x15 - - - SE - Sleep Enable - [0:0] - - - SM - Sleep Mode Select bits - [3:1] - - true - - - - IDLE - Idle - 0 - - - ADC - ADC Noise Reduction (If Available) - 1 - - - PDOWN - Power Down - 2 - - - PSAVE - Power Save - 3 - - - VAL_0x04 - Reserved - 4 - - - VAL_0x05 - Reserved - 5 - - - STDBY - Standby - 6 - - - ESTDBY - Extended Standby - 7 - - - - - - - XMCRA - External Memory Control Register A - 0x36 - - - SRW0 - Wait state select bit lower page - [1:0] - - true - - - - VAL_0x00 - No wait-states - 0 - - - VAL_0x01 - Wait one cycle during read/write strobe - 1 - - - VAL_0x02 - Wait two cycles during read/write strobe - 2 - - - VAL_0x03 - Wait two cycles during read/write and wait one cycle before driving out new address - 3 - - - - - SRW1 - Wait state select bit upper page - [3:2] - - true - - - - VAL_0x00 - No wait-states - 0 - - - VAL_0x01 - Wait one cycle during read/write strobe - 1 - - - VAL_0x02 - Wait two cycles during read/write strobe - 2 - - - VAL_0x03 - Wait two cycles during read/write and wait one cycle before driving out new address - 3 - - - - - SRL - Wait state page limit - [6:4] - - true - - - - VAL_0x00 - LS = N/A, US = 0x1100 - 0xFFFF - 0 - - - VAL_0x01 - LS = 0x2200 - 0x1FFF, US = 0x2000 - 0xFFFF - 1 - - - VAL_0x02 - LS = 0x2200 - 0x3FFF, US = 0x4000 - 0xFFFF - 2 - - - VAL_0x03 - LS = 0x2200 - 0x5FFF, US = 0x6000 - 0xFFFF - 3 - - - VAL_0x04 - LS = 0x2200 - 0x7FFF, US = 0x8000 - 0xFFFF - 4 - - - VAL_0x05 - LS = 0x2200 - 0x9FFF, US = 0xA000 - 0xFFFF - 5 - - - VAL_0x06 - LS = 0x2200 - 0xBFFF, US = 0xC000 - 0xFFFF - 6 - - - VAL_0x07 - LS = 0x2200 - 0xDFFF, US = 0xE000 - 0xFFFF - 7 - - - - - SRE - External SRAM Enable - [7:7] - - - - - XMCRB - External Memory Control Register B - 0x37 - - - XMM - External Memory High Mask - [2:0] - - - 0 - 7 - - - - - XMBK - External Memory Bus Keeper Enable - [7:7] - - - - - - - EEPROM - EEPROM - 0x3F - - - EEAR - EEPROM Address Register Low Bytes - 0x2 - 16 - - - 0 - 65535 - - - - - EECR - EEPROM Control Register - 0x0 - - - EERE - EEPROM Read Enable - [0:0] - - - EEPE - EEPROM Write Enable - [1:1] - - - EEMPE - EEPROM Master Write Enable - [2:2] - - - EERIE - EEPROM Ready Interrupt Enable - [3:3] - - - EEPM - EEPROM Programming Mode Bits - [5:4] - - true - - - - VAL_0x00 - Erase and Write in one operation - 0 - - - VAL_0x01 - Erase Only - 1 - - - VAL_0x02 - Write Only - 2 - - - - - - - EEDR - EEPROM Data Register - 0x1 - - - 0 - 255 - - - - - - - EXINT - External Interrupts - 0x3B - - - EICRA - External Interrupt Control Register A - 0x2E - - - ISC0 - External Interrupt Sense Control Bit - [1:0] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC1 - External Interrupt Sense Control Bit - [3:2] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC2 - External Interrupt Sense Control Bit - [5:4] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC3 - External Interrupt Sense Control Bit - [7:6] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - - - EICRB - External Interrupt Control Register B - 0x2F - - - ISC4 - External Interrupt 7-4 Sense Control Bit - [1:0] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC5 - External Interrupt 7-4 Sense Control Bit - [3:2] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC6 - External Interrupt 7-4 Sense Control Bit - [5:4] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC7 - External Interrupt 7-4 Sense Control Bit - [7:6] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - - - EIFR - External Interrupt Flag Register - 0x1 - read-only - - - INTF - External Interrupt Flags - [7:0] - - - 0 - 255 - - - - - - - EIMSK - External Interrupt Mask Register - 0x2 - - - INT - External Interrupt Request 7 Enable - [7:0] - - - 0 - 255 - - - - - - - PCICR - Pin Change Interrupt Control Register - 0x2D - - - PCIE - Pin Change Interrupt Enables - [2:0] - - - 0 - 7 - - - - - - - PCIFR - Pin Change Interrupt Flag Register - 0x0 - read-only - - - PCIF - Pin Change Interrupt Flags - [2:0] - - - 0 - 7 - - - - - - - PCMSK0 - Pin Change Mask Register 0 - 0x30 - - - PCINT - Pin Change Mask interrupt - [7:0] - - - 0 - 255 - - - - - - - PCMSK1 - Pin Change Mask Register 1 - 0x31 - - - PCINT - Pin Change Mask interrupt - [7:0] - - - 0 - 255 - - - - - - - PCMSK2 - Pin Change Mask Register 2 - 0x32 - - - PCINT - Pin Change Mask interrupt - [7:0] - - - 0 - 255 - - - - - - - - - FUSE - Fuses - 0x0 - - - EXTENDED - <TBD> - 0x2 - - - BODLEVEL - Brown-out Detector trigger level - [2:0] - - true - - - - 4V3 - Brown-out detection at VCC=4.3 V - 4 - - - 2V7 - Brown-out detection at VCC=2.7 V - 5 - - - 1V8 - Brown-out detection at VCC=1.8 V - 6 - - - DISABLED - Brown-out detection disabled - 7 - - - - - - - HIGH - <TBD> - 0x1 - - - BOOTRST - Boot Reset vector Enabled - [0:0] - - - BOOTSZ - Select Boot Size - [2:1] - - true - - - - 4096W_1F000 - Boot Flash size=4096 words start address=$1F000 - 0 - - - 2048W_1F800 - Boot Flash size=2048 words start address=$1F800 - 1 - - - 1024W_1FC00 - Boot Flash size=1024 words start address=$1FC00 - 2 - - - 512W_1FE00 - Boot Flash size=512 words start address=$1FE00 - 3 - - - - - EESAVE - Preserve EEPROM through the Chip Erase cycle - [3:3] - - - WDTON - Watchdog timer always on - [4:4] - - - SPIEN - Serial program downloading (SPI) enabled - [5:5] - - - JTAGEN - JTAG Interface Enabled - [6:6] - - - OCDEN - On-Chip Debug Enabled - [7:7] - - - - - LOW - <TBD> - 0x0 - - - SUT_CKSEL - Select Clock Source - [5:0] - - true - - - - EXTCLK_6CK_0MS - Ext. Clock; Start-up time: 6 CK + 0 ms - 0 - - - INTRCOSC_6CK_0MS - Int. RC Osc.; Start-up time: 6 CK + 0 ms - 2 - - - INTRCOSC_128KHZ_6CK_0MS - Int. 128kHz RC Osc.; Start-up time: 6 CK + 0 ms - 3 - - - EXTLOFXTAL_1KCK_0MS - Ext. Low-Freq. Crystal; Start-up time: 1K CK + 0 ms - 4 - - - EXTLOFXTAL_32KCK_0MS - Ext. Low-Freq. Crystal; Start-up time: 32K CK + 0 ms - 5 - - - FSOSC_258CK_4MS1_CRES_FASTPWR - Full Swing Oscillator; Start-up time: 258 CK + 4.1 ms; Ceramic res.; fast rising power - 6 - - - FSOSC_1KCK_65MS_CRES_SLOWPWR - Full Swing Oscillator; Start-up time: 1K CK + 65 ms; Ceramic res.; slowly rising power - 7 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 258 CK + 4.1 ms - 8 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 65 ms - 9 - - - EXTXOSC_0MHZ9_3MHZ_258CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 258 CK + 4.1 ms - 10 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 65 ms - 11 - - - EXTXOSC_3MHZ_8MHZ_258CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 258 CK + 4.1 ms - 12 - - - EXTXOSC_3MHZ_8MHZ_1KCK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 65 ms - 13 - - - EXTXOSC_8MHZ_XX_258CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time: 258 CK + 4.1 ms - 14 - - - EXTXOSC_8MHZ_XX_1KCK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 65 ms - 15 - - - EXTCLK_6CK_4MS1 - Ext. Clock; Start-up time: 6 CK + 4.1 ms - 16 - - - INTRCOSC_6CK_4MS1 - Int. RC Osc.; Start-up time: 6 CK + 4.1 ms - 18 - - - INTRCOSC_128KHZ_6CK_4MS - Int. 128kHz RC Osc.; Start-up time: 6 CK + 4 ms - 19 - - - EXTLOFXTAL_1KCK_4MS1 - Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4.1 ms - 20 - - - EXTLOFXTAL_32KCK_4MS1 - Ext. Low-Freq. Crystal; Start-up time: 32K CK + 4.1 ms - 21 - - - FSOSC_258CK_65MS_CRES_SLOWPWR - Full Swing Oscillator; Start-up time: 258 CK + 65 ms; Ceramic res.; slowly rising power - 22 - - - FSOSC_16KCK_0MS_XOSC_BODEN - Full Swing Oscillator; Start-up time: 16K CK + 0 ms; Crystal Osc.; BOD enabled - 23 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 258 CK + 65 ms - 24 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 0 ms - 25 - - - EXTXOSC_0MHZ9_3MHZ_258CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 258 CK + 65 ms - 26 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 0 ms - 27 - - - EXTXOSC_3MHZ_8MHZ_258CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 258 CK + 65 ms - 28 - - - EXTXOSC_3MHZ_8MHZ_16KCK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 0 ms - 29 - - - EXTXOSC_8MHZ_XX_258CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 258 CK + 65 ms - 30 - - - EXTXOSC_8MHZ_XX_16KCK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 0 ms - 31 - - - EXTCLK_6CK_65MS - Ext. Clock; Start-up time: 6 CK + 65 ms - 32 - - - INTRCOSC_6CK_65MS - Int. RC Osc.; Start-up time: 6 CK + 65 ms - 34 - - - INTRCOSC_128KHZ_6CK_64MS - Int. 128kHz RC Osc.; Start-up time: 6 CK + 64 ms - 35 - - - EXTLOFXTAL_1KCK_65MS - Ext. Low-Freq. Crystal; Start-up time: 1K CK + 65 ms - 36 - - - EXTLOFXTAL_32KCK_65MS - Ext. Low-Freq. Crystal; Start-up time: 32K CK + 65 ms - 37 - - - FSOSC_1KCK_0MS_CRES_BODEN - Full Swing Oscillator; Start-up time: 1K CK + 0 ms; Ceramic res.; BOD enable - 38 - - - FSOSC_16KCK_4MS1_XOSC_FASTPWR - Full Swing Oscillator; Start-up time: 16K CK + 4.1 ms; Crystal Osc.; fast rising power - 39 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 0 ms - 40 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 4.1 ms - 41 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 0 ms - 42 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 4.1 ms - 43 - - - EXTXOSC_3MHZ_8MHZ_1KCK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 0 ms - 44 - - - EXTXOSC_3MHZ_8MHZ_16KCK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 4.1 ms - 45 - - - EXTXOSC_8MHZ_XX_1KCK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 0 ms - 46 - - - EXTXOSC_8MHZ_XX_16KCK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 4.1 ms - 47 - - - FSOSC_1KCK_4MS1_CRES_FASTPWR - Full Swing Oscillator; Start-up time: 1K CK + 4.1 ms; Ceramic res.; fast rising power - 54 - - - FSOSC_16KCK_65MS_XOSC_SLOWPWR - Full Swing Oscillator; Start-up time: 16K CK + 65 ms; Crystal Osc.; slowly rising power - 55 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 4.1 ms - 56 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 65 ms - 57 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 4.1 ms - 58 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 65 ms - 59 - - - EXTXOSC_3MHZ_8MHZ_1KCK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 4.1 ms - 60 - - - EXTXOSC_3MHZ_8MHZ_16KCK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 65 ms - 61 - - - EXTXOSC_8MHZ_XX_1KCK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 4.1 ms - 62 - - - EXTXOSC_8MHZ_XX_16KCK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 65 ms - 63 - - - - - CKOUT - Clock output on PORTE7 - [6:6] - - - CKDIV8 - Divide clock by 8 internally - [7:7] - - - - - - - JTAG - JTAG Interface - 0x51 - - - MCUCR - MCU Control Register - 0x4 - - - JTD - JTAG Interface Disable - [7:7] - - - - - MCUSR - MCU Status Register - 0x3 - read-only - - - JTRF - JTAG Reset Flag - [4:4] - - - - - OCDR - On-Chip Debug Related Register in I/O Memory - 0x0 - - - 0 - 255 - - - - - - - LOCKBIT - Lockbits - 0x0 - - - LOCKBIT - <TBD> - 0x0 - - - LB - Memory Lock - [1:0] - - true - - - - PROG_VER_DISABLED - Further programming and verification disabled - 0 - - - PROG_DISABLED - Further programming disabled - 2 - - - NO_LOCK - No memory lock features enabled - 3 - - - - - BLB0 - Boot Loader Protection Mode - [3:2] - - true - - - - LPM_SPM_DISABLE - LPM and SPM prohibited in Application Section - 0 - - - LPM_DISABLE - LPM prohibited in Application Section - 1 - - - SPM_DISABLE - SPM prohibited in Application Section - 2 - - - NO_LOCK - No lock on SPM and LPM in Application Section - 3 - - - - - BLB1 - Boot Loader Protection Mode - [5:4] - - true - - - - LPM_SPM_DISABLE - LPM and SPM prohibited in Boot Section - 0 - - - LPM_DISABLE - LPM prohibited in Boot Section - 1 - - - SPM_DISABLE - SPM prohibited in Boot Section - 2 - - - NO_LOCK - No lock on SPM and LPM in Boot Section - 3 - - - - - - - - - PORTA - I/O Port - 0x20 - - - DDRA - Port A Data Direction Register - 0x1 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - PINA - Port A Input Pins - 0x0 - read-write - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - PORTA - Port A Data Register - 0x2 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - - - PORTB - I/O Port - 0x23 - - - DDRB - Port B Data Direction Register - 0x1 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PINB - Port B Input Pins - 0x0 - read-write - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PORTB - Port B Data Register - 0x2 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - - - PORTC - I/O Port - 0x26 - - - DDRC - Port C Data Direction Register - 0x1 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - PINC - Port C Input Pins - 0x0 - read-write - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - PORTC - Port C Data Register - 0x2 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - - - PORTD - I/O Port - 0x29 - - - DDRD - Port D Data Direction Register - 0x1 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PIND - Port D Input Pins - 0x0 - read-write - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PORTD - Port D Data Register - 0x2 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - - - PORTE - I/O Port - 0x2C - - - DDRE - Data Direction Register, Port E - 0x1 - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - PE4 - Pin E4 - [4:4] - - - PE5 - Pin E5 - [5:5] - - - PE6 - Pin E6 - [6:6] - - - PE7 - Pin E7 - [7:7] - - - - - PINE - Input Pins, Port E - 0x0 - read-write - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - PE4 - Pin E4 - [4:4] - - - PE5 - Pin E5 - [5:5] - - - PE6 - Pin E6 - [6:6] - - - PE7 - Pin E7 - [7:7] - - - - - PORTE - Data Register, Port E - 0x2 - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - PE4 - Pin E4 - [4:4] - - - PE5 - Pin E5 - [5:5] - - - PE6 - Pin E6 - [6:6] - - - PE7 - Pin E7 - [7:7] - - - - - - - PORTF - I/O Port - 0x2F - - - DDRF - Data Direction Register, Port F - 0x1 - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF2 - Pin F2 - [2:2] - - - PF3 - Pin F3 - [3:3] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - PF7 - Pin F7 - [7:7] - - - - - PINF - Input Pins, Port F - 0x0 - read-write - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF2 - Pin F2 - [2:2] - - - PF3 - Pin F3 - [3:3] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - PF7 - Pin F7 - [7:7] - - - - - PORTF - Data Register, Port F - 0x2 - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF2 - Pin F2 - [2:2] - - - PF3 - Pin F3 - [3:3] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - PF7 - Pin F7 - [7:7] - - - - - - - PORTG - I/O Port - 0x32 - - - DDRG - Data Direction Register, Port G - 0x1 - - - PG0 - Pin G0 - [0:0] - - - PG1 - Pin G1 - [1:1] - - - PG2 - Pin G2 - [2:2] - - - PG3 - Pin G3 - [3:3] - - - PG4 - Pin G4 - [4:4] - - - PG5 - Pin G5 - [5:5] - - - PG6 - Pin G6 - [6:6] - - - PG7 - Pin G7 - [7:7] - - - - - PING - Input Pins, Port G - 0x0 - read-write - - PG0 - Pin G0 - [0:0] - - - PG1 - Pin G1 - [1:1] - - - PG2 - Pin G2 - [2:2] - - - PG3 - Pin G3 - [3:3] - - - PG4 - Pin G4 - [4:4] - - - PG5 - Pin G5 - [5:5] - - - PG6 - Pin G6 - [6:6] - - - PG7 - Pin G7 - [7:7] - - - - - PORTG - Data Register, Port G - 0x2 - - - PG0 - Pin G0 - [0:0] - - - PG1 - Pin G1 - [1:1] - - - PG2 - Pin G2 - [2:2] - - - PG3 - Pin G3 - [3:3] - - - PG4 - Pin G4 - [4:4] - - - PG5 - Pin G5 - [5:5] - - - PG6 - Pin G6 - [6:6] - - - PG7 - Pin G7 - [7:7] - - - - - - - PORTH - I/O Port - 0x100 - - - DDRH - PORT H Data Direction Register - 0x1 - - - PH0 - Pin H0 - [0:0] - - - PH1 - Pin H1 - [1:1] - - - PH2 - Pin H2 - [2:2] - - - PH3 - Pin H3 - [3:3] - - - PH4 - Pin H4 - [4:4] - - - PH5 - Pin H5 - [5:5] - - - PH6 - Pin H6 - [6:6] - - - PH7 - Pin H7 - [7:7] - - - - - PINH - PORT H Input Pins - 0x0 - read-write - - PH0 - Pin H0 - [0:0] - - - PH1 - Pin H1 - [1:1] - - - PH2 - Pin H2 - [2:2] - - - PH3 - Pin H3 - [3:3] - - - PH4 - Pin H4 - [4:4] - - - PH5 - Pin H5 - [5:5] - - - PH6 - Pin H6 - [6:6] - - - PH7 - Pin H7 - [7:7] - - - - - PORTH - PORT H Data Register - 0x2 - - - PH0 - Pin H0 - [0:0] - - - PH1 - Pin H1 - [1:1] - - - PH2 - Pin H2 - [2:2] - - - PH3 - Pin H3 - [3:3] - - - PH4 - Pin H4 - [4:4] - - - PH5 - Pin H5 - [5:5] - - - PH6 - Pin H6 - [6:6] - - - PH7 - Pin H7 - [7:7] - - - - - - - PORTJ - I/O Port - 0x103 - - - DDRJ - PORT J Data Direction Register - 0x1 - - - PJ0 - Pin J0 - [0:0] - - - PJ1 - Pin J1 - [1:1] - - - PJ2 - Pin J2 - [2:2] - - - PJ3 - Pin J3 - [3:3] - - - PJ4 - Pin J4 - [4:4] - - - PJ5 - Pin J5 - [5:5] - - - PJ6 - Pin J6 - [6:6] - - - PJ7 - Pin J7 - [7:7] - - - - - PINJ - PORT J Input Pins - 0x0 - read-write - - PJ0 - Pin J0 - [0:0] - - - PJ1 - Pin J1 - [1:1] - - - PJ2 - Pin J2 - [2:2] - - - PJ3 - Pin J3 - [3:3] - - - PJ4 - Pin J4 - [4:4] - - - PJ5 - Pin J5 - [5:5] - - - PJ6 - Pin J6 - [6:6] - - - PJ7 - Pin J7 - [7:7] - - - - - PORTJ - PORT J Data Register - 0x2 - - - PJ0 - Pin J0 - [0:0] - - - PJ1 - Pin J1 - [1:1] - - - PJ2 - Pin J2 - [2:2] - - - PJ3 - Pin J3 - [3:3] - - - PJ4 - Pin J4 - [4:4] - - - PJ5 - Pin J5 - [5:5] - - - PJ6 - Pin J6 - [6:6] - - - PJ7 - Pin J7 - [7:7] - - - - - - - PORTK - I/O Port - 0x106 - - - DDRK - PORT K Data Direction Register - 0x1 - - - PK0 - Pin K0 - [0:0] - - - PK1 - Pin K1 - [1:1] - - - PK2 - Pin K2 - [2:2] - - - PK3 - Pin K3 - [3:3] - - - PK4 - Pin K4 - [4:4] - - - PK5 - Pin K5 - [5:5] - - - PK6 - Pin K6 - [6:6] - - - PK7 - Pin K7 - [7:7] - - - - - PINK - PORT K Input Pins - 0x0 - read-write - - PK0 - Pin K0 - [0:0] - - - PK1 - Pin K1 - [1:1] - - - PK2 - Pin K2 - [2:2] - - - PK3 - Pin K3 - [3:3] - - - PK4 - Pin K4 - [4:4] - - - PK5 - Pin K5 - [5:5] - - - PK6 - Pin K6 - [6:6] - - - PK7 - Pin K7 - [7:7] - - - - - PORTK - PORT K Data Register - 0x2 - - - PK0 - Pin K0 - [0:0] - - - PK1 - Pin K1 - [1:1] - - - PK2 - Pin K2 - [2:2] - - - PK3 - Pin K3 - [3:3] - - - PK4 - Pin K4 - [4:4] - - - PK5 - Pin K5 - [5:5] - - - PK6 - Pin K6 - [6:6] - - - PK7 - Pin K7 - [7:7] - - - - - - - PORTL - I/O Port - 0x109 - - - DDRL - PORT L Data Direction Register - 0x1 - - - PL0 - Pin L0 - [0:0] - - - PL1 - Pin L1 - [1:1] - - - PL2 - Pin L2 - [2:2] - - - PL3 - Pin L3 - [3:3] - - - PL4 - Pin L4 - [4:4] - - - PL5 - Pin L5 - [5:5] - - - PL6 - Pin L6 - [6:6] - - - PL7 - Pin L7 - [7:7] - - - - - PINL - PORT L Input Pins - 0x0 - read-write - - PL0 - Pin L0 - [0:0] - - - PL1 - Pin L1 - [1:1] - - - PL2 - Pin L2 - [2:2] - - - PL3 - Pin L3 - [3:3] - - - PL4 - Pin L4 - [4:4] - - - PL5 - Pin L5 - [5:5] - - - PL6 - Pin L6 - [6:6] - - - PL7 - Pin L7 - [7:7] - - - - - PORTL - PORT L Data Register - 0x2 - - - PL0 - Pin L0 - [0:0] - - - PL1 - Pin L1 - [1:1] - - - PL2 - Pin L2 - [2:2] - - - PL3 - Pin L3 - [3:3] - - - PL4 - Pin L4 - [4:4] - - - PL5 - Pin L5 - [5:5] - - - PL6 - Pin L6 - [6:6] - - - PL7 - Pin L7 - [7:7] - - - - - - - SPI - Serial Peripheral Interface - 0x4C - - - SPCR - SPI Control Register - 0x0 - - - SPR - SPI Clock Rate Selects - [1:0] - - true - - SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 - - - CPHA - Clock Phase - [2:2] - - - CPOL - Clock polarity - [3:3] - - - MSTR - Master/Slave Select - [4:4] - - - DORD - Data Order - [5:5] - - - SPE - SPI Enable - [6:6] - - - SPIE - SPI Interrupt Enable - [7:7] - - - - - SPDR - SPI Data Register - 0x2 - - - 0 - 255 - - - - - SPSR - SPI Status Register - 0x1 - read-write - - - SPI2X - Double SPI Speed Bit - [0:0] - read-write - - WCOL - Write Collision Flag - [6:6] - read-only - - SPIF - SPI Interrupt Flag - [7:7] - read-only - - - - - - TC0 - Timer/Counter, 8-bit - 0x35 - - - GTCCR - General Timer/Counter Control Register - 0xE - - - PSRSYNC - Prescaler Reset Timer/Counter1 and Timer/Counter0 - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - OCR0A - Timer/Counter0 Output Compare Register - 0x12 - - - 0 - 255 - - - - - OCR0B - Timer/Counter0 Output Compare Register - 0x13 - - - 0 - 255 - - - - - TCCR0A - Timer/Counter Control Register A - 0xF - - - WGM0 - Waveform Generation Mode - [1:0] - - true - WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 - - - COM0B - Compare Output B Mode - [5:4] - - true - COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 - - - COM0A - Compare Output A Mode - [7:6] - - true - - - - - - TCCR0B - Timer/Counter Control Register B - 0x10 - - - CS0 - Clock Select - [2:0] - - true - - CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM02 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) - [3:3] - - - FOC0B - Force Output Compare B - [6:6] - write-only - - FOC0A - Force Output Compare A - [7:7] - write-only - - - - TCNT0 - Timer/Counter0 - 0x11 - - - 0 - 255 - - - - - TIFR0 - Timer/Counter0 Interrupt Flag register - 0x0 - read-write - - - TOV0 - Timer/Counter0 Overflow Flag - [0:0] - - - OCF0A - Timer/Counter0 Output Compare Flag 0A - [1:1] - - - OCF0B - Timer/Counter0 Output Compare Flag 0B - [2:2] - - - - - TIMSK0 - Timer/Counter0 Interrupt Mask Register - 0x39 - - - TOIE0 - Timer/Counter0 Overflow Interrupt Enable - [0:0] - - - OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable - [2:2] - - - - - - - TC1 - Timer/Counter, 16-bit - 0x36 - - - ICR1 - Timer/Counter1 Input Capture Register Bytes - 0x50 - 16 - - - 0 - 65535 - - - - - OCR1A - Timer/Counter1 Output Compare Register A Bytes - 0x52 - 16 - - - 0 - 65535 - - - - - OCR1B - Timer/Counter1 Output Compare Register B Bytes - 0x54 - 16 - - - 0 - 65535 - - - - - OCR1C - Timer/Counter1 Output Compare Register C Bytes - 0x56 - 16 - - - 0 - 65535 - - - - - TCCR1A - Timer/Counter1 Control Register A - 0x4A - - - WGM1 - Waveform Generation Mode - [1:0] - - - 0 - 3 - - - - - COM1C - Compare Output Mode 1C, bits - [3:2] - - true - COM1Cread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM1B - Compare Output Mode 1B, bits - [5:4] - - true - - - - COM1A - Compare Output Mode 1A, bits - [7:6] - - true - - - - - - TCCR1B - Timer/Counter1 Control Register B - 0x4B - - - CS1 - Prescaler source of Timer/Counter 1 - [2:0] - - true - CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM1 - Waveform Generation Mode - [4:3] - - - 0 - 3 - - - - - ICES1 - Input Capture 1 Edge Select - [6:6] - - - ICNC1 - Input Capture 1 Noise Canceler - [7:7] - - - - - TCCR1C - Timer/Counter 1 Control Register C - 0x4C - - - FOC1C - Force Output Compare 1C - [5:5] - write-only - - FOC1B - Force Output Compare 1B - [6:6] - write-only - - FOC1A - Force Output Compare 1A - [7:7] - write-only - - - - TCNT1 - Timer/Counter1 Bytes - 0x4E - 16 - - - 0 - 65535 - - - - - TIFR1 - Timer/Counter1 Interrupt Flag register - 0x0 - read-write - - - TOV1 - Timer/Counter1 Overflow Flag - [0:0] - - - OCF1A - Output Compare Flag 1A - [1:1] - - - OCF1B - Output Compare Flag 1B - [2:2] - - - OCF1C - Output Compare Flag 1C - [3:3] - - - ICF1 - Input Capture Flag 1 - [5:5] - - - - - TIMSK1 - Timer/Counter1 Interrupt Mask Register - 0x39 - - - TOIE1 - Timer/Counter1 Overflow Interrupt Enable - [0:0] - - - OCIE1A - Timer/Counter1 Output Compare A Match Interrupt Enable - [1:1] - - - OCIE1B - Timer/Counter1 Output Compare B Match Interrupt Enable - [2:2] - - - OCIE1C - Timer/Counter1 Output Compare C Match Interrupt Enable - [3:3] - - - ICIE1 - Timer/Counter1 Input Capture Interrupt Enable - [5:5] - - - - - - - TC2 - Timer/Counter, 8-bit Async - 0x37 - - - ASSR - Asynchronous Status Register - 0x7F - - - TCR2BUB - Timer/Counter Control Register2 Update Busy - [0:0] - - - TCR2AUB - Timer/Counter Control Register2 Update Busy - [1:1] - - - OCR2BUB - Output Compare Register 2 Update Busy - [2:2] - - - OCR2AUB - Output Compare Register2 Update Busy - [3:3] - - - TCN2UB - Timer/Counter2 Update Busy - [4:4] - - - AS2 - Asynchronous Timer/Counter2 - [5:5] - - - EXCLK - Enable External Clock Input - [6:6] - - - - - GTCCR - General Timer Counter Control register - 0xC - - - PSRASY - Prescaler Reset Timer/Counter2 - [1:1] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - OCR2A - Timer/Counter2 Output Compare Register A - 0x7C - - - 0 - 255 - - - - - OCR2B - Timer/Counter2 Output Compare Register B - 0x7D - - - 0 - 255 - - - - - TCCR2A - Timer/Counter2 Control Register A - 0x79 - - - WGM2 - Waveform Genration Mode - [1:0] - - true - WGM2read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 - - - COM2B - Compare Output B Mode - [5:4] - - true - COM2Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 - - - COM2A - Compare Output A Mode - [7:6] - - true - - - - - - TCCR2B - Timer/Counter2 Control Register B - 0x7A - - - CS2 - Clock Select bits - [2:0] - - true - - CS2read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_32Running, CLK/323PRESCALE_64Running, CLK/644PRESCALE_128Running, CLK/1285PRESCALE_256Running, CLK/2566PRESCALE_1024Running, CLK/10247 - - - WGM22 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) - [3:3] - - - FOC2B - Force Output Compare B - [6:6] - write-only - - FOC2A - Force Output Compare A - [7:7] - write-only - - - - TCNT2 - Timer/Counter2 - 0x7B - - - 0 - 255 - - - - - TIFR2 - Timer/Counter Interrupt Flag Register - 0x0 - read-write - - - TOV2 - Timer/Counter2 Overflow Flag - [0:0] - - - OCF2A - Output Compare Flag 2A - [1:1] - - - OCF2B - Output Compare Flag 2B - [2:2] - - - - - TIMSK2 - Timer/Counter Interrupt Mask register - 0x39 - - - TOIE2 - Timer/Counter2 Overflow Interrupt Enable - [0:0] - - - OCIE2A - Timer/Counter2 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE2B - Timer/Counter2 Output Compare Match B Interrupt Enable - [2:2] - - - - - - - TC3 - Timer/Counter, 16-bit - 0x38 - - - ICR3 - Timer/Counter3 Input Capture Register Bytes - 0x5E - 16 - - - 0 - 65535 - - - - - OCR3A - Timer/Counter3 Output Compare Register A Bytes - 0x60 - 16 - - - 0 - 65535 - - - - - OCR3B - Timer/Counter3 Output Compare Register B Bytes - 0x62 - 16 - - - 0 - 65535 - - - - - OCR3C - Timer/Counter3 Output Compare Register B Bytes - 0x64 - 16 - - - 0 - 65535 - - - - - TCCR3A - Timer/Counter3 Control Register A - 0x58 - - - WGM3 - Waveform Generation Mode - [1:0] - - - 0 - 3 - - - - - COM3C - Compare Output Mode 3C, bits - [3:2] - - true - COM3Cread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM3B - Compare Output Mode 3B, bits - [5:4] - - true - - - - COM3A - Compare Output Mode 1A, bits - [7:6] - - true - - - - - - TCCR3B - Timer/Counter3 Control Register B - 0x59 - - - CS3 - Prescaler source of Timer/Counter 3 - [2:0] - - true - CS3read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM3 - Waveform Generation Mode - [4:3] - - - 0 - 3 - - - - - ICES3 - Input Capture 3 Edge Select - [6:6] - - - ICNC3 - Input Capture 3 Noise Canceler - [7:7] - - - - - TCCR3C - Timer/Counter 3 Control Register C - 0x5A - - - FOC3C - Force Output Compare 3C - [5:5] - write-only - - FOC3B - Force Output Compare 3B - [6:6] - write-only - - FOC3A - Force Output Compare 3A - [7:7] - write-only - - - - TCNT3 - Timer/Counter3 Bytes - 0x5C - 16 - - - 0 - 65535 - - - - - TIFR3 - Timer/Counter3 Interrupt Flag register - 0x0 - read-write - - - TOV3 - Timer/Counter3 Overflow Flag - [0:0] - - - OCF3A - Output Compare Flag 3A - [1:1] - - - OCF3B - Output Compare Flag 3B - [2:2] - - - OCF3C - Output Compare Flag 3C - [3:3] - - - ICF3 - Input Capture Flag 3 - [5:5] - - - - - TIMSK3 - Timer/Counter3 Interrupt Mask Register - 0x39 - - - TOIE3 - Timer/Counter3 Overflow Interrupt Enable - [0:0] - - - OCIE3A - Timer/Counter3 Output Compare A Match Interrupt Enable - [1:1] - - - OCIE3B - Timer/Counter3 Output Compare B Match Interrupt Enable - [2:2] - - - OCIE3C - Timer/Counter3 Output Compare C Match Interrupt Enable - [3:3] - - - ICIE3 - Timer/Counter3 Input Capture Interrupt Enable - [5:5] - - - - - - - TC4 - Timer/Counter, 16-bit - 0x39 - - - ICR4 - Timer/Counter4 Input Capture Register Bytes - 0x6D - 16 - - - 0 - 65535 - - - - - OCR4A - Timer/Counter4 Output Compare Register A Bytes - 0x6F - 16 - - - 0 - 65535 - - - - - OCR4B - Timer/Counter4 Output Compare Register B Bytes - 0x71 - 16 - - - 0 - 65535 - - - - - OCR4C - Timer/Counter4 Output Compare Register B Bytes - 0x73 - 16 - - - 0 - 65535 - - - - - TCCR4A - Timer/Counter4 Control Register A - 0x67 - - - WGM4 - Waveform Generation Mode - [1:0] - - - 0 - 3 - - - - - COM4C - Compare Output Mode 4C, bits - [3:2] - - true - COM4Cread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM4B - Compare Output Mode 4B, bits - [5:4] - - true - - - - COM4A - Compare Output Mode 1A, bits - [7:6] - - true - - - - - - TCCR4B - Timer/Counter4 Control Register B - 0x68 - - - CS4 - Prescaler source of Timer/Counter 4 - [2:0] - - true - CS4read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM4 - Waveform Generation Mode - [4:3] - - - 0 - 3 - - - - - ICES4 - Input Capture 4 Edge Select - [6:6] - - - ICNC4 - Input Capture 4 Noise Canceler - [7:7] - - - - - TCCR4C - Timer/Counter 4 Control Register C - 0x69 - - - FOC4C - Force Output Compare 4C - [5:5] - write-only - - FOC4B - Force Output Compare 4B - [6:6] - write-only - - FOC4A - Force Output Compare 4A - [7:7] - write-only - - - - TCNT4 - Timer/Counter4 Bytes - 0x6B - 16 - - - 0 - 65535 - - - - - TIFR4 - Timer/Counter4 Interrupt Flag register - 0x0 - read-write - - TOV4 - Timer/Counter4 Overflow Flag - [0:0] - - - OCF4A - Output Compare Flag 4A - [1:1] - - - OCF4B - Output Compare Flag 4B - [2:2] - - - OCF4C - Output Compare Flag 4C - [3:3] - - - ICF4 - Input Capture Flag 4 - [5:5] - - - - - TIMSK4 - Timer/Counter4 Interrupt Mask Register - 0x39 - - - TOIE4 - Timer/Counter4 Overflow Interrupt Enable - [0:0] - - - OCIE4A - Timer/Counter4 Output Compare A Match Interrupt Enable - [1:1] - - - OCIE4B - Timer/Counter4 Output Compare B Match Interrupt Enable - [2:2] - - - OCIE4C - Timer/Counter4 Output Compare C Match Interrupt Enable - [3:3] - - - ICIE4 - Timer/Counter4 Input Capture Interrupt Enable - [5:5] - - - - - - - TC5 - Timer/Counter, 16-bit - 0x3A - - - ICR5 - Timer/Counter5 Input Capture Register Bytes - 0xEC - 16 - - - 0 - 65535 - - - - - OCR5A - Timer/Counter5 Output Compare Register A Bytes - 0xEE - 16 - - - 0 - 65535 - - - - - OCR5B - Timer/Counter5 Output Compare Register B Bytes - 0xF0 - 16 - - - 0 - 65535 - - - - - OCR5C - Timer/Counter5 Output Compare Register B Bytes - 0xF2 - 16 - - - 0 - 65535 - - - - - TCCR5A - Timer/Counter5 Control Register A - 0xE6 - - - WGM5 - Waveform Generation Mode - [1:0] - - - 0 - 3 - - - - - COM5C - Compare Output Mode 5C, bits - [3:2] - - true - COM5Cread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM5B - Compare Output Mode 5B, bits - [5:4] - - true - - - - COM5A - Compare Output Mode 1A, bits - [7:6] - - true - - - - - - TCCR5B - Timer/Counter5 Control Register B - 0xE7 - - - CS5 - Prescaler source of Timer/Counter 5 - [2:0] - - true - CS5read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM5 - Waveform Generation Mode - [4:3] - - - 0 - 3 - - - - - ICES5 - Input Capture 5 Edge Select - [6:6] - - - ICNC5 - Input Capture 5 Noise Canceler - [7:7] - - - - - TCCR5C - Timer/Counter 5 Control Register C - 0xE8 - - - FOC5C - Force Output Compare 5C - [5:5] - write-only - - FOC5B - Force Output Compare 5B - [6:6] - write-only - - FOC5A - Force Output Compare 5A - [7:7] - write-only - - - - TCNT5 - Timer/Counter5 Bytes - 0xEA - 16 - - - 0 - 65535 - - - - - TIFR5 - Timer/Counter5 Interrupt Flag register - 0x0 - read-write - - TOV5 - Timer/Counter5 Overflow Flag - [0:0] - - - OCF5A - Output Compare Flag 5A - [1:1] - - - OCF5B - Output Compare Flag 5B - [2:2] - - - OCF5C - Output Compare Flag 5C - [3:3] - - - ICF5 - Input Capture Flag 5 - [5:5] - - - - - TIMSK5 - Timer/Counter5 Interrupt Mask Register - 0x39 - - - TOIE5 - Timer/Counter5 Overflow Interrupt Enable - [0:0] - - - OCIE5A - Timer/Counter5 Output Compare A Match Interrupt Enable - [1:1] - - - OCIE5B - Timer/Counter5 Output Compare B Match Interrupt Enable - [2:2] - - - OCIE5C - Timer/Counter5 Output Compare C Match Interrupt Enable - [3:3] - - - ICIE5 - Timer/Counter5 Input Capture Interrupt Enable - [5:5] - - - - - - - TWI - Two Wire Serial Interface - 0xB8 - - - TWAMR - TWI (Slave) Address Mask Register - 0x5 - - - TWAM - TWI (Slave) Address Mask Bits - [7:1] - - - 0 - 127 - - - - - - - TWAR - TWI (Slave) Address register - 0x2 - - - TWGCE - TWI General Call Recognition Enable Bit - [0:0] - - - TWA - TWI (Slave) Address register Bits - [7:1] - - - 0 - 127 - - - - - - - TWBR - TWI Bit Rate register - 0x0 - - - 0 - 255 - - - - - TWCR - TWI Control Register - 0x4 - read-write - - - TWIE - TWI Interrupt Enable - [0:0] - - - TWEN - TWI Enable Bit - [2:2] - - - TWWC - TWI Write Collition Flag - [3:3] - read-only - - TWSTO - TWI Stop Condition Bit - [4:4] - - - TWSTA - TWI Start Condition Bit - [5:5] - - - TWEA - TWI Enable Acknowledge Bit - [6:6] - - - TWINT - TWI Interrupt Flag - [7:7] - - - - - TWDR - TWI Data register - 0x3 - - - 0 - 255 - - - - - TWSR - TWI Status Register - 0x1 - - - TWPS - TWI Prescaler - [1:0] - - true - - TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 - - - TWS - TWI Status - [7:3] - read-only - - 0 - 31 - - - - - - - - - USART0 - USART - 0xC0 - - - UBRR0 - USART Baud Rate Register Bytes - 0x4 - 16 - - - 0 - 65535 - - - - - UCSR0A - USART Control and Status Register A - 0x0 - read-write - - - MPCM0 - Multi-processor Communication Mode - [0:0] - - - U2X0 - Double the USART transmission speed - [1:1] - - - UPE0 - Parity Error - [2:2] - read-only - - DOR0 - Data overRun - [3:3] - read-only - - FE0 - Framing Error - [4:4] - read-only - - UDRE0 - USART Data Register Empty - [5:5] - read-only - - TXC0 - USART Transmit Complete - [6:6] - - - RXC0 - USART Receive Complete - [7:7] - read-only - - - - UCSR0B - USART Control and Status Register B - 0x1 - - - TXB80 - Transmit Data Bit 8 - [0:0] - - - RXB80 - Receive Data Bit 8 - [1:1] - read-only - - UCSZ02 - Character Size - [2:2] - - - TXEN0 - Transmitter Enable - [3:3] - - - RXEN0 - Receiver Enable - [4:4] - - - UDRIE0 - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE0 - TX Complete Interrupt Enable - [6:6] - - - RXCIE0 - RX Complete Interrupt Enable - [7:7] - - - - - UCSR0C - USART Control and Status Register C - 0x2 - - - UCPOL0 - Clock Polarity - [0:0] - UCPOL0read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 - - - UCSZ0 - Character Size - [2:1] - - - 0 - 3 - - - UCSZ0read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 - - - USBS0 - Stop Bit Select - [3:3] - - true - - USBS0read-writeSTOP11-bit0STOP22-bit1 - - - UPM0 - Parity Mode Bits - [5:4] - - true - - UPM0read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 - - - UMSEL0 - USART Mode Select - [7:6] - - true - - UMSEL0read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 - - - - - UDR0 - USART I/O Data Register - 0x6 - - - 0 - 255 - - - - - - - USART1 - USART - 0xC8 - - - UBRR1 - USART Baud Rate Register Bytes - 0x4 - 16 - - - 0 - 65535 - - - - - UCSR1A - USART Control and Status Register A - 0x0 - read-write - - - MPCM1 - Multi-processor Communication Mode - [0:0] - - - U2X1 - Double the USART transmission speed - [1:1] - - - UPE1 - Parity Error - [2:2] - read-only - - DOR1 - Data overRun - [3:3] - read-only - - FE1 - Framing Error - [4:4] - read-only - - UDRE1 - USART Data Register Empty - [5:5] - read-only - - TXC1 - USART Transmit Complete - [6:6] - - - RXC1 - USART Receive Complete - [7:7] - read-only - - - - UCSR1B - USART Control and Status Register B - 0x1 - - - TXB81 - Transmit Data Bit 8 - [0:0] - - - RXB81 - Receive Data Bit 8 - [1:1] - read-only - - UCSZ12 - Character Size - [2:2] - - - TXEN1 - Transmitter Enable - [3:3] - - - RXEN1 - Receiver Enable - [4:4] - - - UDRIE1 - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE1 - TX Complete Interrupt Enable - [6:6] - - - RXCIE1 - RX Complete Interrupt Enable - [7:7] - - - - - UCSR1C - USART Control and Status Register C - 0x2 - - - UCPOL1 - Clock Polarity - [0:0] - UCPOL1read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 - - - UCSZ1 - Character Size - [2:1] - - - 0 - 3 - - - UCSZ1read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 - - - USBS1 - Stop Bit Select - [3:3] - - true - - USBS1read-writeSTOP11-bit0STOP22-bit1 - - - UPM1 - Parity Mode Bits - [5:4] - - true - - UPM1read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 - - - UMSEL1 - USART Mode Select - [7:6] - - true - - UMSEL1read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 - - - - - UDR1 - USART I/O Data Register - 0x6 - - - 0 - 255 - - - - - - - USART2 - USART - 0xD0 - - - UBRR2 - USART Baud Rate Register Bytes - 0x4 - 16 - - - 0 - 65535 - - - - - UCSR2A - USART Control and Status Register A - 0x0 - read-write - - - MPCM2 - Multi-processor Communication Mode - [0:0] - - - U2X2 - Double the USART transmission speed - [1:1] - - - UPE2 - Parity Error - [2:2] - read-only - - DOR2 - Data overRun - [3:3] - read-only - - FE2 - Framing Error - [4:4] - read-only - - UDRE2 - USART Data Register Empty - [5:5] - read-only - - TXC2 - USART Transmit Complete - [6:6] - - - RXC2 - USART Receive Complete - [7:7] - read-only - - - - UCSR2B - USART Control and Status Register B - 0x1 - - - TXB82 - Transmit Data Bit 8 - [0:0] - - - RXB82 - Receive Data Bit 8 - [1:1] - read-only - - UCSZ22 - Character Size - [2:2] - - - TXEN2 - Transmitter Enable - [3:3] - - - RXEN2 - Receiver Enable - [4:4] - - - UDRIE2 - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE2 - TX Complete Interrupt Enable - [6:6] - - - RXCIE2 - RX Complete Interrupt Enable - [7:7] - - - - - UCSR2C - USART Control and Status Register C - 0x2 - - - UCPOL2 - Clock Polarity - [0:0] - UCPOL2read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 - - - UCSZ2 - Character Size - [2:1] - - - 0 - 3 - - - UCSZ2read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 - - - USBS2 - Stop Bit Select - [3:3] - - true - - USBS2read-writeSTOP11-bit0STOP22-bit1 - - - UPM2 - Parity Mode Bits - [5:4] - - true - - UPM2read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 - - - UMSEL2 - USART Mode Select - [7:6] - - true - - UMSEL2read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 - - - - - UDR2 - USART I/O Data Register - 0x6 - - - 0 - 255 - - - - - - - USART3 - USART - 0x130 - - - UBRR3 - USART Baud Rate Register Bytes - 0x4 - 16 - - - 0 - 65535 - - - - - UCSR3A - USART Control and Status Register A - 0x0 - read-write - - - MPCM3 - Multi-processor Communication Mode - [0:0] - - - U2X3 - Double the USART transmission speed - [1:1] - - - UPE3 - Parity Error - [2:2] - read-only - - DOR3 - Data overRun - [3:3] - read-only - - FE3 - Framing Error - [4:4] - read-only - - UDRE3 - USART Data Register Empty - [5:5] - read-only - - TXC3 - USART Transmit Complete - [6:6] - - - RXC3 - USART Receive Complete - [7:7] - read-only - - - - UCSR3B - USART Control and Status Register B - 0x1 - - - TXB83 - Transmit Data Bit 8 - [0:0] - - - RXB83 - Receive Data Bit 8 - [1:1] - read-only - - UCSZ32 - Character Size - [2:2] - - - TXEN3 - Transmitter Enable - [3:3] - - - RXEN3 - Receiver Enable - [4:4] - - - UDRIE3 - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE3 - TX Complete Interrupt Enable - [6:6] - - - RXCIE3 - RX Complete Interrupt Enable - [7:7] - - - - - UCSR3C - USART Control and Status Register C - 0x2 - - - UCPOL3 - Clock Polarity - [0:0] - UCPOL3read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 - - - UCSZ3 - Character Size - [2:1] - - - 0 - 3 - - - UCSZ3read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 - - - USBS3 - Stop Bit Select - [3:3] - - true - - USBS3read-writeSTOP11-bit0STOP22-bit1 - - - UPM3 - Parity Mode Bits - [5:4] - - true - - UPM3read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 - - - UMSEL3 - USART Mode Select - [7:6] - - true - - UMSEL3read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 - - - - - UDR3 - USART I/O Data Register - 0x6 - - - 0 - 255 - - - - - - - WDT - Watchdog Timer - 0x60 - - - WDTCSR - Watchdog Timer Control Register - 0x0 - read-write - - - WDE - Watch Dog Enable - [3:3] - - - WDCE - Watchdog Change Enable - [4:4] - - - WDIE - Watchdog Timeout Interrupt Enable - [6:6] - - - WDIF - Watchdog Timeout Interrupt Flag - [7:7] - - WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 - - WDPHWatchdog Timer Prescaler - High Bit[5:5] - - - - - - \ No newline at end of file diff --git a/misc/svd/atmega328p.svd b/misc/svd/atmega328p.svd deleted file mode 100644 index b169013..0000000 --- a/misc/svd/atmega328p.svd +++ /dev/null @@ -1,3040 +0,0 @@ - - - Atmel - ATmega328P - 8 - 8 - read-write - 0 - 0xff - - - AC - Analog Comparator - 0x50 - - - ACSR - Analog Comparator Control And Status Register - 0x0 - read-write - - - ACIS - Analog Comparator Interrupt Mode Select - [1:0] - - true - - ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 - - - ACIC - Analog Comparator Input Capture Enable - [2:2] - - - ACIE - Analog Comparator Interrupt Enable - [3:3] - - - ACI - Analog Comparator Interrupt Flag - [4:4] - - - ACO - Analog Compare Output - [5:5] - read-only - - ACBG - Analog Comparator Bandgap Select - [6:6] - - - ACD - Analog Comparator Disable - [7:7] - - - - - DIDR1 - Digital Input Disable Register 1 - 0x2F - - - AIN0D - AIN0 Digital Input Disable - [0:0] - - - AIN1D - AIN1 Digital Input Disable - [1:1] - - - - - - - ADC - Analog-to-Digital Converter - 0x78 - - - ADC - ADC Data Register Bytes - 0x0 - 16 - - - 0 - 65535 - - - - - ADCSRA - The ADC Control and Status register A - 0x2 - read-write - - - ADPS - ADC Prescaler Select Bits - [2:0] - - true - - ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 - - - ADIE - ADC Interrupt Enable - [3:3] - - - ADIF - ADC Interrupt Flag - [4:4] - - - ADATE - ADC Auto Trigger Enable - [5:5] - - - ADSC - ADC Start Conversion - [6:6] - - - ADEN - ADC Enable - [7:7] - - - - - ADCSRB - The ADC Control and Status register B - 0x3 - - - ADTS - ADC Auto Trigger Source bits - [2:0] - - true - - - - VAL_0x00 - Free Running mode - 0 - - - VAL_0x01 - Analog Comparator - 1 - - - VAL_0x02 - External Interrupt Request 0 - 2 - - - VAL_0x03 - Timer/Counter0 Compare Match A - 3 - - - VAL_0x04 - Timer/Counter0 Overflow - 4 - - - VAL_0x05 - Timer/Counter1 Compare Match B - 5 - - - VAL_0x06 - Timer/Counter1 Overflow - 6 - - - VAL_0x07 - Timer/Counter1 Capture Event - 7 - - - - - ACME - <TBD> - [6:6] - - - - - ADMUX - The ADC multiplexer Selection Register - 0x4 - - - MUX - Analog Channel Selection Bits - [3:0] - - true - - - - ADC0 - ADC Single Ended Input pin 0 - 0 - - - ADC1 - ADC Single Ended Input pin 1 - 1 - - - ADC2 - ADC Single Ended Input pin 2 - 2 - - - ADC3 - ADC Single Ended Input pin 3 - 3 - - - ADC4 - ADC Single Ended Input pin 4 - 4 - - - ADC5 - ADC Single Ended Input pin 5 - 5 - - - ADC6 - ADC Single Ended Input pin 6 - 6 - - - ADC7 - ADC Single Ended Input pin 7 - 7 - - - TEMPSENS - Temperature sensor - 8 - - - ADC_VBG - Internal Reference (VBG) - 14 - - - ADC_GND - 0V (GND) - 15 - - - - - ADLAR - Left Adjust Result - [5:5] - - - REFS - Reference Selection Bits - [7:6] - - true - - REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 - - - - - DIDR0 - Digital Input Disable Register - 0x6 - - - ADC0D - <TBD> - [0:0] - - - ADC1D - <TBD> - [1:1] - - - ADC2D - <TBD> - [2:2] - - - ADC3D - <TBD> - [3:3] - - - ADC4D - <TBD> - [4:4] - - - ADC5D - <TBD> - [5:5] - - - - - - - CPU - CPU Registers - 0x3E - - RESET - External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset - 0 - - - INT0 - External Interrupt Request 0 - 1 - - - INT1 - External Interrupt Request 1 - 2 - - - PCINT0 - Pin Change Interrupt Request 0 - 3 - - - PCINT1 - Pin Change Interrupt Request 1 - 4 - - - PCINT2 - Pin Change Interrupt Request 2 - 5 - - - WDT - Watchdog Time-out Interrupt - 6 - - - TIMER2_COMPA - Timer/Counter2 Compare Match A - 7 - - - TIMER2_COMPB - Timer/Counter2 Compare Match B - 8 - - - TIMER2_OVF - Timer/Counter2 Overflow - 9 - - - TIMER1_CAPT - Timer/Counter1 Capture Event - 10 - - - TIMER1_COMPA - Timer/Counter1 Compare Match A - 11 - - - TIMER1_COMPB - Timer/Counter1 Compare Match B - 12 - - - TIMER1_OVF - Timer/Counter1 Overflow - 13 - - - TIMER0_COMPA - TimerCounter0 Compare Match A - 14 - - - TIMER0_COMPB - TimerCounter0 Compare Match B - 15 - - - TIMER0_OVF - Timer/Couner0 Overflow - 16 - - - SPI_STC - SPI Serial Transfer Complete - 17 - - - USART_RX - USART Rx Complete - 18 - - - USART_UDRE - USART, Data Register Empty - 19 - - - USART_TX - USART Tx Complete - 20 - - - ADC - ADC Conversion Complete - 21 - - - EE_READY - EEPROM Ready - 22 - - - ANALOG_COMP - Analog Comparator - 23 - - - TWI - Two-wire Serial Interface - 24 - - - SPM_Ready - Store Program Memory Read - 25 - - - - CLKPR - Clock Prescale Register - 0x23 - read-only - - - CLKPS - Clock Prescaler Select Bits - [3:0] - - true - - - - VAL_0x00 - 1 - 0 - - - VAL_0x01 - 2 - 1 - - - VAL_0x02 - 4 - 2 - - - VAL_0x03 - 8 - 3 - - - VAL_0x04 - 16 - 4 - - - VAL_0x05 - 32 - 5 - - - VAL_0x06 - 64 - 6 - - - VAL_0x07 - 128 - 7 - - - VAL_0x08 - 256 - 8 - - - - - CLKPCE - Clock Prescaler Change Enable - [7:7] - - - - - GPIOR0 - General Purpose I/O Register 0 - 0x0 - - - 0 - 255 - - - - - GPIOR1 - General Purpose I/O Register 1 - 0xC - - - 0 - 255 - - - - - GPIOR2 - General Purpose I/O Register 2 - 0xD - - - 0 - 255 - - - - - MCUCR - MCU Control Register - 0x17 - - - IVCE - <TBD> - [0:0] - - - IVSEL - <TBD> - [1:1] - - - PUD - <TBD> - [4:4] - - - BODSE - BOD Sleep Enable - [5:5] - - - BODS - BOD Sleep - [6:6] - - - - - MCUSR - MCU Status Register - 0x16 - - - PORF - Power-on reset flag - [0:0] - - - EXTRF - External Reset Flag - [1:1] - - - BORF - Brown-out Reset Flag - [2:2] - - - WDRF - Watchdog Reset Flag - [3:3] - - - - - OSCCAL - Oscillator Calibration Value - 0x28 - read-only - - - OSCCAL - Oscillator Calibration - [7:0] - - - 0 - 255 - - - - - - - PRR - Power Reduction Register - 0x26 - read-write - - - PRADC - Power Reduction ADC - [0:0] - - - PRUSART0 - Power Reduction USART - [1:1] - - - PRSPI - Power Reduction Serial Peripheral Interface - [2:2] - - - PRTIM1 - Power Reduction Timer/Counter1 - [3:3] - - - PRTIM0 - Power Reduction Timer/Counter0 - [5:5] - - - PRTIM2 - Power Reduction Timer/Counter2 - [6:6] - - - PRTWI - Power Reduction TWI - [7:7] - - - - - SMCR - Sleep Mode Control Register - 0x15 - - - SE - Sleep Enable - [0:0] - - - SM - Sleep Mode Select Bits - [3:1] - - true - - - - IDLE - Idle - 0 - - - ADC - ADC Noise Reduction (If Available) - 1 - - - PDOWN - Power Down - 2 - - - PSAVE - Power Save - 3 - - - VAL_0x04 - Reserved - 4 - - - VAL_0x05 - Reserved - 5 - - - STDBY - Standby - 6 - - - ESTDBY - Extended Standby - 7 - - - - - - - SPMCSR - Store Program Memory Control and Status Register - 0x19 - - - SPMEN - Store Program Memory - [0:0] - - - PGERS - Page Erase - [1:1] - - - PGWRT - Page Write - [2:2] - - - BLBSET - Boot Lock Bit Set - [3:3] - - - RWWSRE - Read-While-Write section read enable - [4:4] - - - SIGRD - Signature Row Read - [5:5] - - - RWWSB - Read-While-Write Section Busy - [6:6] - - - SPMIE - SPM Interrupt Enable - [7:7] - - - - - - - EEPROM - EEPROM - 0x3F - - - EEAR - EEPROM Address Register Bytes - 0x2 - 16 - - - 0 - 65535 - - - - - EECR - EEPROM Control Register - 0x0 - - - EERE - EEPROM Read Enable - [0:0] - - - EEPE - EEPROM Write Enable - [1:1] - - - EEMPE - EEPROM Master Write Enable - [2:2] - - - EERIE - EEPROM Ready Interrupt Enable - [3:3] - - - EEPM - EEPROM Programming Mode Bits - [5:4] - - true - - - - VAL_0x00 - Erase and Write in one operation - 0 - - - VAL_0x01 - Erase Only - 1 - - - VAL_0x02 - Write Only - 2 - - - - - - - EEDR - EEPROM Data Register - 0x1 - - - 0 - 255 - - - - - - - EXINT - External Interrupts - 0x3B - - - EICRA - External Interrupt Control Register - 0x2E - - - ISC0 - External Interrupt Sense Control 0 Bits - [1:0] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC1 - External Interrupt Sense Control 1 Bits - [3:2] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - - - EIFR - External Interrupt Flag Register - 0x1 - read-only - - - INTF - External Interrupt Flags - [1:0] - - - 0 - 3 - - - - - - - EIMSK - External Interrupt Mask Register - 0x2 - - INT0External Interrupt Request Enable01INT1External Interrupt Request Enable11 - - - PCICR - Pin Change Interrupt Control Register - 0x2D - - - PCIE - Pin Change Interrupt Enables - [2:0] - - - 0 - 7 - - - - - - - PCIFR - Pin Change Interrupt Flag Register - 0x0 - read-only - - - PCIF - Pin Change Interrupt Flags - [2:0] - - - 0 - 7 - - - - - - - PCMSK0 - Pin Change Mask Register 0 - 0x30 - - - PCINT - Pin Change Enable Masks - [7:0] - - - 0 - 255 - - - - - - - PCMSK1 - Pin Change Mask Register 1 - 0x31 - - - PCINT - Pin Change Enable Masks - [6:0] - - - 0 - 127 - - - - - - - PCMSK2 - Pin Change Mask Register 2 - 0x32 - - - PCINT - Pin Change Enable Masks - [7:0] - - - 0 - 255 - - - - - - - - - FUSE - Fuses - 0x0 - - - EXTENDED - <TBD> - 0x2 - - - BODLEVEL - Brown-out Detector trigger level - [2:0] - - true - - - - 4V3 - Brown-out detection at VCC=4.3 V - 4 - - - 2V7 - Brown-out detection at VCC=2.7 V - 5 - - - 1V8 - Brown-out detection at VCC=1.8 V - 6 - - - DISABLED - Brown-out detection disabled - 7 - - - - - - - HIGH - <TBD> - 0x1 - - - BOOTRST - Boot Reset vector Enabled - [0:0] - - - BOOTSZ - Select boot size - [2:1] - - true - - - - 2048W_3800 - Boot Flash size=2048 words start address=$3800 - 0 - - - 1024W_3C00 - Boot Flash size=1024 words start address=$3C00 - 1 - - - 512W_3E00 - Boot Flash size=512 words start address=$3E00 - 2 - - - 256W_3F00 - Boot Flash size=256 words start address=$3F00 - 3 - - - - - EESAVE - Preserve EEPROM through the Chip Erase cycle - [3:3] - - - WDTON - Watch-dog Timer always on - [4:4] - - - SPIEN - Serial program downloading (SPI) enabled - [5:5] - - - DWEN - Debug Wire enable - [6:6] - - - RSTDISBL - Reset Disabled (Enable PC6 as i/o pin) - [7:7] - - - - - LOW - <TBD> - 0x0 - - - SUT_CKSEL - Select Clock Source - [5:0] - - true - - - - EXTCLK_6CK_14CK_0MS - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 0 - - - INTRCOSC_8MHZ_6CK_14CK_0MS - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 2 - - - INTRCOSC_128KHZ_6CK_14CK_0MS - Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 3 - - - EXTLOFXTAL_1KCK_14CK_0MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms - 4 - - - EXTLOFXTAL_32KCK_14CK_0MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms - 5 - - - EXTFSXTAL_258CK_14CK_4MS1 - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 6 - - - EXTFSXTAL_1KCK_14CK_65MS - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 7 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 8 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 9 - - - EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 10 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 11 - - - EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 12 - - - EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 13 - - - EXTXOSC_8MHZ_XX_258CK_14CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 14 - - - EXTXOSC_8MHZ_XX_1KCK_14CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 15 - - - EXTCLK_6CK_14CK_4MS1 - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - 16 - - - INTRCOSC_8MHZ_6CK_14CK_4MS1 - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - 18 - - - INTRCOSC_128KHZ_6CK_14CK_4MS1 - Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - 19 - - - EXTLOFXTAL_1KCK_14CK_4MS1 - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms - 20 - - - EXTLOFXTAL_32KCK_14CK_4MS1 - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms - 21 - - - EXTFSXTAL_258CK_14CK_65MS - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 22 - - - EXTFSXTAL_16KCK_14CK_0MS - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 23 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 24 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 25 - - - EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 26 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 27 - - - EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 28 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 29 - - - EXTXOSC_8MHZ_XX_258CK_14CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 30 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 31 - - - EXTCLK_6CK_14CK_65MS - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms - 32 - - - INTRCOSC_8MHZ_6CK_14CK_65MS - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms - 34 - - - INTRCOSC_128KHZ_6CK_14CK_65MS - Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms - 35 - - - EXTLOFXTAL_1KCK_14CK_65MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms - 36 - - - EXTLOFXTAL_32KCK_14CK_65MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms - 37 - - - EXTFSXTAL_1KCK_14CK_0MS - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 38 - - - EXTFSXTAL_16KCK_14CK_4MS1 - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 39 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 40 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 41 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 42 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 43 - - - EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 44 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 45 - - - EXTXOSC_8MHZ_XX_1KCK_14CK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 46 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 47 - - - EXTFSXTAL_1KCK_14CK_4MS1 - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 54 - - - EXTFSXTAL_16KCK_14CK_65MS - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 55 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 56 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 57 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 58 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 59 - - - EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 60 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 61 - - - EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 62 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 63 - - - - - CKOUT - Clock output on PORTB0 - [6:6] - - - CKDIV8 - Divide clock by 8 internally - [7:7] - - - - - - - LOCKBIT - Lockbits - 0x0 - - - LOCKBIT - <TBD> - 0x0 - - - LB - Memory Lock - [1:0] - - true - - - - PROG_VER_DISABLED - Further programming and verification disabled - 0 - - - PROG_DISABLED - Further programming disabled - 2 - - - NO_LOCK - No memory lock features enabled - 3 - - - - - BLB0 - Boot Loader Protection Mode - [3:2] - - true - - - - LPM_SPM_DISABLE - LPM and SPM prohibited in Application Section - 0 - - - LPM_DISABLE - LPM prohibited in Application Section - 1 - - - SPM_DISABLE - SPM prohibited in Application Section - 2 - - - NO_LOCK - No lock on SPM and LPM in Application Section - 3 - - - - - BLB1 - Boot Loader Protection Mode - [5:4] - - true - - - - LPM_SPM_DISABLE - LPM and SPM prohibited in Boot Section - 0 - - - LPM_DISABLE - LPM prohibited in Boot Section - 1 - - - SPM_DISABLE - SPM prohibited in Boot Section - 2 - - - NO_LOCK - No lock on SPM and LPM in Boot Section - 3 - - - - - - - - - PORTB - I/O Port - 0x23 - - - DDRB - Port B Data Direction Register - 0x1 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PINB - Port B Input Pins - 0x0 - read-write - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PORTB - Port B Data Register - 0x2 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - - - PORTC - I/O Port - 0x26 - - - DDRC - Port C Data Direction Register - 0x1 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - - - PINC - Port C Input Pins - 0x0 - read-write - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - - - PORTC - Port C Data Register - 0x2 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - - - - - PORTD - I/O Port - 0x29 - - - DDRD - Port D Data Direction Register - 0x1 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PIND - Port D Input Pins - 0x0 - read-write - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PORTD - Port D Data Register - 0x2 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - - - SPI - Serial Peripheral Interface - 0x4C - - - SPCR - SPI Control Register - 0x0 - - - SPR - SPI Clock Rate Selects - [1:0] - - true - - SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 - - - CPHA - Clock Phase - [2:2] - - - CPOL - Clock polarity - [3:3] - - - MSTR - Master/Slave Select - [4:4] - - - DORD - Data Order - [5:5] - - - SPE - SPI Enable - [6:6] - - - SPIE - SPI Interrupt Enable - [7:7] - - - - - SPDR - SPI Data Register - 0x2 - - - 0 - 255 - - - - - SPSR - SPI Status Register - 0x1 - read-write - - - SPI2X - Double SPI Speed Bit - [0:0] - read-write - - WCOL - Write Collision Flag - [6:6] - read-only - - SPIF - SPI Interrupt Flag - [7:7] - read-only - - - - - - TC0 - Timer/Counter, 8-bit - 0x35 - - - GTCCR - General Timer/Counter Control Register - 0xE - - - PSRSYNC - Prescaler Reset Timer/Counter1 and Timer/Counter0 - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - OCR0A - Timer/Counter0 Output Compare Register - 0x12 - - - 0 - 255 - - - - - OCR0B - Timer/Counter0 Output Compare Register - 0x13 - - - 0 - 255 - - - - - TCCR0A - Timer/Counter Control Register A - 0xF - - - WGM0 - Waveform Generation Mode - [1:0] - - true - WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 - - - COM0B - Compare Output B Mode - [5:4] - - true - COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 - - - COM0A - Compare Output A Mode - [7:6] - - true - - - - - - TCCR0B - Timer/Counter Control Register B - 0x10 - - - CS0 - Clock Select - [2:0] - - true - - CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM02 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) - [3:3] - - - FOC0B - Force Output Compare B - [6:6] - write-only - - FOC0A - Force Output Compare A - [7:7] - write-only - - - - TCNT0 - Timer/Counter0 - 0x11 - - - 0 - 255 - - - - - TIFR0 - Timer/Counter0 Interrupt Flag register - 0x0 - read-write - - - TOV0 - Timer/Counter0 Overflow Flag - [0:0] - - - OCF0A - Timer/Counter0 Output Compare Flag 0A - [1:1] - - - OCF0B - Timer/Counter0 Output Compare Flag 0B - [2:2] - - - - - TIMSK0 - Timer/Counter0 Interrupt Mask Register - 0x39 - - - TOIE0 - Timer/Counter0 Overflow Interrupt Enable - [0:0] - - - OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable - [2:2] - - - - - - - TC1 - Timer/Counter, 16-bit - 0x36 - - - GTCCR - General Timer/Counter Control Register - 0xD - - - PSRSYNC - Prescaler Reset Timer/Counter1 and Timer/Counter0 - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - ICR1 - Timer/Counter1 Input Capture Register Bytes - 0x50 - 16 - - - 0 - 65535 - - - - - OCR1A - Timer/Counter1 Output Compare Register Bytes - 0x52 - 16 - - - 0 - 65535 - - - - - OCR1B - Timer/Counter1 Output Compare Register Bytes - 0x54 - 16 - - - 0 - 65535 - - - - - TCCR1A - Timer/Counter1 Control Register A - 0x4A - - - WGM1 - Waveform Generation Mode - [1:0] - - - 0 - 3 - - - - - COM1B - Compare Output Mode 1B, bits - [5:4] - - true - COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM1A - Compare Output Mode 1A, bits - [7:6] - - true - - - - - - TCCR1B - Timer/Counter1 Control Register B - 0x4B - - - CS1 - Prescaler source of Timer/Counter 1 - [2:0] - - true - CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM1 - Waveform Generation Mode - [4:3] - - - 0 - 3 - - - - - ICES1 - Input Capture 1 Edge Select - [6:6] - - - ICNC1 - Input Capture 1 Noise Canceler - [7:7] - - - - - TCCR1C - Timer/Counter1 Control Register C - 0x4C - - - FOC1B - <TBD> - [6:6] - write-only - - FOC1A - <TBD> - [7:7] - write-only - - - - TCNT1 - Timer/Counter1 Bytes - 0x4E - 16 - - - 0 - 65535 - - - - - TIFR1 - Timer/Counter Interrupt Flag register - 0x0 - read-write - - - TOV1 - Timer/Counter1 Overflow Flag - [0:0] - - - OCF1A - Output Compare Flag 1A - [1:1] - - - OCF1B - Output Compare Flag 1B - [2:2] - - - ICF1 - Input Capture Flag 1 - [5:5] - - - - - TIMSK1 - Timer/Counter Interrupt Mask Register - 0x39 - - - TOIE1 - Timer/Counter1 Overflow Interrupt Enable - [0:0] - - - OCIE1A - Timer/Counter1 Output CompareA Match Interrupt Enable - [1:1] - - - OCIE1B - Timer/Counter1 Output CompareB Match Interrupt Enable - [2:2] - - - ICIE1 - Timer/Counter1 Input Capture Interrupt Enable - [5:5] - - - - - - - TC2 - Timer/Counter, 8-bit Async - 0x37 - - - ASSR - Asynchronous Status Register - 0x7F - - - TCR2BUB - Timer/Counter Control Register2 Update Busy - [0:0] - - - TCR2AUB - Timer/Counter Control Register2 Update Busy - [1:1] - - - OCR2BUB - Output Compare Register 2 Update Busy - [2:2] - - - OCR2AUB - Output Compare Register2 Update Busy - [3:3] - - - TCN2UB - Timer/Counter2 Update Busy - [4:4] - - - AS2 - Asynchronous Timer/Counter2 - [5:5] - - - EXCLK - Enable External Clock Input - [6:6] - - - - - GTCCR - General Timer Counter Control register - 0xC - - - PSRASY - Prescaler Reset Timer/Counter2 - [1:1] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - OCR2A - Timer/Counter2 Output Compare Register A - 0x7C - - - 0 - 255 - - - - - OCR2B - Timer/Counter2 Output Compare Register B - 0x7D - - - 0 - 255 - - - - - TCCR2A - Timer/Counter2 Control Register A - 0x79 - - - WGM2 - Waveform Genration Mode - [1:0] - - true - WGM2read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 - - - COM2B - Compare Output B Mode - [5:4] - - true - COM2Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 - - - COM2A - Compare Output A Mode - [7:6] - - true - - - - - - TCCR2B - Timer/Counter2 Control Register B - 0x7A - - - CS2 - Clock Select bits - [2:0] - - true - - CS2read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_32Running, CLK/323PRESCALE_64Running, CLK/644PRESCALE_128Running, CLK/1285PRESCALE_256Running, CLK/2566PRESCALE_1024Running, CLK/10247 - - - WGM22 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) - [3:3] - - - FOC2B - Force Output Compare B - [6:6] - write-only - - FOC2A - Force Output Compare A - [7:7] - write-only - - - - TCNT2 - Timer/Counter2 - 0x7B - - - 0 - 255 - - - - - TIFR2 - Timer/Counter Interrupt Flag Register - 0x0 - read-write - - - TOV2 - Timer/Counter2 Overflow Flag - [0:0] - - - OCF2A - Output Compare Flag 2A - [1:1] - - - OCF2B - Output Compare Flag 2B - [2:2] - - - - - TIMSK2 - Timer/Counter Interrupt Mask register - 0x39 - - - TOIE2 - Timer/Counter2 Overflow Interrupt Enable - [0:0] - - - OCIE2A - Timer/Counter2 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE2B - Timer/Counter2 Output Compare Match B Interrupt Enable - [2:2] - - - - - - - TWI - Two Wire Serial Interface - 0xB8 - - - TWAMR - TWI (Slave) Address Mask Register - 0x5 - - - TWAM - TWI (Slave) Address Mask Bits - [7:1] - - - 0 - 127 - - - - - - - TWAR - TWI (Slave) Address register - 0x2 - - - TWGCE - TWI General Call Recognition Enable Bit - [0:0] - - - TWA - TWI (Slave) Address register Bits - [7:1] - - - 0 - 127 - - - - - - - TWBR - TWI Bit Rate register - 0x0 - - - 0 - 255 - - - - - TWCR - TWI Control Register - 0x4 - read-write - - - TWIE - TWI Interrupt Enable - [0:0] - - - TWEN - TWI Enable Bit - [2:2] - - - TWWC - TWI Write Collition Flag - [3:3] - read-only - - TWSTO - TWI Stop Condition Bit - [4:4] - - - TWSTA - TWI Start Condition Bit - [5:5] - - - TWEA - TWI Enable Acknowledge Bit - [6:6] - - - TWINT - TWI Interrupt Flag - [7:7] - - - - - TWDR - TWI Data register - 0x3 - - - 0 - 255 - - - - - TWSR - TWI Status Register - 0x1 - - - TWPS - TWI Prescaler - [1:0] - - true - - TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 - - - TWS - TWI Status - [7:3] - read-only - - 0 - 31 - - - - - - - - - USART0 - USART - 0xC0 - - - UBRR0 - USART Baud Rate Register Bytes - 0x4 - 16 - - - 0 - 65535 - - - - - UCSR0A - USART Control and Status Register A - 0x0 - read-write - - - MPCM0 - Multi-processor Communication Mode - [0:0] - - - U2X0 - Double the USART transmission speed - [1:1] - - - UPE0 - Parity Error - [2:2] - read-only - - DOR0 - Data overRun - [3:3] - read-only - - FE0 - Framing Error - [4:4] - read-only - - UDRE0 - USART Data Register Empty - [5:5] - read-only - - TXC0 - USART Transmit Complete - [6:6] - - - RXC0 - USART Receive Complete - [7:7] - read-only - - - - UCSR0B - USART Control and Status Register B - 0x1 - - - TXB80 - Transmit Data Bit 8 - [0:0] - - - RXB80 - Receive Data Bit 8 - [1:1] - read-only - - UCSZ02 - Character Size - [2:2] - - - TXEN0 - Transmitter Enable - [3:3] - - - RXEN0 - Receiver Enable - [4:4] - - - UDRIE0 - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE0 - TX Complete Interrupt Enable - [6:6] - - - RXCIE0 - RX Complete Interrupt Enable - [7:7] - - - - - UCSR0C - USART Control and Status Register C - 0x2 - - - UCPOL0 - Clock Polarity - [0:0] - UCPOL0read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 - - - UCSZ0 - Character Size - [2:1] - - - 0 - 3 - - - UCSZ0read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 - - - USBS0 - Stop Bit Select - [3:3] - - true - - USBS0read-writeSTOP11-bit0STOP22-bit1 - - - UPM0 - Parity Mode Bits - [5:4] - - true - - UPM0read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 - - - UMSEL0 - USART Mode Select - [7:6] - - true - - UMSEL0read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 - - - - - UDR0 - USART I/O Data Register - 0x6 - - - 0 - 255 - - - - - - - WDT - Watchdog Timer - 0x60 - - - WDTCSR - Watchdog Timer Control Register - 0x0 - read-write - - - WDE - Watch Dog Enable - [3:3] - - - WDCE - Watchdog Change Enable - [4:4] - - - WDIE - Watchdog Timeout Interrupt Enable - [6:6] - - - WDIF - Watchdog Timeout Interrupt Flag - [7:7] - - WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 - - WDPHWatchdog Timer Prescaler - High Bit[5:5] - - - - - - \ No newline at end of file diff --git a/misc/svd/atmega328pb.svd b/misc/svd/atmega328pb.svd deleted file mode 100644 index 4d665ad..0000000 --- a/misc/svd/atmega328pb.svd +++ /dev/null @@ -1,4127 +0,0 @@ - - Atmel - ATmega328PB - 8 - 8 - read-write - 0 - 0xff - - - AC - <TBD> - 0x4F - - - ACSR - Analog Comparator Control And Status Register - 0x1 - read-write - - - ACIS - Analog Comparator Interrupt Mode Select - [1:0] - - true - - ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 - - - ACIC - Analog Comparator Input Capture Enable - [2:2] - - - ACIE - Analog Comparator Interrupt Enable - [3:3] - - - ACI - Analog Comparator Interrupt Flag - [4:4] - - - ACO - Analog Compare Output - [5:5] - read-only - - ACBG - Analog Comparator Bandgap Select - [6:6] - - - ACD - Analog Comparator Disable - [7:7] - - - - - ACSRA - Analog Comparator Control And Status Register-A - 0x1 - read-only - - - 0 - 255 - - - - - ACSRB - Analog Comparator Control And Status Register-B - 0x0 - - - ACOE - Analog Comparator Output Enable - [0:0] - - - - - DIDR1 - Digital Input Disable Register 1 - 0x30 - - - AIN0D - AIN0 Digital Input Disable - [0:0] - - - AIN1D - AIN1 Digital Input Disable - [1:1] - - - - - - - ADC - Analog-to-Digital Converter - 0x78 - - - ADC - ADC Data Register Bytes - 0x0 - 16 - - - 0 - 65535 - - - - - ADCSRA - The ADC Control and Status register A - 0x2 - read-write - - - ADPS - ADC Prescaler Select Bits - [2:0] - - true - - ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 - - - ADIE - ADC Interrupt Enable - [3:3] - - - ADIF - ADC Interrupt Flag - [4:4] - - - ADATE - ADC Auto Trigger Enable - [5:5] - - - ADSC - ADC Start Conversion - [6:6] - - - ADEN - ADC Enable - [7:7] - - - - - ADCSRB - The ADC Control and Status register B - 0x3 - - - ADTS - ADC Auto Trigger Source bits - [2:0] - - true - - - - VAL_0x00 - Free Running mode - 0 - - - VAL_0x01 - Analog Comparator - 1 - - - VAL_0x02 - External Interrupt Request 0 - 2 - - - VAL_0x03 - Timer/Counter0 Compare Match A - 3 - - - VAL_0x04 - Timer/Counter0 Overflow - 4 - - - VAL_0x05 - Timer/Counter1 Compare Match B - 5 - - - VAL_0x06 - Timer/Counter1 Overflow - 6 - - - VAL_0x07 - Timer/Counter1 Capture Event - 7 - - - - - ACME - Analog Comparator Multiplexer Enable - [6:6] - - - - - ADMUX - The ADC multiplexer Selection Register - 0x4 - - - MUX - Analog Channel Selection Bits - [3:0] - - true - - - - ADC0 - ADC Single Ended Input pin 0 - 0 - - - ADC1 - ADC Single Ended Input pin 1 - 1 - - - ADC2 - ADC Single Ended Input pin 2 - 2 - - - ADC3 - ADC Single Ended Input pin 3 - 3 - - - ADC4 - ADC Single Ended Input pin 4 - 4 - - - ADC5 - ADC Single Ended Input pin 5 - 5 - - - ADC6 - ADC Single Ended Input pin 6 - 6 - - - ADC7 - ADC Single Ended Input pin 7 - 7 - - - TEMPSENS - Temperature sensor - 8 - - - ADC_VBG - Internal Reference (VBG) - 14 - - - ADC_GND - 0V (GND) - 15 - - - - - ADLAR - Left Adjust Result - [5:5] - - - REFS - Reference Selection Bits - [7:6] - - true - - REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 - - - - - DIDR0 - Digital Input Disable Register - 0x6 - - - ADC0D - ADC Digital Input Disable - [0:0] - - - ADC1D - ADC Digital Input Disable - [1:1] - - - ADC2D - ADC Digital Input Disable - [2:2] - - - ADC3D - ADC Digital Input Disable - [3:3] - - - ADC4D - ADC Digital Input Disable - [4:4] - - - ADC5D - ADC Digital Input Disable - [5:5] - - - ADC6D - ADC Digital Input Disable - [6:6] - - - ADC7D - ADC Digital Input Disable - [7:7] - - - - - - - CFD - <TBD> - 0x62 - - - XFDCSR - XOSC Failure Detection Control and Status Register - 0x0 - - - XFDIE - Failure Detection Interrupt Enable - [0:0] - - - XFDIF - Failure Detection Interrupt Flag - [1:1] - - - - - - - CPU - <TBD> - 0x3E - - RESET - External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset - 0 - - - INT0 - External Interrupt Request 0 - 1 - - - INT1 - External Interrupt Request 1 - 2 - - - PCINT0 - Pin Change Interrupt Request 0 - 3 - - - PCINT1 - Pin Change Interrupt Request 1 - 4 - - - PCINT2 - Pin Change Interrupt Request 2 - 5 - - - WDT - Watchdog Time-out Interrupt - 6 - - - TIMER2_COMPA - Timer/Counter2 Compare Match A - 7 - - - TIMER2_COMPB - Timer/Counter2 Compare Match B - 8 - - - TIMER2_OVF - Timer/Counter2 Overflow - 9 - - - TIMER1_CAPT - Timer/Counter1 Capture Event - 10 - - - TIMER1_COMPA - Timer/Counter1 Compare Match A - 11 - - - TIMER1_COMPB - Timer/Counter1 Compare Match B - 12 - - - TIMER1_OVF - Timer/Counter1 Overflow - 13 - - - TIMER0_COMPA - TimerCounter0 Compare Match A - 14 - - - TIMER0_COMPB - TimerCounter0 Compare Match B - 15 - - - TIMER0_OVF - Timer/Couner0 Overflow - 16 - - - SPI0_STC - SPI Serial Transfer Complete - 17 - - - USART0_RX - USART0 Rx Complete - 18 - - - USART0_UDRE - USART0, Data Register Empty - 19 - - - USART0_TX - USART0 Tx Complete - 20 - - - ADC - ADC Conversion Complete - 21 - - - EE_READY - EEPROM Ready - 22 - - - ANALOG_COMP - Analog Comparator - 23 - - - TWI0 - Two-wire Serial Interface - 24 - - - SPM_Ready - Store Program Memory Read - 25 - - - USART0_START - USART0 Start frame detection - 26 - - - PCINT3 - Pin Change Interrupt Request 3 - 27 - - - USART1_RX - USART1 Rx Complete - 28 - - - USART1_UDRE - USART1, Data Register Empty - 29 - - - USART1_TX - USART1 Tx Complete - 30 - - - USART1_START - USART1 Start frame detection - 31 - - - TIMER3_CAPT - Timer/Counter3 Capture Event - 32 - - - TIMER3_COMPA - Timer/Counter3 Compare Match A - 33 - - - TIMER3_COMPB - Timer/Counter3 Compare Match B - 34 - - - TIMER3_OVF - Timer/Counter3 Overflow - 35 - - - CFD - Clock failure detection interrupt - 36 - - - PTC_EOC - PTC End of conversion - 37 - - - PTC_WCOMP - PTC Window comparator mode - 38 - - - SPI1_STC - SPI1 Serial Transfer Complete - 39 - - - TWI1 - TWI Transfer Complete - 40 - - - TIMER4_CAPT - Timer/Counter4 Capture Event - 41 - - - TIMER4_COMPA - Timer/Counter4 Compare Match A - 42 - - - TIMER4_COMPB - Timer/Counter4 Compare Match B - 43 - - - TIMER4_OVF - Timer/Counter4 Overflow - 44 - - - - CLKPR - Clock Prescale Register - 0x23 - read-only - - - CLKPS - Clock Prescaler Select Bits - [3:0] - - true - - - - VAL_0x00 - 1 - 0 - - - VAL_0x01 - 2 - 1 - - - VAL_0x02 - 4 - 2 - - - VAL_0x03 - 8 - 3 - - - VAL_0x04 - 16 - 4 - - - VAL_0x05 - 32 - 5 - - - VAL_0x06 - 64 - 6 - - - VAL_0x07 - 128 - 7 - - - VAL_0x08 - 256 - 8 - - - - - CLKPCE - Clock Prescaler Change Enable - [7:7] - - - - - GPIOR0 - General Purpose I/O Register 0 - 0x0 - - - 0 - 255 - - - - - GPIOR1 - General Purpose I/O Register 1 - 0xC - - - 0 - 255 - - - - - GPIOR2 - General Purpose I/O Register 2 - 0xD - - - 0 - 255 - - - - - MCUCR - MCU Control Register - 0x17 - - - IVCE - <TBD> - [0:0] - - - IVSEL - <TBD> - [1:1] - - - PUD - <TBD> - [4:4] - - - BODSE - BOD Sleep Enable - [5:5] - - - BODS - BOD Sleep - [6:6] - - - - - MCUSR - MCU Status Register - 0x16 - - - PORF - Power-on reset flag - [0:0] - - - EXTRF - External Reset Flag - [1:1] - - - BORF - Brown-out Reset Flag - [2:2] - - - WDRF - Watchdog Reset Flag - [3:3] - - - - - OSCCAL - Oscillator Calibration Value - 0x28 - read-only - - - OSCCAL - Oscillator Calibration - [7:0] - - - 0 - 255 - - - - - - - PRR0 - Power Reduction Register 0 - 0x26 - read-write - - - PRADC - Power Reduction ADC - [0:0] - - - PRUSART0 - Power Reduction USART0 - [1:1] - - - PRSPI0 - Power Reduction Serial Peripheral Interface 1 - [2:2] - - - PRTIM1 - Power Reduction Timer/Counter1 - [3:3] - - - PRUSART1 - Power Reduction USART1 - [4:4] - - - PRTIM0 - Power Reduction Timer/Counter0 - [5:5] - - - PRTIM2 - Power Reduction Timer/Counter2 - [6:6] - - - PRTWI0 - Power Reduction TWI0 - [7:7] - - - - - PRR1 - Power Reduction Register 1 - 0x27 - read-write - - - PRTIM3 - Power Reduction Timer/Counter3 - [0:0] - - - PRSPI1 - Power Reduction Serial Peripheral Interface 1 - [2:2] - - - PRTIM4 - Power Reduction Timer/Counter4 - [3:3] - - - PRPTC - Power Reduction Peripheral Touch Controller - [4:4] - - - PRTWI1 - Power Reduction TWI1 - [5:5] - - - - - SMCR - Sleep Mode Control Register - 0x15 - - - SE - Sleep Enable - [0:0] - - - SM - Sleep Mode Select Bits - [3:1] - - true - - - - IDLE - Idle - 0 - - - ADC - ADC Noise Reduction (If Available) - 1 - - - PDOWN - Power Down - 2 - - - PSAVE - Power Save - 3 - - - VAL_0x04 - Reserved - 4 - - - VAL_0x05 - Reserved - 5 - - - STDBY - Standby - 6 - - - ESTDBY - Extended Standby - 7 - - - - - - - SPMCSR - Store Program Memory Control and Status Register - 0x19 - - - SPMEN - Store Program Memory - [0:0] - - - PGERS - Page Erase - [1:1] - - - PGWRT - Page Write - [2:2] - - - BLBSET - Boot Lock Bit Set - [3:3] - - - RWWSRE - Read-While-Write section read enable - [4:4] - - - SIGRD - Signature Row Read - [5:5] - - - RWWSB - Read-While-Write Section Busy - [6:6] - - - SPMIE - SPM Interrupt Enable - [7:7] - - - - - - - EEPROM - <TBD> - 0x3F - - - EEAR - EEPROM Address Register Bytes - 0x2 - 16 - - - 0 - 65535 - - - - - EECR - EEPROM Control Register - 0x0 - - - EERE - EEPROM Read Enable - [0:0] - - - EEPE - EEPROM Write Enable - [1:1] - - - EEMPE - EEPROM Master Write Enable - [2:2] - - - EERIE - EEPROM Ready Interrupt Enable - [3:3] - - - EEPM - EEPROM Programming Mode Bits - [5:4] - - true - - - - VAL_0x00 - Erase and Write in one operation - 0 - - - VAL_0x01 - Erase Only - 1 - - - VAL_0x02 - Write Only - 2 - - - - - - - EEDR - EEPROM Data Register - 0x1 - - - 0 - 255 - - - - - - - EXINT - <TBD> - 0x3B - - - EICRA - External Interrupt Control Register - 0x2E - - - ISC0 - External Interrupt Sense Control 0 Bits - [1:0] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC1 - External Interrupt Sense Control 1 Bits - [3:2] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - - - EIFR - External Interrupt Flag Register - 0x1 - read-only - - - INTF - External Interrupt Flags - [1:0] - - - 0 - 3 - - - - - - - EIMSK - External Interrupt Mask Register - 0x2 - - INT0External Interrupt Request Enable01INT1External Interrupt Request Enable11 - - - PCICR - Pin Change Interrupt Control Register - 0x2D - - - PCIE - Pin Change Interrupt Enables - [3:0] - - - 0 - 15 - - - - - - - PCIFR - Pin Change Interrupt Flag Register - 0x0 - read-only - - - PCIF - Pin Change Interrupt Flags - [3:0] - - - 0 - 15 - - - - - - - PCMSK0 - Pin Change Mask Register 0 - 0x30 - - - PCINT - Pin Change Enable Masks - [7:0] - - - 0 - 255 - - - - - - - PCMSK1 - Pin Change Mask Register 1 - 0x31 - - - PCINT - Pin Change Enable Masks - [6:0] - - - 0 - 127 - - - - - - - PCMSK2 - Pin Change Mask Register 2 - 0x32 - - - PCINT - Pin Change Enable Masks - [7:0] - - - 0 - 255 - - - - - - - PCMSK3 - Pin Change Mask Register 3 - 0x38 - - - PCINT - Pin Change Enable Masks - [3:0] - - - 0 - 15 - - - - - - - - - FUSE - Fuses - 0x0 - - - EXTENDED - <TBD> - 0x2 - - - BODLEVEL - Brown-out Detector trigger level - [2:0] - - true - - - - 4V3 - Brown-out detection at VCC=4.3 V - 4 - - - 2V7 - Brown-out detection at VCC=2.7 V - 5 - - - 1V8 - Brown-out detection at VCC=1.8 V - 6 - - - DISABLED - Brown-out detection disabled - 7 - - - - - CFD - Clock Failure Detection - [3:3] - - true - - - - CFD_DISABLED - Disabled - 0 - - - CFD_ENABLED - Enabled - 1 - - - - - - - HIGH - <TBD> - 0x1 - - - BOOTRST - Boot Reset vector Enabled - [0:0] - - - BOOTSZ - Select boot size - [2:1] - - true - - - - 2048W_3800 - Boot Flash size=2048 words start address=$3800 - 0 - - - 1024W_3C00 - Boot Flash size=1024 words start address=$3C00 - 1 - - - 512W_3E00 - Boot Flash size=512 words start address=$3E00 - 2 - - - 256W_3F00 - Boot Flash size=256 words start address=$3F00 - 3 - - - - - EESAVE - Preserve EEPROM through the Chip Erase cycle - [3:3] - - - WDTON - Watch-dog Timer always on - [4:4] - - - SPIEN - Serial program downloading (SPI) enabled - [5:5] - - - DWEN - Debug Wire enable - [6:6] - - - RSTDISBL - Reset Disabled (Enable PC6 as i/o pin) - [7:7] - - - - - LOW - <TBD> - 0x0 - - - SUT_CKSEL - Select Clock Source - [5:0] - - true - - - - EXTCLK_6CK_14CK_0MS - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 0 - - - INTRCOSC_8MHZ_6CK_14CK_0MS - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 2 - - - INTRCOSC_128KHZ_6CK_14CK_0MS - Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 3 - - - EXTLOFXTAL_1KCK_14CK_0MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms - 4 - - - EXTLOFXTAL_32KCK_14CK_0MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms - 5 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 8 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 9 - - - EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 10 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 11 - - - EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 12 - - - EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 13 - - - EXTXOSC_8MHZ_XX_258CK_14CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 14 - - - EXTXOSC_8MHZ_XX_1KCK_14CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 15 - - - EXTCLK_6CK_14CK_4MS1 - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - 16 - - - INTRCOSC_8MHZ_6CK_14CK_4MS1 - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - 18 - - - INTRCOSC_128KHZ_6CK_14CK_4MS1 - Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - 19 - - - EXTLOFXTAL_1KCK_14CK_4MS1 - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms - 20 - - - EXTLOFXTAL_32KCK_14CK_4MS1 - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms - 21 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 24 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 25 - - - EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 26 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 27 - - - EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 28 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 29 - - - EXTXOSC_8MHZ_XX_258CK_14CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 30 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 31 - - - EXTCLK_6CK_14CK_65MS - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms - 32 - - - INTRCOSC_8MHZ_6CK_14CK_65MS - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms - 34 - - - INTRCOSC_128KHZ_6CK_14CK_65MS - Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms - 35 - - - EXTLOFXTAL_1KCK_14CK_65MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms - 36 - - - EXTLOFXTAL_32KCK_14CK_65MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms - 37 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 40 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 41 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 42 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 43 - - - EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 44 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 45 - - - EXTXOSC_8MHZ_XX_1KCK_14CK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 46 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 47 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 56 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 57 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 58 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 59 - - - EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 60 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 61 - - - EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 62 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 63 - - - - - CKOUT - Clock output on PORTB0 - [6:6] - - - CKDIV8 - Divide clock by 8 internally - [7:7] - - - - - - - LOCKBIT - Lockbits - 0x0 - - - LOCKBIT - <TBD> - 0x0 - - - LB - Memory Lock - [1:0] - - true - - - - PROG_VER_DISABLED - Further programming and verification disabled - 0 - - - PROG_DISABLED - Further programming disabled - 2 - - - NO_LOCK - No memory lock features enabled - 3 - - - - - BLB0 - Boot Loader Protection Mode - [3:2] - - true - - - - LPM_SPM_DISABLE - LPM and SPM prohibited in Application Section - 0 - - - LPM_DISABLE - LPM prohibited in Application Section - 1 - - - SPM_DISABLE - SPM prohibited in Application Section - 2 - - - NO_LOCK - No lock on SPM and LPM in Application Section - 3 - - - - - BLB1 - Boot Loader Protection Mode - [5:4] - - true - - - - LPM_SPM_DISABLE - LPM and SPM prohibited in Boot Section - 0 - - - LPM_DISABLE - LPM prohibited in Boot Section - 1 - - - SPM_DISABLE - SPM prohibited in Boot Section - 2 - - - NO_LOCK - No lock on SPM and LPM in Boot Section - 3 - - - - - - - - - PORTB - I/O Port - 0x23 - - - DDRB - Port B Data Direction Register - 0x1 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PINB - Port B Input Pins - 0x0 - read-write - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PORTB - Port B Data Register - 0x2 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - - - PORTC - I/O Port - 0x26 - - - DDRC - Port C Data Direction Register - 0x1 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - - - PINC - Port C Input Pins - 0x0 - read-write - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - - - PORTC - Port C Data Register - 0x2 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - - - - - PORTD - I/O Port - 0x29 - - - DDRD - Port D Data Direction Register - 0x1 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PIND - Port D Input Pins - 0x0 - read-write - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PORTD - Port D Data Register - 0x2 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - - - PORTE - I/O Port - 0x2C - - - DDRE - Port E Data Direction Register - 0x1 - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - - - PINE - Port E Input Pins - 0x0 - read-write - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - - - PORTE - Port E Data Register - 0x2 - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - - - - - SPI0 - <TBD> - 0x4C - - - SPCR - SPI Control Register - 0x0 - - - SPR - SPI Clock Rate Selects - [1:0] - - true - - SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 - - - CPHA - Clock Phase - [2:2] - - - CPOL - Clock polarity - [3:3] - - - MSTR - Master/Slave Select - [4:4] - - - DORD - Data Order - [5:5] - - - SPE - SPI Enable - [6:6] - - - SPIE - SPI Interrupt Enable - [7:7] - - - - - SPDR - SPI Data Register - 0x2 - - - 0 - 255 - - - - - SPSR - SPI Status Register - 0x1 - read-write - - - SPI2X - Double SPI Speed Bit - [0:0] - read-write - - WCOL - Write Collision Flag - [6:6] - read-only - - SPIF - SPI Interrupt Flag - [7:7] - read-only - - - - - - SPI1 - <TBD> - 0xAC - - - SPCR - SPI Control Register - 0x0 - - - SPR - SPI Clock Rate Selects - [1:0] - - true - - SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 - - - CPHA - Clock Phase - [2:2] - - - CPOL - Clock polarity - [3:3] - - - MSTR - Master/Slave Select - [4:4] - - - DORD - Data Order - [5:5] - - - SPE - SPI Enable - [6:6] - - - SPIE - SPI Interrupt Enable - [7:7] - - - - - SPDR - SPI Data Register - 0x2 - - - 0 - 255 - - - - - SPSR - SPI Status Register - 0x1 - read-write - - - SPI2X - Double SPI Speed Bit - [0:0] - read-write - - WCOL - Write Collision Flag - [6:6] - read-only - - SPIF - SPI Interrupt Flag - [7:7] - read-only - - - - - - TC0 - <TBD> - 0x35 - - - GTCCR - General Timer/Counter Control Register - 0xE - - - PSRSYNC - Prescaler Reset Timer/Counter1 and Timer/Counter0 - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - OCR0A - Timer/Counter0 Output Compare Register - 0x12 - - - 0 - 255 - - - - - OCR0B - Timer/Counter0 Output Compare Register - 0x13 - - - 0 - 255 - - - - - TCCR0A - Timer/Counter Control Register A - 0xF - - - WGM0 - Waveform Generation Mode - [1:0] - - true - WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 - - - COM0B - Compare Output B Mode - [5:4] - - true - COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 - - - COM0A - Compare Output A Mode - [7:6] - - true - - - - - - TCCR0B - Timer/Counter Control Register B - 0x10 - - - CS0 - Clock Select - [2:0] - - true - - CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM02 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) - [3:3] - - - FOC0B - Force Output Compare B - [6:6] - write-only - - FOC0A - Force Output Compare A - [7:7] - write-only - - - - TCNT0 - Timer/Counter0 - 0x11 - - - 0 - 255 - - - - - TIFR0 - Timer/Counter0 Interrupt Flag register - 0x0 - read-write - - - TOV0 - Timer/Counter0 Overflow Flag - [0:0] - - - OCF0A - Timer/Counter0 Output Compare Flag 0A - [1:1] - - - OCF0B - Timer/Counter0 Output Compare Flag 0B - [2:2] - - - - - TIMSK0 - Timer/Counter0 Interrupt Mask Register - 0x39 - - - TOIE0 - Timer/Counter0 Overflow Interrupt Enable - [0:0] - - - OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable - [2:2] - - - - - - - TC1 - <TBD> - 0x36 - - - GTCCR - General Timer/Counter Control Register - 0xD - - - PSRSYNC - Prescaler Reset Timer/Counter1 and Timer/Counter0 - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - ICR1 - Timer/Counter1 Input Capture Register Bytes - 0x50 - 16 - - - 0 - 65535 - - - - - OCR1A - Timer/Counter1 Output Compare Register Bytes - 0x52 - 16 - - - 0 - 65535 - - - - - OCR1B - Timer/Counter1 Output Compare Register Bytes - 0x54 - 16 - - - 0 - 65535 - - - - - TCCR1A - Timer/Counter1 Control Register A - 0x4A - - - WGM1 - Waveform Generation Mode - [1:0] - - - 0 - 3 - - - - - COM1B - Compare Output Mode 1B, bits - [5:4] - - true - COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM1A - Compare Output Mode 1A, bits - [7:6] - - true - - - - - - TCCR1B - Timer/Counter1 Control Register B - 0x4B - - - CS1 - Prescaler source of Timer/Counter 1 - [2:0] - - true - CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM1 - Waveform Generation Mode - [4:3] - - - 0 - 3 - - - - - ICES1 - Input Capture 1 Edge Select - [6:6] - - - ICNC1 - Input Capture 1 Noise Canceler - [7:7] - - - - - TCCR1C - Timer/Counter1 Control Register C - 0x4C - - - FOC1B - <TBD> - [6:6] - write-only - - FOC1A - <TBD> - [7:7] - write-only - - - - TCNT1 - Timer/Counter1 Bytes - 0x4E - 16 - - - 0 - 65535 - - - - - TIFR1 - Timer/Counter Interrupt Flag register - 0x0 - read-write - - - TOV1 - Timer/Counter1 Overflow Flag - [0:0] - - - OCF1A - Output Compare Flag 1A - [1:1] - - - OCF1B - Output Compare Flag 1B - [2:2] - - - ICF1 - Input Capture Flag 1 - [5:5] - - - - - TIMSK1 - Timer/Counter Interrupt Mask Register - 0x39 - - - TOIE1 - Timer/Counter1 Overflow Interrupt Enable - [0:0] - - - OCIE1A - Timer/Counter1 Output CompareA Match Interrupt Enable - [1:1] - - - OCIE1B - Timer/Counter1 Output CompareB Match Interrupt Enable - [2:2] - - - ICIE1 - Timer/Counter1 Input Capture Interrupt Enable - [5:5] - - - - - - - TC2 - Timer/Counter, 8-bit Async - 0x37 - - - ASSR - Asynchronous Status Register - 0x7F - - - TCR2BUB - Timer/Counter Control Register2 Update Busy - [0:0] - - - TCR2AUB - Timer/Counter Control Register2 Update Busy - [1:1] - - - OCR2BUB - Output Compare Register 2 Update Busy - [2:2] - - - OCR2AUB - Output Compare Register2 Update Busy - [3:3] - - - TCN2UB - Timer/Counter2 Update Busy - [4:4] - - - AS2 - Asynchronous Timer/Counter2 - [5:5] - - - EXCLK - Enable External Clock Input - [6:6] - - - - - GTCCR - General Timer Counter Control register - 0xC - - - PSRASY - Prescaler Reset Timer/Counter2 - [1:1] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - OCR2A - Timer/Counter2 Output Compare Register A - 0x7C - - - 0 - 255 - - - - - OCR2B - Timer/Counter2 Output Compare Register B - 0x7D - - - 0 - 255 - - - - - TCCR2A - Timer/Counter2 Control Register A - 0x79 - - - WGM2 - Waveform Genration Mode - [1:0] - - true - WGM2read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 - - - COM2B - Compare Output B Mode - [5:4] - - true - COM2Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 - - - COM2A - Compare Output A Mode - [7:6] - - true - - - - - - TCCR2B - Timer/Counter2 Control Register B - 0x7A - - - CS2 - Clock Select bits - [2:0] - - true - - CS2read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_32Running, CLK/323PRESCALE_64Running, CLK/644PRESCALE_128Running, CLK/1285PRESCALE_256Running, CLK/2566PRESCALE_1024Running, CLK/10247 - - - WGM22 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) - [3:3] - - - FOC2B - Force Output Compare B - [6:6] - write-only - - FOC2A - Force Output Compare A - [7:7] - write-only - - - - TCNT2 - Timer/Counter2 - 0x7B - - - 0 - 255 - - - - - TIFR2 - Timer/Counter Interrupt Flag Register - 0x0 - read-write - - - TOV2 - Timer/Counter2 Overflow Flag - [0:0] - - - OCF2A - Output Compare Flag 2A - [1:1] - - - OCF2B - Output Compare Flag 2B - [2:2] - - - - - TIMSK2 - Timer/Counter Interrupt Mask register - 0x39 - - - TOIE2 - Timer/Counter2 Overflow Interrupt Enable - [0:0] - - - OCIE2A - Timer/Counter2 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE2B - Timer/Counter2 Output Compare Match B Interrupt Enable - [2:2] - - - - - - - TC3 - <TBD> - 0x38 - - - ICR3 - Timer/Counter3 Input Capture Register Bytes - 0x5E - 16 - - - 0 - 65535 - - - - - OCR3A - Timer/Counter3 Output Compare Register Bytes - 0x60 - 16 - - - 0 - 65535 - - - - - OCR3B - Timer/Counter3 Output Compare Register Bytes - 0x62 - 16 - - - 0 - 65535 - - - - - TCCR3A - Timer/Counter3 Control Register A - 0x58 - - - WGM3 - Waveform Genration Mode - [1:0] - - - 0 - 3 - - - - - COM3B - Compare Output Mode bits - [5:4] - - true - COM3Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM3A - Compare Output Mode bits - [7:6] - - true - - - - - - TCCR3B - Timer/Counter3 Control Register B - 0x59 - - - CS3 - Clock Select bits - [2:0] - - true - CS3read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - ICES3 - Input Capture Edge Select - [6:6] - - - ICNC3 - Input Capture Noise Canceler - [7:7] - - WGM3Waveform Generation Mode32read-write - - - - TCCR3C - Timer/Counter3 Control Register C - 0x5A - - - FOC3B - Force Output Compare for Channel B - [6:6] - write-only - - FOC3A - Force Output Compare for Channel A - [7:7] - write-only - - - - TCNT3 - Timer/Counter3 Bytes - 0x5C - 16 - - - 0 - 65535 - - - - - TIFR3 - Timer/Counter3 Interrupt Flag register - 0x0 - read-write - - - TOV3 - Timer/Counter3 Overflow Flag - [0:0] - - - OCF3A - Output Compare Flag 3A - [1:1] - - - OCF3B - Output Compare Flag 3B - [2:2] - - - ICF3 - Timer/Counter3 Input Capture Flag - [5:5] - - - - - TIMSK3 - Timer/Counter Interrupt Mask Register - 0x39 - - - TOIE3 - Timer/Counter3 Overflow Interrupt Enable - [0:0] - - - OCIE3A - Timer/Counter3 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE3B - Timer/Counter3 Output Compare Match B Interrupt Enable - [2:2] - - - ICIE3 - Timer/Counter3 Input Capture Interrupt Enable - [5:5] - - - - - - - TC4 - <TBD> - 0x39 - - - ICR4 - Timer/Counter4 Input Capture Register Bytes - 0x6D - 16 - - - 0 - 65535 - - - - - OCR4A - Timer/Counter4 Output Compare Register Bytes - 0x6F - 16 - - - 0 - 65535 - - - - - OCR4B - Timer/Counter4 Output Compare Register Bytes - 0x71 - 16 - - - 0 - 65535 - - - - - TCCR4A - Timer/Counter4 Control Register A - 0x67 - - - WGM4 - Waveform Generation Mode - [1:0] - - - 0 - 3 - - - - - COM4B - Compare Output Mode bits - [5:4] - - true - COM4Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM4A - Compare Output Mode bits - [7:6] - - true - - - - - - TCCR4B - Timer/Counter4 Control Register B - 0x68 - - - CS4 - Clock Select bits - [2:0] - - true - CS4read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - ICES4 - Input Capture Edge Select - [6:6] - - - ICNC4 - Input Capture Noise Canceler - [7:7] - - WGM4Waveform Generation Mode32read-write - - - - TCCR4C - Timer/Counter4 Control Register C - 0x69 - - - FOC4B - Force Output Compare for Channel B - [6:6] - write-only - - FOC4A - Force Output Compare for Channel A - [7:7] - write-only - - - - TCNT4 - Timer/Counter4 Bytes - 0x6B - 16 - - - 0 - 65535 - - - - - TIFR4 - Timer/Counter4 Interrupt Flag register - 0x0 - read-write - - - TOV4 - Timer/Counter4 Overflow Flag - [0:0] - - - OCF4A - Output Compare Flag 4A - [1:1] - - - OCF4B - Output Compare Flag 4B - [2:2] - - - ICF4 - Timer/Counter4 Input Capture Flag - [5:5] - - - - - TIMSK4 - Timer/Counter4 Interrupt Mask Register - 0x39 - - - TOIE4 - Timer/Counter4 Overflow Interrupt Enable - [0:0] - - - OCIE4A - Timer/Counter4 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE4B - Timer/Counter4 Output Compare Match B Interrupt Enable - [2:2] - - - ICIE4 - Timer/Counter4 Input Capture Interrupt Enable - [5:5] - - - - - - - TWI0 - Two Wire Serial Interface - 0xB8 - - - TWAMR - TWI (Slave) Address Mask Register - 0x5 - - - TWAM - TWI (Slave) Address Mask Bits - [7:1] - - - 0 - 127 - - - - - - - TWAR - TWI (Slave) Address register - 0x2 - - - TWGCE - TWI General Call Recognition Enable Bit - [0:0] - - - TWA - TWI (Slave) Address register Bits - [7:1] - - - 0 - 127 - - - - - - - TWBR - TWI Bit Rate register - 0x0 - - - 0 - 255 - - - - - TWCR - TWI Control Register - 0x4 - read-write - - - TWIE - TWI Interrupt Enable - [0:0] - - - TWEN - TWI Enable Bit - [2:2] - - - TWWC - TWI Write Collition Flag - [3:3] - read-only - - TWSTO - TWI Stop Condition Bit - [4:4] - - - TWSTA - TWI Start Condition Bit - [5:5] - - - TWEA - TWI Enable Acknowledge Bit - [6:6] - - - TWINT - TWI Interrupt Flag - [7:7] - - - - - TWDR - TWI Data register - 0x3 - - - 0 - 255 - - - - - TWSR - TWI Status Register - 0x1 - - - TWPS - TWI Prescaler - [1:0] - - true - - TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 - - - TWS - TWI Status - [7:3] - read-only - - 0 - 31 - - - - - - - - - TWI1 - Two Wire Serial Interface - 0xD8 - - - TWAMR - TWI (Slave) Address Mask Register - 0x5 - - - TWAM1 - <TBD> - [7:1] - - - 0 - 127 - - - - - - - TWAR - TWI (Slave) Address register - 0x2 - - - 0 - 255 - - - - - TWBR - TWI Bit Rate register - 0x0 - - - 0 - 255 - - - - - TWCR - TWI Control Register - 0x4 - read-write - - - TWIE - TWI Interrupt Enable - [0:0] - - - TWEN - TWI Enable Bit - [2:2] - - - TWWC - TWI Write Collition Flag - [3:3] - read-only - - TWSTO - TWI Stop Condition Bit - [4:4] - - - TWSTA - TWI Start Condition Bit - [5:5] - - - TWEA - TWI Enable Acknowledge Bit - [6:6] - - - TWINT - TWI Interrupt Flag - [7:7] - - - - - TWDR - TWI Data register - 0x3 - - - 0 - 255 - - - - - TWSR - TWI Status Register - 0x1 - - - TWPS - TWI Prescaler - [1:0] - - true - - TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 - - - TWS - TWI Status - [7:3] - read-only - - 0 - 31 - - - - - - - - - USART0 - USART - 0xC0 - - - UBRR0 - USART Baud Rate Register Bytes - 0x4 - 16 - - - 0 - 65535 - - - - - UCSR0A - USART Control and Status Register A - 0x0 - read-write - - - MPCM0 - Multi-processor Communication Mode - [0:0] - - - U2X0 - Double the USART transmission speed - [1:1] - - - UPE0 - Parity Error - [2:2] - read-only - - DOR0 - Data overRun - [3:3] - read-only - - FE0 - Framing Error - [4:4] - read-only - - UDRE0 - USART Data Register Empty - [5:5] - read-only - - TXC0 - USART Transmit Complete - [6:6] - - - RXC0 - USART Receive Complete - [7:7] - read-only - - - - UCSR0B - USART Control and Status Register B - 0x1 - - - TXB80 - Transmit Data Bit 8 - [0:0] - - - RXB80 - Receive Data Bit 8 - [1:1] - read-only - - UCSZ02 - Character Size - together with UCSZ0 in UCSR0C - [2:2] - - - TXEN0 - Transmitter Enable - [3:3] - - - RXEN0 - Receiver Enable - [4:4] - - - UDRIE0 - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE0 - TX Complete Interrupt Enable - [6:6] - - - RXCIE0 - RX Complete Interrupt Enable - [7:7] - - - - - UCSR0C - USART Control and Status Register C - 0x2 - - - UCPOL0 - Clock Polarity - [0:0] - UCPOL0read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 - - - UCSZ0 - Character Size - together with UCSZ2 in UCSR0B - [2:1] - - - 0 - 3 - - - UCSZ0read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 - - - USBS0 - Stop Bit Select - [3:3] - - true - - USBS0read-writeSTOP11-bit0STOP22-bit1 - - - UPM0 - Parity Mode Bits - [5:4] - - true - - UPM0read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 - - - UMSEL0 - USART Mode Select - [7:6] - - true - - UMSEL0read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 - - - - - UCSR0D - USART Control and Status Register D - 0x3 - - - SFDE - Start frame detection enable - [5:5] - - - RXS - USART RX Start - [6:6] - - - RXSIE - USART RX Start Interrupt Enable - [7:7] - - - - - UDR0 - USART I/O Data Register 0 - 0x6 - - - 0 - 255 - - - - - - - USART1 - USART - 0xC8 - - - UBRR1 - USART Baud Rate Register Bytes - 0x4 - 16 - - - 0 - 65535 - - - - - UCSR1A - USART Control and Status Register A - 0x0 - read-write - - - MPCM1 - Multi-processor Communication Mode - [0:0] - - - U2X1 - Double the USART transmission speed - [1:1] - - - UPE1 - Parity Error - [2:2] - read-only - - DOR1 - Data overRun - [3:3] - read-only - - FE1 - Framing Error - [4:4] - read-only - - UDRE1 - USART Data Register Empty - [5:5] - read-only - - TXC1 - USART Transmit Complete - [6:6] - - - RXC1 - USART Receive Complete - [7:7] - read-only - - - - UCSR1B - USART Control and Status Register B - 0x1 - - - TXB81 - Transmit Data Bit 8 - [0:0] - - - RXB81 - Receive Data Bit 8 - [1:1] - read-only - - UCSZ12 - Character Size - together with UCSZ0 in UCSR1C - [2:2] - - - TXEN1 - Transmitter Enable - [3:3] - - - RXEN1 - Receiver Enable - [4:4] - - - UDRIE1 - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE1 - TX Complete Interrupt Enable - [6:6] - - - RXCIE1 - RX Complete Interrupt Enable - [7:7] - - - - - UCSR1C - USART Control and Status Register C - 0x2 - - - UCPOL1 - Clock Polarity - [0:0] - UCPOL1read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 - - - UCSZ1 - Character Size - together with UCSZ12 in UCSR1B - [2:1] - - - 0 - 3 - - - UCSZ1read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 - - - USBS1 - Stop Bit Select - [3:3] - - true - - USBS1read-writeSTOP11-bit0STOP22-bit1 - - - UPM1 - Parity Mode Bits - [5:4] - - true - - UPM1read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 - - - UMSEL1 - USART Mode Select - [7:6] - - true - - UMSEL1read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 - - - - - UCSR1D - USART Control and Status Register D - 0x3 - - - SFDE1 - Start frame detection enable - [5:5] - - - RXS1 - USART RX Start - [6:6] - - - RXSIE1 - USART RX Start Interrupt Enable - [7:7] - - - - - UDR1 - USART I/O Data Register - 0x6 - - - 0 - 255 - - - - - - - WDT - <TBD> - 0x60 - - - WDTCSR - Watchdog Timer Control Register - 0x0 - read-write - - - WDE - Watch Dog Enable - [3:3] - - - WDCE - Watchdog Change Enable - [4:4] - - - WDIE - Watchdog Timeout Interrupt Enable - [6:6] - - - WDIF - Watchdog Timeout Interrupt Flag - [7:7] - - WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 - - WDPHWatchdog Timer Prescaler - High Bit[5:5] - - - - - - \ No newline at end of file diff --git a/misc/svd/atmega32u4.svd b/misc/svd/atmega32u4.svd deleted file mode 100644 index 704a006..0000000 --- a/misc/svd/atmega32u4.svd +++ /dev/null @@ -1,4649 +0,0 @@ - - Atmel - ATmega32U4 - 8 - 8 - read-write - 0 - 0xff - - - AC - Analog Comparator - 0x50 - - - ACSR - Analog Comparator Control And Status Register - 0x0 - read-write - - - ACIS - Analog Comparator Interrupt Mode Select - [1:0] - - true - - ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 - - - ACIC - Analog Comparator Input Capture Enable - [2:2] - - - ACIE - Analog Comparator Interrupt Enable - [3:3] - - - ACI - Analog Comparator Interrupt Flag - [4:4] - - - ACO - Analog Compare Output - [5:5] - read-only - - ACBG - Analog Comparator Bandgap Select - [6:6] - - - ACD - Analog Comparator Disable - [7:7] - - - - - ADCSRB - ADC Control and Status Register B - 0x2B - - - ACME - Analog Comparator Multiplexer Enable - [6:6] - - - - - DIDR1 - <TBD> - 0x2F - - - AIN0D - AIN0 Digital Input Disable - [0:0] - - - AIN1D - AIN1 Digital Input Disable - [1:1] - - - - - - - ADC - Analog-to-Digital Converter - 0x78 - - - ADC - ADC Data Register Bytes - 0x0 - 16 - - - 0 - 65535 - - - - - ADCSRA - The ADC Control and Status register - 0x2 - read-write - - - ADPS - ADC Prescaler Select Bits - [2:0] - - true - - ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 - - - ADIE - ADC Interrupt Enable - [3:3] - - - ADIF - ADC Interrupt Flag - [4:4] - - - ADATE - ADC Auto Trigger Enable - [5:5] - - - ADSC - ADC Start Conversion - [6:6] - - - ADEN - ADC Enable - [7:7] - - - - - ADCSRB - ADC Control and Status Register B - 0x3 - - - ADTS - ADC Auto Trigger Sources - [4:0] - - true - - - - VAL_0x00 - Free Running mode - 0 - - - VAL_0x01 - Analog Comparator - 1 - - - VAL_0x02 - External Interrupt Request 0 - 2 - - - VAL_0x03 - Timer/Counter0 Compare Match A - 3 - - - VAL_0x04 - Timer/Counter0 Overflow - 4 - - - VAL_0x05 - Timer/Counter1 Compare Match B - 5 - - - VAL_0x06 - Timer/Counter1 Overflow - 6 - - - VAL_0x07 - Timer/Counter1 Capture Event - 7 - - - - - MUX5 - Analog Channel and Gain Selection Bits - [5:5] - - - ADHSM - ADC High Speed Mode - [7:7] - - - - - ADMUX - The ADC multiplexer Selection Register - 0x4 - - - MUX - Analog Channel and Gain Selection Bits - [4:0] - - - 0 - 31 - - - - - ADLAR - Left Adjust Result - [5:5] - - - REFS - Reference Selection Bits - [7:6] - - true - - REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 - - - - - DIDR0 - Digital Input Disable Register 0 - 0x6 - - - ADC0D - ADC0 Digital input Disable - [0:0] - - - ADC1D - ADC1 Digital input Disable - [1:1] - - - ADC2D - ADC2 Digital input Disable - [2:2] - - - ADC3D - ADC3 Digital input Disable - [3:3] - - - ADC4D - ADC4 Digital input Disable - [4:4] - - - ADC5D - ADC5 Digital input Disable - [5:5] - - - ADC6D - ADC6 Digital input Disable - [6:6] - - - ADC7D - ADC7 Digital input Disable - [7:7] - - - - - DIDR2 - Digital Input Disable Register 2 - 0x5 - - - ADC8D - ADC8 Digital input Disable - [0:0] - - - ADC9D - ADC9 Digital input Disable - [1:1] - - - ADC10D - ADC10 Digital input Disable - [2:2] - - - ADC11D - ADC11 Digital input Disable - [3:3] - - - ADC12D - ADC12 Digital input Disable - [4:4] - - - ADC13D - ADC13 Digital input Disable - [5:5] - - - - - - - BOOT_LOAD - Bootloader - 0x57 - - - SPMCSR - Store Program Memory Control Register - 0x0 - - - SPMEN - Store Program Memory Enable - [0:0] - - - PGERS - Page Erase - [1:1] - - - PGWRT - Page Write - [2:2] - - - BLBSET - Boot Lock Bit Set - [3:3] - - - RWWSRE - Read While Write section read enable - [4:4] - - - SIGRD - Signature Row Read - [5:5] - - - RWWSB - Read While Write Section Busy - [6:6] - - - SPMIE - SPM Interrupt Enable - [7:7] - - - - - - - CPU - CPU Registers - 0x3E - - RESET - External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. - 0 - - - INT0 - External Interrupt Request 0 - 1 - - - INT1 - External Interrupt Request 1 - 2 - - - INT2 - External Interrupt Request 2 - 3 - - - INT3 - External Interrupt Request 3 - 4 - - - Reserved1 - Reserved1 - 5 - - - Reserved2 - Reserved2 - 6 - - - INT6 - External Interrupt Request 6 - 7 - - - Reserved3 - Reserved3 - 8 - - - PCINT0 - Pin Change Interrupt Request 0 - 9 - - - USB_GEN - USB General Interrupt Request - 10 - - - USB_COM - USB Endpoint/Pipe Interrupt Communication Request - 11 - - - WDT - Watchdog Time-out Interrupt - 12 - - - Reserved4 - Reserved4 - 13 - - - Reserved5 - Reserved5 - 14 - - - Reserved6 - Reserved6 - 15 - - - TIMER1_CAPT - Timer/Counter1 Capture Event - 16 - - - TIMER1_COMPA - Timer/Counter1 Compare Match A - 17 - - - TIMER1_COMPB - Timer/Counter1 Compare Match B - 18 - - - TIMER1_COMPC - Timer/Counter1 Compare Match C - 19 - - - TIMER1_OVF - Timer/Counter1 Overflow - 20 - - - TIMER0_COMPA - Timer/Counter0 Compare Match A - 21 - - - TIMER0_COMPB - Timer/Counter0 Compare Match B - 22 - - - TIMER0_OVF - Timer/Counter0 Overflow - 23 - - - SPI_STC - SPI Serial Transfer Complete - 24 - - - USART1_RX - USART1, Rx Complete - 25 - - - USART1_UDRE - USART1 Data register Empty - 26 - - - USART1_TX - USART1, Tx Complete - 27 - - - ANALOG_COMP - Analog Comparator - 28 - - - ADC - ADC Conversion Complete - 29 - - - EE_READY - EEPROM Ready - 30 - - - TIMER3_CAPT - Timer/Counter3 Capture Event - 31 - - - TIMER3_COMPA - Timer/Counter3 Compare Match A - 32 - - - TIMER3_COMPB - Timer/Counter3 Compare Match B - 33 - - - TIMER3_COMPC - Timer/Counter3 Compare Match C - 34 - - - TIMER3_OVF - Timer/Counter3 Overflow - 35 - - - TWI - 2-wire Serial Interface - 36 - - - SPM_READY - Store Program Memory Read - 37 - - - TIMER4_COMPA - Timer/Counter4 Compare Match A - 38 - - - TIMER4_COMPB - Timer/Counter4 Compare Match B - 39 - - - TIMER4_COMPD - Timer/Counter4 Compare Match D - 40 - - - TIMER4_OVF - Timer/Counter4 Overflow - 41 - - - TIMER4_FPF - Timer/Counter4 Fault Protection Interrupt - 42 - - - - CLKPR - <TBD> - 0x23 - - - CLKPS - <TBD> - [3:0] - - true - - - - VAL_0x00 - 1 - 0 - - - VAL_0x01 - 2 - 1 - - - VAL_0x02 - 4 - 2 - - - VAL_0x03 - 8 - 3 - - - VAL_0x04 - 16 - 4 - - - VAL_0x05 - 32 - 5 - - - VAL_0x06 - 64 - 6 - - - VAL_0x07 - 128 - 7 - - - VAL_0x08 - 256 - 8 - - - - - CLKPCE - <TBD> - [7:7] - - - - - CLKSEL0 - <TBD> - 0x87 - - - CLKS - <TBD> - [0:0] - - - EXTE - <TBD> - [2:2] - - - RCE - <TBD> - [3:3] - - - EXSUT - <TBD> - [5:4] - - - 0 - 3 - - - - - RCSUT - <TBD> - [7:6] - - - 0 - 3 - - - - - - - CLKSEL1 - <TBD> - 0x88 - - - EXCKSEL - <TBD> - [3:0] - - - 0 - 15 - - - - - RCCKSEL - <TBD> - [7:4] - - - 0 - 15 - - - - - - - CLKSTA - <TBD> - 0x89 - read-only - - - EXTON - <TBD> - [0:0] - - - RCON - <TBD> - [1:1] - - - - - EIND - Extended Indirect Register - 0x1E - - - 0 - 255 - - - - - GPIOR0 - General Purpose IO Register 0 - 0x0 - - - GPIOR00 - General Purpose IO Register 0 bit 0 - [0:0] - - - GPIOR01 - General Purpose IO Register 0 bit 1 - [1:1] - - - GPIOR02 - General Purpose IO Register 0 bit 2 - [2:2] - - - GPIOR03 - General Purpose IO Register 0 bit 3 - [3:3] - - - GPIOR04 - General Purpose IO Register 0 bit 4 - [4:4] - - - GPIOR05 - General Purpose IO Register 0 bit 5 - [5:5] - - - GPIOR06 - General Purpose IO Register 0 bit 6 - [6:6] - - - GPIOR07 - General Purpose IO Register 0 bit 7 - [7:7] - - - - - GPIOR1 - General Purpose IO Register 1 - 0xC - - - GPIOR - General Purpose IO Register 1 bis - [7:0] - - - 0 - 255 - - - - - - - GPIOR2 - General Purpose IO Register 2 - 0xD - - - GPIOR - General Purpose IO Register 2 bis - [7:0] - - - 0 - 255 - - - - - - - MCUCR - MCU Control Register - 0x17 - - - IVCE - Interrupt Vector Change Enable - [0:0] - - - IVSEL - Interrupt Vector Select - [1:1] - - - PUD - Pull-up disable - [4:4] - - - JTD - JTAG Interface Disable - [7:7] - - - - - MCUSR - MCU Status Register - 0x16 - - - PORF - Power-on reset flag - [0:0] - - - EXTRF - External Reset Flag - [1:1] - - - BORF - Brown-out Reset Flag - [2:2] - - - WDRF - Watchdog Reset Flag - [3:3] - - - JTRF - JTAG Reset Flag - [4:4] - - - - - OSCCAL - Oscillator Calibration Value - 0x28 - - - OSCCAL - Oscillator Calibration - [7:0] - - - 0 - 255 - - - - - - - PRR0 - Power Reduction Register0 - 0x26 - - - PRADC - Power Reduction ADC - [0:0] - - - PRUSART0 - Power Reduction USART - [1:1] - - - PRSPI - Power Reduction Serial Peripheral Interface - [2:2] - - - PRTIM1 - Power Reduction Timer/Counter1 - [3:3] - - - PRTIM0 - Power Reduction Timer/Counter0 - [5:5] - - - PRTIM2 - Power Reduction Timer/Counter2 - [6:6] - - - PRTWI - Power Reduction TWI - [7:7] - - - - - PRR1 - Power Reduction Register1 - 0x27 - - - PRUSART1 - Power Reduction USART1 - [0:0] - - - PRTIM3 - Power Reduction Timer/Counter3 - [3:3] - - - PRTIM4 - Power Reduction Timer/Counter4 - [4:4] - - - PRUSB - Power Reduction USB - [7:7] - - - - - RAMPZ - Extended Z-pointer Register for ELPM/SPM - 0x1D - - - RAMPZ - Extended Z-Pointer Value - [1:0] - - true - - - - VAL_0 - Default value of Z-pointer MSB's. - 0 - - - - - Res - Reserved - [7:2] - - - 0 - 63 - - - - - - - RCCTRL - Oscillator Control Register - 0x29 - - - RCFREQ - <TBD> - [0:0] - - - - - SMCR - Sleep Mode Control Register - 0x15 - - - SE - Sleep Enable - [0:0] - - - SM - Sleep Mode Select bits - [3:1] - - true - - - - IDLE - Idle - 0 - - - ADC - ADC Noise Reduction (If Available) - 1 - - - PDOWN - Power Down - 2 - - - PSAVE - Power Save - 3 - - - VAL_0x04 - Reserved - 4 - - - VAL_0x05 - Reserved - 5 - - - STDBY - Standby - 6 - - - ESTDBY - Extended Standby - 7 - - - - - - - - - EEPROM - EEPROM - 0x3F - - - EEAR - EEPROM Address Register Low Bytes - 0x2 - 16 - - - 0 - 65535 - - - - - EECR - EEPROM Control Register - 0x0 - - - EERE - EEPROM Read Enable - [0:0] - - - EEPE - EEPROM Write Enable - [1:1] - - - EEMPE - EEPROM Master Write Enable - [2:2] - - - EERIE - EEPROM Ready Interrupt Enable - [3:3] - - - EEPM - EEPROM Programming Mode Bits - [5:4] - - true - - - - VAL_0x00 - Erase and Write in one operation - 0 - - - VAL_0x01 - Erase Only - 1 - - - VAL_0x02 - Write Only - 2 - - - - - - - EEDR - EEPROM Data Register - 0x1 - - - 0 - 255 - - - - - - - EXINT - External Interrupts - 0x3B - - - EICRA - External Interrupt Control Register A - 0x2E - - - ISC0 - External Interrupt Sense Control Bit - [1:0] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC1 - External Interrupt Sense Control Bit - [3:2] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC2 - External Interrupt Sense Control Bit - [5:4] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC3 - External Interrupt Sense Control Bit - [7:6] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - - - EICRB - External Interrupt Control Register B - 0x2F - - - ISC4 - External Interrupt 7-4 Sense Control Bit - [1:0] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC5 - External Interrupt 7-4 Sense Control Bit - [3:2] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC6 - External Interrupt 7-4 Sense Control Bit - [5:4] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC7 - External Interrupt 7-4 Sense Control Bit - [7:6] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - - - EIFR - External Interrupt Flag Register - 0x1 - read-only - - - INTF - External Interrupt Flags - [7:0] - - - 0 - 255 - - - - - - - EIMSK - External Interrupt Mask Register - 0x2 - - - INT - External Interrupt Request 7 Enable - [7:0] - - - 0 - 255 - - - - - - - PCICR - Pin Change Interrupt Control Register - 0x2D - - - PCIE0 - Pin Change Interrupt Enable 0 - [0:0] - - - - - PCIFR - Pin Change Interrupt Flag Register - 0x0 - read-only - - - PCIF0 - Pin Change Interrupt Flag 0 - [0:0] - - - - - PCMSK0 - Pin Change Mask Register 0 - 0x30 - - - 0 - 255 - - - - - - - FUSE - Fuses - 0x0 - - - EXTENDED - <TBD> - 0x2 - - - BODLEVEL - Brown-out Detector trigger level - [2:0] - - true - - - - 4V3 - Brown-out detection at VCC=4.3 V - 0 - - - 3V5 - Brown-out detection at VCC=3.5 V - 1 - - - 3V4 - Brown-out detection at VCC=3.4 V - 2 - - - 2V6 - Brown-out detection at VCC=2.6 V - 3 - - - 2V4 - Brown-out detection at VCC=2.4 V - 4 - - - 2V2 - Brown-out detection at VCC=2.2 V - 5 - - - 2V0 - Brown-out detection at VCC=2.0 V - 6 - - - DISABLED - Brown-out detection disabled; [BODLEVEL=111] - 7 - - - - - HWBE - Hardware Boot Enable - [3:3] - - - - - HIGH - <TBD> - 0x1 - - - BOOTRST - Boot Reset vector Enabled - [0:0] - - - BOOTSZ - Select Boot Size - [2:1] - - true - - - - 2048W_3800 - Boot Flash size=2048 words start address=$3800 - 0 - - - 1024W_3C00 - Boot Flash size=1024 words start address=$3C00 - 1 - - - 512W_3E00 - Boot Flash size=512 words start address=$3E00 - 2 - - - 256W_3F00 - Boot Flash size=256 words start address=$3F00 - 3 - - - - - EESAVE - Preserve EEPROM through the Chip Erase cycle - [3:3] - - - WDTON - Watchdog timer always on - [4:4] - - - SPIEN - Serial program downloading (SPI) enabled - [5:5] - - - JTAGEN - JTAG Interface Enabled - [6:6] - - - OCDEN - On-Chip Debug Enabled - [7:7] - - - - - LOW - <TBD> - 0x0 - - - SUT_CKSEL - Select Clock Source - [5:0] - - true - - - - EXTCLK_6CK_0MS - Ext. Clock; Start-up time: 6 CK + 0 ms - 0 - - - INTRCOSC_6CK_0MS - Int. RC Osc.; Start-up time: 6 CK + 0 ms - 2 - - - EXTLOFXTAL_1KCK_0MS - Ext. Low-Freq. Crystal; Start-up time: 1K CK + 0 ms - 4 - - - EXTLOFXTAL_32KCK_0MS - Ext. Low-Freq. Crystal; Start-up time: 32K CK + 0 ms - 5 - - - EXTLOFXTAL_1KCK_0MS_INTCAP - Ext. Low-Freq. Crystal; Start-up time: 1K CK + 0 ms; Int. Cap. - 6 - - - EXTLOFXTAL_32KCK_0MS_INTCAP - Ext. Low-Freq. Crystal; Start-up time: 32K CK + 0 ms; Int. Cap. - 7 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 258 CK + 4.1 ms - 8 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 65 ms - 9 - - - EXTXOSC_0MHZ9_3MHZ_258CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 258 CK + 4.1 ms - 10 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 65 ms - 11 - - - EXTXOSC_3MHZ_8MHZ_258CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 258 CK + 4.1 ms - 12 - - - EXTXOSC_3MHZ_8MHZ_1KCK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 65 ms - 13 - - - EXTXOSC_8MHZ_XX_258CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time: 258 CK + 4.1 ms - 14 - - - EXTXOSC_8MHZ_XX_1KCK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 65 ms - 15 - - - EXTCLK_6CK_4MS1 - Ext. Clock; Start-up time: 6 CK + 4.1 ms - 16 - - - INTRCOSC_6CK_4MS1 - Int. RC Osc.; Start-up time: 6 CK + 4.1 ms - 18 - - - EXTLOFXTAL_1KCK_4MS1 - Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4.1 ms - 20 - - - EXTLOFXTAL_32KCK_4MS1 - Ext. Low-Freq. Crystal; Start-up time: 32K CK + 4.1 ms - 21 - - - EXTLOFXTAL_1KCK_4MS1_INTCAP - Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4.1 ms; Int. Cap. - 22 - - - EXTLOFXTAL_32KCK_4MS1_INTCAP - Ext. Low-Freq. Crystal; Start-up time: 32K CK + 4.1 ms; Int. Cap. - 23 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 258 CK + 65 ms - 24 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 0 ms - 25 - - - EXTXOSC_0MHZ9_3MHZ_258CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 258 CK + 65 ms - 26 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 0 ms - 27 - - - EXTXOSC_3MHZ_8MHZ_258CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 258 CK + 65 ms - 28 - - - EXTXOSC_3MHZ_8MHZ_16KCK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 0 ms - 29 - - - EXTXOSC_8MHZ_XX_258CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 258 CK + 65 ms - 30 - - - EXTXOSC_8MHZ_XX_16KCK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 0 ms - 31 - - - EXTCLK_6CK_65MS - Ext. Clock; Start-up time: 6 CK + 65 ms - 32 - - - INTRCOSC_6CK_65MS - Int. RC Osc.; Start-up time: 6 CK + 65 ms - 34 - - - EXTLOFXTAL_1KCK_65MS - Ext. Low-Freq. Crystal; Start-up time: 1K CK + 65 ms - 36 - - - EXTLOFXTAL_32KCK_65MS - Ext. Low-Freq. Crystal; Start-up time: 32K CK + 65 ms - 37 - - - EXTLOFXTAL_1KCK_65MS_INTCAP - Ext. Low-Freq. Crystal; Start-up time: 1K CK + 65 ms; Int. Cap. - 38 - - - EXTLOFXTAL_32KCK_65MS_INTCAP - Ext. Low-Freq. Crystal; Start-up time: 32K CK + 65 ms; Int. Cap. - 39 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 0 ms - 40 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 4.1 ms - 41 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 0 ms - 42 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 4.1 ms - 43 - - - EXTXOSC_3MHZ_8MHZ_1KCK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 0 ms - 44 - - - EXTXOSC_3MHZ_8MHZ_16KCK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 4.1 ms - 45 - - - EXTXOSC_8MHZ_XX_1KCK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 0 ms - 46 - - - EXTXOSC_8MHZ_XX_16KCK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 4.1 ms - 47 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 4.1 ms - 56 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 65 ms - 57 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 4.1 ms - 58 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 65 ms - 59 - - - EXTXOSC_3MHZ_8MHZ_1KCK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 4.1 ms - 60 - - - EXTXOSC_3MHZ_8MHZ_16KCK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 65 ms - 61 - - - EXTXOSC_8MHZ_XX_1KCK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 4.1 ms - 62 - - - EXTXOSC_8MHZ_XX_16KCK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 65 ms - 63 - - - - - CKOUT - Clock output on PORTC7 - [6:6] - - - CKDIV8 - Divide clock by 8 internally - [7:7] - - - - - - - JTAG - JTAG Interface - 0x51 - - - MCUCR - MCU Control Register - 0x4 - - - JTD - JTAG Interface Disable - [7:7] - - - - - MCUSR - MCU Status Register - 0x3 - read-only - - - JTRF - JTAG Reset Flag - [4:4] - - - - - OCDR - On-Chip Debug Related Register in I/O Memory - 0x0 - - - 0 - 255 - - - - - - - LOCKBIT - Lockbits - 0x0 - - - LOCKBIT - <TBD> - 0x0 - - - LB - Memory Lock - [1:0] - - true - - - - PROG_VER_DISABLED - Further programming and verification disabled - 0 - - - PROG_DISABLED - Further programming disabled - 2 - - - NO_LOCK - No memory lock features enabled - 3 - - - - - BLB0 - Boot Loader Protection Mode - [3:2] - - true - - - - LPM_SPM_DISABLE - LPM and SPM prohibited in Application Section - 0 - - - LPM_DISABLE - LPM prohibited in Application Section - 1 - - - SPM_DISABLE - SPM prohibited in Application Section - 2 - - - NO_LOCK - No lock on SPM and LPM in Application Section - 3 - - - - - BLB1 - Boot Loader Protection Mode - [5:4] - - true - - - - LPM_SPM_DISABLE - LPM and SPM prohibited in Boot Section - 0 - - - LPM_DISABLE - LPM prohibited in Boot Section - 1 - - - SPM_DISABLE - SPM prohibited in Boot Section - 2 - - - NO_LOCK - No lock on SPM and LPM in Boot Section - 3 - - - - - - - - - PLL - Phase Locked Loop - 0x49 - - - PLLCSR - PLL Status and Control register - 0x0 - - - PLOCK - PLL Lock Status Bit - [0:0] - read-only - - PLLE - PLL Enable Bit - [1:1] - - - PINDIV - PLL prescaler Bit 2 - [4:4] - - - - - PLLFRQ - PLL Frequency Control Register - 0x9 - - - PDIV - PLL Lock Frequency - [3:0] - PDIVread-writeMHZ4040 MHz3MHZ4848 MHz4MHZ5656 MHz5MHZ7272 MHz7MHZ8080 MHz8MHZ8888 MHz9MHZ9696 MHz10 - - - PLLTM - PLL Postscaler for High Speed Timer - [5:4] - - true - PLLTMread-writeDISCONNECTED0 (Disconnected)0FACTOR_111FACTOR_151.52FACTOR_223 - - - PLLUSB - PLL Postscaler for USB Peripheral - [6:6] - - - PINMUX - PLL Input Multiplexer - [7:7] - - - - - - - PORTB - I/O Port - 0x23 - - - DDRB - Port B Data Direction Register - 0x1 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PINB - Port B Input Pins - 0x0 - read-write - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PORTB - Port B Data Register - 0x2 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - - - PORTC - I/O Port - 0x26 - - - DDRC - Port C Data Direction Register - 0x1 - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - PINC - Port C Input Pins - 0x0 - read-write - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - PORTC - Port C Data Register - 0x2 - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - - - PORTD - I/O Port - 0x29 - - - DDRD - Port D Data Direction Register - 0x1 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PIND - Port D Input Pins - 0x0 - read-write - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PORTD - Port D Data Register - 0x2 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - - - PORTE - I/O Port - 0x2C - - - DDRE - Data Direction Register, Port E - 0x1 - - - PE2 - Pin E2 - [2:2] - - - PE6 - Pin E6 - [6:6] - - - - - PINE - Input Pins, Port E - 0x0 - read-write - - - PE2 - Pin E2 - [2:2] - - - PE6 - Pin E6 - [6:6] - - - - - PORTE - Data Register, Port E - 0x2 - - - PE2 - Pin E2 - [2:2] - - - PE6 - Pin E6 - [6:6] - - - - - - - PORTF - I/O Port - 0x2F - - - DDRF - Data Direction Register, Port F - 0x1 - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - - - PINF - Input Pins, Port F - 0x0 - read-write - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - - - PORTF - Data Register, Port F - 0x2 - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - - - - - SPI - Serial Peripheral Interface - 0x4C - - - SPCR - SPI Control Register - 0x0 - - - SPR - SPI Clock Rate Selects - [1:0] - - true - - SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 - - - CPHA - Clock Phase - [2:2] - - - CPOL - Clock polarity - [3:3] - - - MSTR - Master/Slave Select - [4:4] - - - DORD - Data Order - [5:5] - - - SPE - SPI Enable - [6:6] - - - SPIE - SPI Interrupt Enable - [7:7] - - - - - SPDR - SPI Data Register - 0x2 - - - 0 - 255 - - - - - SPSR - SPI Status Register - 0x1 - read-write - - - SPI2X - Double SPI Speed Bit - [0:0] - read-write - - WCOL - Write Collision Flag - [6:6] - read-only - - SPIF - SPI Interrupt Flag - [7:7] - read-only - - - - - - TC0 - Timer/Counter, 8-bit - 0x35 - - - GTCCR - General Timer/Counter Control Register - 0xE - - - PSRSYNC - Prescaler Reset Timer/Counter1 and Timer/Counter0 - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - OCR0A - Timer/Counter0 Output Compare Register - 0x12 - - - 0 - 255 - - - - - OCR0B - Timer/Counter0 Output Compare Register - 0x13 - - - 0 - 255 - - - - - TCCR0A - Timer/Counter Control Register A - 0xF - - - WGM0 - Waveform Generation Mode - [1:0] - - true - WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 - - - COM0B - Compare Output B Mode - [5:4] - - true - COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 - - - COM0A - Compare Output A Mode - [7:6] - - true - - - - - - TCCR0B - Timer/Counter Control Register B - 0x10 - - - CS0 - Clock Select - [2:0] - - true - - CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM02 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) - [3:3] - - - FOC0B - Force Output Compare B - [6:6] - write-only - - FOC0A - Force Output Compare A - [7:7] - write-only - - - - TCNT0 - Timer/Counter0 - 0x11 - - - 0 - 255 - - - - - TIFR0 - Timer/Counter0 Interrupt Flag register - 0x0 - read-write - - - TOV0 - Timer/Counter0 Overflow Flag - [0:0] - - - OCF0A - Timer/Counter0 Output Compare Flag 0A - [1:1] - - - OCF0B - Timer/Counter0 Output Compare Flag 0B - [2:2] - - - - - TIMSK0 - Timer/Counter0 Interrupt Mask Register - 0x39 - - - TOIE0 - Timer/Counter0 Overflow Interrupt Enable - [0:0] - - - OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable - [2:2] - - - - - - - TC1 - Timer/Counter, 16-bit - 0x36 - - - ICR1 - Timer/Counter1 Input Capture Register Bytes - 0x50 - 16 - - - 0 - 65535 - - - - - OCR1A - Timer/Counter1 Output Compare Register A Bytes - 0x52 - 16 - - - 0 - 65535 - - - - - OCR1B - Timer/Counter1 Output Compare Register B Bytes - 0x54 - 16 - - - 0 - 65535 - - - - - OCR1C - Timer/Counter1 Output Compare Register C Bytes - 0x56 - 16 - - - 0 - 65535 - - - - - TCCR1A - Timer/Counter1 Control Register A - 0x4A - - - WGM1 - Waveform Generation Mode - [1:0] - - - 0 - 3 - - - - - COM1C - Compare Output Mode 1C, bits - [3:2] - - true - COM1Cread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM1B - Compare Output Mode 1B, bits - [5:4] - - true - - - - COM1A - Compare Output Mode 1A, bits - [7:6] - - true - - - - - - TCCR1B - Timer/Counter1 Control Register B - 0x4B - - - CS1 - Prescaler source of Timer/Counter 1 - [2:0] - - true - CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM1 - Waveform Generation Mode - [4:3] - - - 0 - 3 - - - - - ICES1 - Input Capture 1 Edge Select - [6:6] - - - ICNC1 - Input Capture 1 Noise Canceler - [7:7] - - - - - TCCR1C - Timer/Counter 1 Control Register C - 0x4C - - - FOC1C - Force Output Compare 1C - [5:5] - write-only - - FOC1B - Force Output Compare 1B - [6:6] - write-only - - FOC1A - Force Output Compare 1A - [7:7] - write-only - - - - TCNT1 - Timer/Counter1 Bytes - 0x4E - 16 - - - 0 - 65535 - - - - - TIFR1 - Timer/Counter1 Interrupt Flag register - 0x0 - read-write - - - TOV1 - Timer/Counter1 Overflow Flag - [0:0] - - - OCF1A - Output Compare Flag 1A - [1:1] - - - OCF1B - Output Compare Flag 1B - [2:2] - - - OCF1C - Output Compare Flag 1C - [3:3] - - - ICF1 - Input Capture Flag 1 - [5:5] - - - - - TIMSK1 - Timer/Counter1 Interrupt Mask Register - 0x39 - - - TOIE1 - Timer/Counter1 Overflow Interrupt Enable - [0:0] - - - OCIE1A - Timer/Counter1 Output Compare A Match Interrupt Enable - [1:1] - - - OCIE1B - Timer/Counter1 Output Compare B Match Interrupt Enable - [2:2] - - - OCIE1C - Timer/Counter1 Output Compare C Match Interrupt Enable - [3:3] - - - ICIE1 - Timer/Counter1 Input Capture Interrupt Enable - [5:5] - - - - - - - TC3 - Timer/Counter, 16-bit - 0x38 - - - ICR3 - Timer/Counter3 Input Capture Register Bytes - 0x5E - 16 - - - 0 - 65535 - - - - - OCR3A - Timer/Counter3 Output Compare Register A Bytes - 0x60 - 16 - - - 0 - 65535 - - - - - OCR3B - Timer/Counter3 Output Compare Register B Bytes - 0x62 - 16 - - - 0 - 65535 - - - - - OCR3C - Timer/Counter3 Output Compare Register B Bytes - 0x64 - 16 - - - 0 - 65535 - - - - - TCCR3A - Timer/Counter3 Control Register A - 0x58 - - - WGM3 - Waveform Generation Mode - [1:0] - - - 0 - 3 - - - - - COM3C - Compare Output Mode 3C, bits - [3:2] - - true - COM3Cread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM3B - Compare Output Mode 3B, bits - [5:4] - - true - - - - COM3A - Compare Output Mode 1A, bits - [7:6] - - true - - - - - - TCCR3B - Timer/Counter3 Control Register B - 0x59 - - - CS3 - Prescaler source of Timer/Counter 3 - [2:0] - - true - CS3read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM3 - Waveform Generation Mode - [4:3] - - - 0 - 3 - - - - - ICES3 - Input Capture 3 Edge Select - [6:6] - - - ICNC3 - Input Capture 3 Noise Canceler - [7:7] - - - - - TCCR3C - Timer/Counter 3 Control Register C - 0x5A - - - FOC3C - Force Output Compare 3C - [5:5] - write-only - - FOC3B - Force Output Compare 3B - [6:6] - write-only - - FOC3A - Force Output Compare 3A - [7:7] - write-only - - - - TCNT3 - Timer/Counter3 Bytes - 0x5C - 16 - - - 0 - 65535 - - - - - TIFR3 - Timer/Counter3 Interrupt Flag register - 0x0 - read-write - - - TOV3 - Timer/Counter3 Overflow Flag - [0:0] - - - OCF3A - Output Compare Flag 3A - [1:1] - - - OCF3B - Output Compare Flag 3B - [2:2] - - - OCF3C - Output Compare Flag 3C - [3:3] - - - ICF3 - Input Capture Flag 3 - [5:5] - - - - - TIMSK3 - Timer/Counter3 Interrupt Mask Register - 0x39 - - - TOIE3 - Timer/Counter3 Overflow Interrupt Enable - [0:0] - - - OCIE3A - Timer/Counter3 Output Compare A Match Interrupt Enable - [1:1] - - - OCIE3B - Timer/Counter3 Output Compare B Match Interrupt Enable - [2:2] - - - OCIE3C - Timer/Counter3 Output Compare C Match Interrupt Enable - [3:3] - - - ICIE3 - Timer/Counter3 Input Capture Interrupt Enable - [5:5] - - - - - - - TC4 - Timer/Counter, 10-bit - 0x39 - - - DT4 - Timer/Counter 4 Dead Time Value - 0x9B - - - DT4L - Timer/Counter 4 Dead Time Value Bits - [7:0] - - - 0 - 255 - - - - - - - OCR4A - Timer/Counter4 Output Compare Register A - 0x96 - - - 0 - 255 - - - - - OCR4B - Timer/Counter4 Output Compare Register B - 0x97 - - - 0 - 255 - - - - - OCR4C - Timer/Counter4 Output Compare Register C - 0x98 - - - 0 - 255 - - - - - OCR4D - Timer/Counter4 Output Compare Register D - 0x99 - - - 0 - 255 - - - - - TC4H - Timer/Counter High Bits - 0x86 - - - 0 - 255 - - - - - TCCR4A - Timer/Counter4 Control Register A - 0x87 - - - PWM4B - <TBD> - [0:0] - - - PWM4A - <TBD> - [1:1] - - - FOC4B - Force Output Compare Match 4B - [2:2] - write-only - - FOC4A - Force Output Compare Match 4A - [3:3] - write-only - - COM4B - Compare Output Mode 4B, bits - [5:4] - - true - COM4Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 - - - COM4A - Compare Output Mode 1A, bits - [7:6] - - true - - - - - - TCCR4B - Timer/Counter4 Control Register B - 0x88 - - - CS4 - Clock Select Bits - [3:0] - - true - CS4read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_2Running, CLK/22PRESCALE_4Running, CLK/43PRESCALE_8Running, CLK/84PRESCALE_16Running, CLK/165PRESCALE_32Running, CLK/326PRESCALE_64Running, CLK/647PRESCALE_128Running, CLK/1288PRESCALE_256Running, CLK/2569PRESCALE_512Running, CLK/51210PRESCALE_1024Running, CLK/102411PRESCALE_2048Running, CLK/204812PRESCALE_4096Running, CLK/409613PRESCALE_8192Running, CLK/819214PRESCALE_16384Running, CLK/1638415 - - - DTPS4 - Dead Time Prescaler Bits - [5:4] - - - 0 - 3 - - - DTPS4read-writeX11x (no division)0X22x1X44x2X88x3 - - - PSR4 - Prescaler Reset Timer/Counter 4 - [6:6] - - - PWM4X - PWM Inversion Mode - [7:7] - - - - - TCCR4C - Timer/Counter 4 Control Register C - 0x89 - - - PWM4D - Pulse Width Modulator D Enable - [0:0] - - - FOC4D - Force Output Compare Match 4D - [1:1] - write-only - - COM4D - Comparator D Output Mode - [3:2] - - true - COM4Dread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 - - - COM4B0S - Comparator B Output Mode - [4:4] - - - COM4B1S - Comparator B Output Mode - [5:5] - - - COM4A0S - Comparator A Output Mode - [6:6] - - - COM4A1S - Comparator A Output Mode - [7:7] - - - - - TCCR4D - Timer/Counter 4 Control Register D - 0x8A - - - WGM4 - Waveform Generation Mode bits - [1:0] - - true - WGM4read-writePWM_FASTFast PWM, Update: *TOP*, Flag: *TOP*0PWM_CORRECTPhase and Frequency Correct PWM, Update: *BOTTOM*, Flag: *BOTTOM*1PWM_SINGLE_SLOPEPWM6 / Single-slope, Update: *TOP*, Flag: *TOP*2PWM_DUAL_SLOPEPWM6 / Dual-slope, Update: *BOTTOM*, Flag: *BOTTOM*3 - - - FPF4 - Fault Protection Interrupt Flag - [2:2] - - - FPAC4 - Fault Protection Analog Comparator Enable - [3:3] - - - FPES4 - Fault Protection Edge Select - [4:4] - - - FPNC4 - Fault Protection Noise Canceler - [5:5] - - - FPEN4 - Fault Protection Mode Enable - [6:6] - - - FPIE4 - Fault Protection Interrupt Enable - [7:7] - - - - - TCCR4E - Timer/Counter 4 Control Register E - 0x8B - - - OC4OE - Output Compare Override Enable bit - [5:0] - - - 0 - 63 - - - - - ENHC4 - Enhanced Compare/PWM Mode - [6:6] - - - TLOCK4 - Register Update Lock - [7:7] - - - - - TCNT4 - Timer/Counter4 Low Bytes - 0x85 - - - 0 - 255 - - - - - TIFR4 - Timer/Counter4 Interrupt Flag register - 0x0 - read-only - - - TOV4 - Timer/Counter4 Overflow Flag - [2:2] - - - OCF4B - Output Compare Flag 4B - [5:5] - - - OCF4A - Output Compare Flag 4A - [6:6] - - - OCF4D - Output Compare Flag 4D - [7:7] - - - - - TIMSK4 - Timer/Counter4 Interrupt Mask Register - 0x39 - - - TOIE4 - Timer/Counter4 Overflow Interrupt Enable - [2:2] - - - OCIE4B - Timer/Counter4 Output Compare B Match Interrupt Enable - [5:5] - - - OCIE4A - Timer/Counter4 Output Compare A Match Interrupt Enable - [6:6] - - - OCIE4D - Timer/Counter4 Output Compare D Match Interrupt Enable - [7:7] - - - - - - - TWI - Two Wire Serial Interface - 0xB8 - - - TWAMR - TWI (Slave) Address Mask Register - 0x5 - - - TWAM - TWI (Slave) Address Mask Bits - [7:1] - - - 0 - 127 - - - - - - - TWAR - TWI (Slave) Address register - 0x2 - - - TWGCE - TWI General Call Recognition Enable Bit - [0:0] - - - TWA - TWI (Slave) Address register Bits - [7:1] - - - 0 - 127 - - - - - - - TWBR - TWI Bit Rate register - 0x0 - - - 0 - 255 - - - - - TWCR - TWI Control Register - 0x4 - read-write - - - TWIE - TWI Interrupt Enable - [0:0] - - - TWEN - TWI Enable Bit - [2:2] - - - TWWC - TWI Write Collition Flag - [3:3] - read-only - - TWSTO - TWI Stop Condition Bit - [4:4] - - - TWSTA - TWI Start Condition Bit - [5:5] - - - TWEA - TWI Enable Acknowledge Bit - [6:6] - - - TWINT - TWI Interrupt Flag - [7:7] - - - - - TWDR - TWI Data register - 0x3 - - - 0 - 255 - - - - - TWSR - TWI Status Register - 0x1 - - - TWPS - TWI Prescaler - [1:0] - - true - - TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 - - - TWS - TWI Status - [7:3] - read-only - - 0 - 31 - - - - - - - - - USART1 - USART - 0xC8 - - - UBRR1 - USART Baud Rate Register Bytes - 0x4 - 16 - - - 0 - 65535 - - - - - UCSR1A - USART Control and Status Register A - 0x0 - read-write - - - MPCM1 - Multi-processor Communication Mode - [0:0] - - - U2X1 - Double the USART transmission speed - [1:1] - - - UPE1 - Parity Error - [2:2] - read-only - - DOR1 - Data overRun - [3:3] - read-only - - FE1 - Framing Error - [4:4] - read-only - - UDRE1 - USART Data Register Empty - [5:5] - read-only - - TXC1 - USART Transmit Complete - [6:6] - - - RXC1 - USART Receive Complete - [7:7] - read-only - - - - UCSR1B - USART Control and Status Register B - 0x1 - - - TXB81 - Transmit Data Bit 8 - [0:0] - - - RXB81 - Receive Data Bit 8 - [1:1] - read-only - - UCSZ12 - Character Size - [2:2] - - - TXEN1 - Transmitter Enable - [3:3] - - - RXEN1 - Receiver Enable - [4:4] - - - UDRIE1 - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE1 - TX Complete Interrupt Enable - [6:6] - - - RXCIE1 - RX Complete Interrupt Enable - [7:7] - - - - - UCSR1C - USART Control and Status Register C - 0x2 - - - UCPOL1 - Clock Polarity - [0:0] - UCPOL1read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 - - - UCSZ1 - Character Size - [2:1] - - - 0 - 3 - - - UCSZ1read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 - - - USBS1 - Stop Bit Select - [3:3] - - true - - USBS1read-writeSTOP11-bit0STOP22-bit1 - - - UPM1 - Parity Mode Bits - [5:4] - - true - - UPM1read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 - - - UMSEL1 - USART Mode Select - [7:6] - - true - - UMSEL1read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 - - - - - UCSR1D - USART Control and Status Register D - 0x3 - - - RTSEN - RTS Enable - [0:0] - - - CTSEN - CTS Enable - [1:1] - - - - - UDR1 - USART I/O Data Register - 0x6 - - - 0 - 255 - - - - - - - USB_DEVICE - USB Device Registers - 0xD7 - - - UDADDR - <TBD> - 0xC - - - UADD - <TBD> - [6:0] - - - 0 - 127 - - - - - ADDEN - <TBD> - [7:7] - - - - - UDCON - <TBD> - 0x9 - - - DETACH - <TBD> - [0:0] - - - RMWKUP - <TBD> - [1:1] - - - LSM - USB low speed mode - [2:2] - - - RSTCPU - <TBD> - [3:3] - - - - - UDFNUM - <TBD> - 0xD - 16 - - - 0 - 65535 - - - - - UDIEN - <TBD> - 0xB - - - SUSPE - <TBD> - [0:0] - - - SOFE - <TBD> - [2:2] - - - EORSTE - <TBD> - [3:3] - - - WAKEUPE - <TBD> - [4:4] - - - EORSME - <TBD> - [5:5] - - - UPRSME - <TBD> - [6:6] - - - - - UDINT - <TBD> - 0xA - - - SUSPI - <TBD> - [0:0] - - - SOFI - <TBD> - [2:2] - - - EORSTI - <TBD> - [3:3] - - - WAKEUPI - <TBD> - [4:4] - - - EORSMI - <TBD> - [5:5] - - - UPRSMI - <TBD> - [6:6] - - - - - UDMFN - <TBD> - 0xF - read-only - - - FNCERR - <TBD> - [4:4] - - - - - UEBCHX - <TBD> - 0x1C - read-only - - - 0 - 255 - - - - - UEBCLX - <TBD> - 0x1B - read-only - - - 0 - 255 - - - - - UECFG0X - <TBD> - 0x15 - - - EPDIR - <TBD> - [0:0] - - - EPTYPE - <TBD> - [7:6] - - - 0 - 3 - - - - - - - UECFG1X - <TBD> - 0x16 - - - ALLOC - <TBD> - [1:1] - - - EPBK - <TBD> - [3:2] - - - 0 - 3 - - - - - EPSIZE - <TBD> - [6:4] - - - 0 - 7 - - - - - - - UECONX - <TBD> - 0x14 - - - EPEN - <TBD> - [0:0] - - - RSTDT - <TBD> - [3:3] - - - STALLRQC - <TBD> - [4:4] - - - STALLRQ - <TBD> - [5:5] - - - - - UEDATX - <TBD> - 0x1A - - - DAT - <TBD> - [7:0] - - - 0 - 255 - - - - - - - UEIENX - <TBD> - 0x19 - - - TXINE - <TBD> - [0:0] - - - STALLEDE - <TBD> - [1:1] - - - RXOUTE - <TBD> - [2:2] - - - RXSTPE - <TBD> - [3:3] - - - NAKOUTE - <TBD> - [4:4] - - - NAKINE - <TBD> - [6:6] - - - FLERRE - <TBD> - [7:7] - - - - - UEINT - <TBD> - 0x1D - - - 0 - 255 - - - - - UEINTX - <TBD> - 0x11 - - - TXINI - <TBD> - [0:0] - - - STALLEDI - <TBD> - [1:1] - - - RXOUTI - <TBD> - [2:2] - - - RXSTPI - <TBD> - [3:3] - - - NAKOUTI - <TBD> - [4:4] - - - RWAL - <TBD> - [5:5] - - - NAKINI - <TBD> - [6:6] - - - FIFOCON - <TBD> - [7:7] - - - - - UENUM - <TBD> - 0x12 - - - 0 - 255 - - - - - UERST - <TBD> - 0x13 - - - EPRST - <TBD> - [6:0] - - - 0 - 127 - - - - - - - UESTA0X - <TBD> - 0x17 - - - NBUSYBK - <TBD> - [1:0] - - - 0 - 3 - - - - - DTSEQ - <TBD> - [3:2] - - - 0 - 3 - - - - - UNDERFI - <TBD> - [5:5] - - - OVERFI - <TBD> - [6:6] - - - CFGOK - <TBD> - [7:7] - - - - - UESTA1X - <TBD> - 0x18 - read-only - - - CURRBK - <TBD> - [1:0] - - - 0 - 3 - - - - - CTRLDIR - <TBD> - [2:2] - - - - - UHWCON - <TBD> - 0x0 - - - UVREGE - <TBD> - [0:0] - - - - - USBCON - USB General Control Register - 0x1 - - - VBUSTE - <TBD> - [0:0] - - - OTGPADE - <TBD> - [4:4] - - - FRZCLK - <TBD> - [5:5] - - - USBE - <TBD> - [7:7] - - - - - USBINT - <TBD> - 0x3 - - - VBUSTI - <TBD> - [0:0] - - - - - USBSTA - <TBD> - 0x2 - read-only - - - VBUS - <TBD> - [0:0] - - - SPEED - <TBD> - [3:3] - - - - - - - WDT - Watchdog Timer - 0x60 - - - WDTCSR - Watchdog Timer Control Register - 0x0 - read-write - - - WDE - Watch Dog Enable - [3:3] - - - WDCE - Watchdog Change Enable - [4:4] - - - WDIE - Watchdog Timeout Interrupt Enable - [6:6] - - - WDIF - Watchdog Timeout Interrupt Flag - [7:7] - - WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 - - WDPHWatchdog Timer Prescaler - High Bit[5:5] - - - - - - \ No newline at end of file diff --git a/misc/svd/atmega4809.svd b/misc/svd/atmega4809.svd deleted file mode 100644 index cfba676..0000000 --- a/misc/svd/atmega4809.svd +++ /dev/null @@ -1,18369 +0,0 @@ - - Atmel - ATmega4809 - 8 - 8 - read-write - 0 - 0xff - - - AC0 - Analog Comparator - 0x680 - - - CTRLA - Control A - 0x0 - - - ENABLE - Enable - [0:0] - - - HYSMODE - Hysteresis Mode - [2:1] - - true - - - - OFF - No hysteresis - 0 - - - 10mV - 10mV hysteresis - 1 - - - 25mV - 25mV hysteresis - 2 - - - 50mV - 50mV hysteresis - 3 - - - - - LPMODE - Low Power Mode - [3:3] - - true - - - - DIS - Low power mode disabled - 0 - - - EN - Low power mode enabled - 1 - - - - - INTMODE - Interrupt Mode - [5:4] - - true - - - - BOTHEDGE - Any Edge - 0 - - - NEGEDGE - Negative Edge - 2 - - - POSEDGE - Positive Edge - 3 - - - - - OUTEN - Output Buffer Enable - [6:6] - - - RUNSTDBY - Run in Standby Mode - [7:7] - - - - - DACREF - Referance scale control - 0x4 - - - DATA - DAC voltage reference - [7:0] - - - 0 - 255 - - - - - - - INTCTRL - Interrupt Control - 0x6 - - - CMP - Analog Comparator 0 Interrupt Enable - [0:0] - - - - - MUXCTRLA - Mux Control A - 0x2 - - - MUXNEG - Negative Input MUX Selection - [1:0] - - true - - - - PIN0 - Negative Pin 0 - 0 - - - PIN1 - Negative Pin 1 - 1 - - - PIN2 - Negative Pin 2 - 2 - - - DACREF - DAC Voltage Reference - 3 - - - - - MUXPOS - Positive Input MUX Selection - [4:3] - - true - - - - PIN0 - Positive Pin 0 - 0 - - - PIN1 - Positive Pin 1 - 1 - - - PIN2 - Positive Pin 2 - 2 - - - PIN3 - Positive Pin 3 - 3 - - - - - INVERT - Invert AC Output - [7:7] - - - - - STATUS - Status - 0x7 - - - CMP - Analog Comparator Interrupt Flag - [0:0] - - - STATE - Analog Comparator State - [4:4] - read-only - - - - - - - ADC0 - Analog to Digital Converter - 0x600 - - - CALIB - Calibration - 0x16 - - - DUTYCYC - Duty Cycle - [0:0] - - true - - - - DUTY50 - 50% Duty cycle - 0 - - - DUTY25 - 25% Duty cycle - 1 - - - - - - - COMMAND - Command - 0x8 - - - STCONV - Start Conversion Operation - [0:0] - - - - - CTRLA - Control A - 0x0 - - - ENABLE - ADC Enable - [0:0] - - - FREERUN - ADC Freerun mode - [1:1] - - - RESSEL - ADC Resolution - [2:2] - - true - - - - 10BIT - 10-bit mode - 0 - - - 8BIT - 8-bit mode - 1 - - - - - RUNSTBY - Run standby mode - [7:7] - - - - - CTRLB - Control B - 0x1 - - - SAMPNUM - Accumulation Samples - [2:0] - - true - - - - ACC1 - 1 ADC sample - 0 - - - ACC2 - Accumulate 2 samples - 1 - - - ACC4 - Accumulate 4 samples - 2 - - - ACC8 - Accumulate 8 samples - 3 - - - ACC16 - Accumulate 16 samples - 4 - - - ACC32 - Accumulate 32 samples - 5 - - - ACC64 - Accumulate 64 samples - 6 - - - - - - - CTRLC - Control C - 0x2 - - - PRESC - Clock Pre-scaler - [2:0] - - true - - - - DIV2 - CLK_PER divided by 2 - 0 - - - DIV4 - CLK_PER divided by 4 - 1 - - - DIV8 - CLK_PER divided by 8 - 2 - - - DIV16 - CLK_PER divided by 16 - 3 - - - DIV32 - CLK_PER divided by 32 - 4 - - - DIV64 - CLK_PER divided by 64 - 5 - - - DIV128 - CLK_PER divided by 128 - 6 - - - DIV256 - CLK_PER divided by 256 - 7 - - - - - REFSEL - Reference Selection - [5:4] - - true - - - - INTREF - Internal reference - 0 - - - VDDREF - VDD - 1 - - - VREFA - External reference - 2 - - - - - SAMPCAP - Sample Capacitance Selection - [6:6] - - - - - CTRLD - Control D - 0x3 - - - SAMPDLY - Sampling Delay Selection - [3:0] - - - 0 - 15 - - - - - ASDV - Automatic Sampling Delay Variation - [4:4] - - true - - - - ASVOFF - The Automatic Sampling Delay Variation is disabled - 0 - - - ASVON - The Automatic Sampling Delay Variation is enabled - 1 - - - - - INITDLY - Initial Delay Selection - [7:5] - - true - - - - DLY0 - Delay 0 CLK_ADC cycles - 0 - - - DLY16 - Delay 16 CLK_ADC cycles - 1 - - - DLY32 - Delay 32 CLK_ADC cycles - 2 - - - DLY64 - Delay 64 CLK_ADC cycles - 3 - - - DLY128 - Delay 128 CLK_ADC cycles - 4 - - - DLY256 - Delay 256 CLK_ADC cycles - 5 - - - - - - - CTRLE - Control E - 0x4 - - - WINCM - Window Comparator Mode - [2:0] - - true - - - - NONE - No Window Comparison - 0 - - - BELOW - Below Window - 1 - - - ABOVE - Above Window - 2 - - - INSIDE - Inside Window - 3 - - - OUTSIDE - Outside Window - 4 - - - - - - - DBGCTRL - Debug Control - 0xC - - - DBGRUN - Debug run - [0:0] - - - - - EVCTRL - Event Control - 0x9 - - - STARTEI - Start Event Input Enable - [0:0] - - - - - INTCTRL - Interrupt Control - 0xA - - - RESRDY - Result Ready Interrupt Enable - [0:0] - - - WCMP - Window Comparator Interrupt Enable - [1:1] - - - - - INTFLAGS - Interrupt Flags - 0xB - - - RESRDY - Result Ready Flag - [0:0] - - - WCMP - Window Comparator Flag - [1:1] - - - - - MUXPOS - Positive mux input - 0x6 - - - MUXPOS - Analog Channel Selection Bits - [4:0] - - true - - - - AIN0 - ADC input pin 0 - 0 - - - AIN1 - ADC input pin 1 - 1 - - - AIN2 - ADC input pin 2 - 2 - - - AIN3 - ADC input pin 3 - 3 - - - AIN4 - ADC input pin 4 - 4 - - - AIN5 - ADC input pin 5 - 5 - - - AIN6 - ADC input pin 6 - 6 - - - AIN7 - ADC input pin 7 - 7 - - - AIN8 - ADC input pin 8 - 8 - - - AIN9 - ADC input pin 9 - 9 - - - AIN10 - ADC input pin 10 - 10 - - - AIN11 - ADC input pin 11 - 11 - - - AIN12 - ADC input pin 12 - 12 - - - AIN13 - ADC input pin 13 - 13 - - - AIN14 - ADC input pin 14 - 14 - - - AIN15 - ADC input pin 15 - 15 - - - DACREF - AC DAC Reference - 28 - - - TEMPSENSE - Temperature sensor - 30 - - - GND - 0V (GND) - 31 - - - - - - - RES - ADC Accumulator Result - 0x10 - 16 - - - 0 - 65535 - - - - - SAMPCTRL - Sample Control - 0x5 - - - SAMPLEN - Sample lenght - [4:0] - - - 0 - 31 - - - - - - - TEMP - Temporary Data - 0xD - - - TEMP - Temporary - [7:0] - - - 0 - 255 - - - - - - - WINHT - Window comparator high threshold - 0x14 - 16 - - - 0 - 65535 - - - - - WINLT - Window comparator low threshold - 0x12 - 16 - - - 0 - 65535 - - - - - - - BOD - Bod interface - 0x80 - - - CTRLA - Control A - 0x0 - - - SLEEP - Operation in sleep mode - [1:0] - - true - - - - DIS - Disabled - 0 - - - ENABLED - Enabled - 1 - - - SAMPLED - Sampled - 2 - - - - - ACTIVE - Operation in active mode - [3:2] - read-only - - true - - - - DIS - Disabled - 0 - - - ENABLED - Enabled - 1 - - - SAMPLED - Sampled - 2 - - - ENWAKE - Enabled with wake-up halted until BOD is ready - 3 - - - - - SAMPFREQ - Sample frequency - [4:4] - read-only - - true - - - - 1KHZ - 1kHz sampling frequency - 0 - - - 125HZ - 125Hz sampling frequency - 1 - - - - - - - CTRLB - Control B - 0x1 - - - LVL - Bod level - [2:0] - read-only - - true - - - - BODLEVEL0 - 1.8 V - 0 - - - BODLEVEL2 - 2.6 V - 2 - - - BODLEVEL7 - 4.2 V - 7 - - - - - - - INTCTRL - Voltage level monitor interrupt Control - 0x9 - - - VLMIE - voltage level monitor interrrupt enable - [0:0] - - - VLMCFG - Configuration - [2:1] - - true - - - - BELOW - Interrupt when supply goes below VLM level - 0 - - - ABOVE - Interrupt when supply goes above VLM level - 1 - - - CROSS - Interrupt when supply crosses VLM level - 2 - - - - - - - INTFLAGS - Voltage level monitor interrupt Flags - 0xA - - - VLMIF - Voltage level monitor interrupt flag - [0:0] - - - - - STATUS - Voltage level monitor status - 0xB - - - VLMS - Voltage level monitor status - [0:0] - read-only - - - - - VLMCTRLA - Voltage level monitor Control - 0x8 - - - VLMLVL - voltage level monitor level - [1:0] - - true - - - - 5ABOVE - VLM threshold 5% above BOD level - 0 - - - 15ABOVE - VLM threshold 15% above BOD level - 1 - - - 25ABOVE - VLM threshold 25% above BOD level - 2 - - - - - - - - - CCL - Configurable Custom Logic - 0x1C0 - - - CTRLA - Control Register A - 0x0 - - - ENABLE - Enable - [0:0] - - - RUNSTDBY - Run in Standby - [6:6] - - - - - INTCTRL0 - Interrupt Control 0 - 0x5 - - - INTMODE0 - Interrupt Mode for LUT0 - [1:0] - - true - - - - INTDISABLE - Interrupt disabled - 0 - - - RISING - Sense rising edge - 1 - - - FALLING - Sense falling edge - 2 - - - BOTH - Sense both edges - 3 - - - - - INTMODE1 - Interrupt Mode for LUT1 - [3:2] - - true - - - - INTDISABLE - Interrupt disabled - 0 - - - RISING - Sense rising edge - 1 - - - FALLING - Sense falling edge - 2 - - - BOTH - Sense both edges - 3 - - - - - INTMODE2 - Interrupt Mode for LUT2 - [5:4] - - true - - - - INTDISABLE - Interrupt disabled - 0 - - - RISING - Sense rising edge - 1 - - - FALLING - Sense falling edge - 2 - - - BOTH - Sense both edges - 3 - - - - - INTMODE3 - Interrupt Mode for LUT3 - [7:6] - - true - - - - INTDISABLE - Interrupt disabled - 0 - - - RISING - Sense rising edge - 1 - - - FALLING - Sense falling edge - 2 - - - BOTH - Sense both edges - 3 - - - - - - - INTFLAGS - Interrupt Flags - 0x7 - - - INT - Interrupt Flags - [3:0] - - - 0 - 15 - - - - - - - LUT0CTRLA - LUT Control 0 A - 0x8 - - - ENABLE - LUT Enable - [0:0] - - - CLKSRC - Clock Source Selection - [3:1] - - true - - - - CLKPER - CLK_PER is clocking the LUT - 0 - - - IN2 - IN[2] is clocking the LUT - 1 - - - OSC20M - 20MHz oscillator before prescaler is clocking the LUT - 4 - - - OSCULP32K - 32kHz oscillator is clocking the LUT - 5 - - - OSCULP1K - 32kHz oscillator after DIV32 is clocking the LUT - 6 - - - - - FILTSEL - Filter Selection - [5:4] - - true - - - - DISABLE - Filter disabled - 0 - - - SYNCH - Synchronizer enabled - 1 - - - FILTER - Filter enabled - 2 - - - - - OUTEN - Output Enable - [6:6] - - - EDGEDET - Edge Detection Enable - [7:7] - - true - - - - DIS - Edge detector is disabled - 0 - - - EN - Edge detector is enabled - 1 - - - - - - - LUT0CTRLB - LUT Control 0 B - 0x9 - - - INSEL0 - LUT Input 0 Source Selection - [3:0] - - true - - - - MASK - Masked input - 0 - - - FEEDBACK - Feedback input source - 1 - - - LINK - Linked LUT input source - 2 - - - EVENTA - Event input source A - 3 - - - EVENTB - Event input source B - 4 - - - IO - IO pin LUTn-IN0 input source - 5 - - - AC0 - AC0 OUT input source - 6 - - - USART0 - USART0 TXD input source - 8 - - - SPI0 - SPI0 MOSI input source - 9 - - - TCA0 - TCA0 WO0 input source - 10 - - - TCB0 - TCB0 WO input source - 12 - - - - - INSEL1 - LUT Input 1 Source Selection - [7:4] - - true - - - - MASK - Masked input - 0 - - - FEEDBACK - Feedback input source - 1 - - - LINK - Linked LUT input source - 2 - - - EVENTA - Event input source A - 3 - - - EVENTB - Event input source B - 4 - - - IO - IO pin LUTn-N1 input source - 5 - - - AC0 - AC0 OUT input source - 6 - - - USART1 - USART1 TXD input source - 8 - - - SPI0 - SPI0 MOSI input source - 9 - - - TCA0 - TCA0 WO1 input source - 10 - - - TCB1 - TCB1 WO input source - 12 - - - - - - - LUT0CTRLC - LUT Control 0 C - 0xA - - - INSEL2 - LUT Input 2 Source Selection - [3:0] - - true - - - - MASK - Masked input - 0 - - - FEEDBACK - Feedback input source - 1 - - - LINK - Linked LUT input source - 2 - - - EVENTA - Event input source A - 3 - - - EVENTB - Event input source B - 4 - - - IO - IO pin LUTn-IN2 input source - 5 - - - AC0 - AC0 OUT input source - 6 - - - USART2 - USART2 TXD input source - 8 - - - SPI0 - SPI0 SCK input source - 9 - - - TCA0 - TCA0 WO2 input source - 10 - - - TCB2 - TCB2 WO input source - 12 - - - - - - - LUT1CTRLA - LUT Control 1 A - 0xC - - - ENABLE - LUT Enable - [0:0] - - - CLKSRC - Clock Source Selection - [3:1] - - true - - - - CLKPER - CLK_PER is clocking the LUT - 0 - - - IN2 - IN[2] is clocking the LUT - 1 - - - OSC20M - 20MHz oscillator before prescaler is clocking the LUT - 4 - - - OSCULP32K - 32kHz oscillator is clocking the LUT - 5 - - - OSCULP1K - 32kHz oscillator after DIV32 is clocking the LUT - 6 - - - - - FILTSEL - Filter Selection - [5:4] - - true - - - - DISABLE - Filter disabled - 0 - - - SYNCH - Synchronizer enabled - 1 - - - FILTER - Filter enabled - 2 - - - - - OUTEN - Output Enable - [6:6] - - - EDGEDET - Edge Detection Enable - [7:7] - - true - - - - DIS - Edge detector is disabled - 0 - - - EN - Edge detector is enabled - 1 - - - - - - - LUT1CTRLB - LUT Control 1 B - 0xD - - - INSEL0 - LUT Input 0 Source Selection - [3:0] - - true - - - - MASK - Masked input - 0 - - - FEEDBACK - Feedback input source - 1 - - - LINK - Linked LUT input source - 2 - - - EVENTA - Event input source A - 3 - - - EVENTB - Event input source B - 4 - - - IO - IO pin LUTn-IN0 input source - 5 - - - AC0 - AC0 OUT input source - 6 - - - USART0 - USART0 TXD input source - 8 - - - SPI0 - SPI0 MOSI input source - 9 - - - TCA0 - TCA0 WO0 input source - 10 - - - TCB0 - TCB0 WO input source - 12 - - - - - INSEL1 - LUT Input 1 Source Selection - [7:4] - - true - - - - MASK - Masked input - 0 - - - FEEDBACK - Feedback input source - 1 - - - LINK - Linked LUT input source - 2 - - - EVENTA - Event input source A - 3 - - - EVENTB - Event input source B - 4 - - - IO - IO pin LUTn-N1 input source - 5 - - - AC0 - AC0 OUT input source - 6 - - - USART1 - USART1 TXD input source - 8 - - - SPI0 - SPI0 MOSI input source - 9 - - - TCA0 - TCA0 WO1 input source - 10 - - - TCB1 - TCB1 WO input source - 12 - - - - - - - LUT1CTRLC - LUT Control 1 C - 0xE - - - INSEL2 - LUT Input 2 Source Selection - [3:0] - - true - - - - MASK - Masked input - 0 - - - FEEDBACK - Feedback input source - 1 - - - LINK - Linked LUT input source - 2 - - - EVENTA - Event input source A - 3 - - - EVENTB - Event input source B - 4 - - - IO - IO pin LUTn-IN2 input source - 5 - - - AC0 - AC0 OUT input source - 6 - - - USART2 - USART2 TXD input source - 8 - - - SPI0 - SPI0 SCK input source - 9 - - - TCA0 - TCA0 WO2 input source - 10 - - - TCB2 - TCB2 WO input source - 12 - - - - - - - LUT2CTRLA - LUT Control 2 A - 0x10 - - - ENABLE - LUT Enable - [0:0] - - - CLKSRC - Clock Source Selection - [3:1] - - true - - - - CLKPER - CLK_PER is clocking the LUT - 0 - - - IN2 - IN[2] is clocking the LUT - 1 - - - OSC20M - 20MHz oscillator before prescaler is clocking the LUT - 4 - - - OSCULP32K - 32kHz oscillator is clocking the LUT - 5 - - - OSCULP1K - 32kHz oscillator after DIV32 is clocking the LUT - 6 - - - - - FILTSEL - Filter Selection - [5:4] - - true - - - - DISABLE - Filter disabled - 0 - - - SYNCH - Synchronizer enabled - 1 - - - FILTER - Filter enabled - 2 - - - - - OUTEN - Output Enable - [6:6] - - - EDGEDET - Edge Detection Enable - [7:7] - - true - - - - DIS - Edge detector is disabled - 0 - - - EN - Edge detector is enabled - 1 - - - - - - - LUT2CTRLB - LUT Control 2 B - 0x11 - - - INSEL0 - LUT Input 0 Source Selection - [3:0] - - true - - - - MASK - Masked input - 0 - - - FEEDBACK - Feedback input source - 1 - - - LINK - Linked LUT input source - 2 - - - EVENTA - Event input source A - 3 - - - EVENTB - Event input source B - 4 - - - IO - IO pin LUTn-IN0 input source - 5 - - - AC0 - AC0 OUT input source - 6 - - - USART0 - USART0 TXD input source - 8 - - - SPI0 - SPI0 MOSI input source - 9 - - - TCA0 - TCA0 WO0 input source - 10 - - - TCB0 - TCB0 WO input source - 12 - - - - - INSEL1 - LUT Input 1 Source Selection - [7:4] - - true - - - - MASK - Masked input - 0 - - - FEEDBACK - Feedback input source - 1 - - - LINK - Linked LUT input source - 2 - - - EVENTA - Event input source A - 3 - - - EVENTB - Event input source B - 4 - - - IO - IO pin LUTn-N1 input source - 5 - - - AC0 - AC0 OUT input source - 6 - - - USART1 - USART1 TXD input source - 8 - - - SPI0 - SPI0 MOSI input source - 9 - - - TCA0 - TCA0 WO1 input source - 10 - - - TCB1 - TCB1 WO input source - 12 - - - - - - - LUT2CTRLC - LUT Control 2 C - 0x12 - - - INSEL2 - LUT Input 2 Source Selection - [3:0] - - true - - - - MASK - Masked input - 0 - - - FEEDBACK - Feedback input source - 1 - - - LINK - Linked LUT input source - 2 - - - EVENTA - Event input source A - 3 - - - EVENTB - Event input source B - 4 - - - IO - IO pin LUTn-IN2 input source - 5 - - - AC0 - AC0 OUT input source - 6 - - - USART2 - USART2 TXD input source - 8 - - - SPI0 - SPI0 SCK input source - 9 - - - TCA0 - TCA0 WO2 input source - 10 - - - TCB2 - TCB2 WO input source - 12 - - - - - - - LUT3CTRLA - LUT Control 3 A - 0x14 - - - ENABLE - LUT Enable - [0:0] - - - CLKSRC - Clock Source Selection - [3:1] - - true - - - - CLKPER - CLK_PER is clocking the LUT - 0 - - - IN2 - IN[2] is clocking the LUT - 1 - - - OSC20M - 20MHz oscillator before prescaler is clocking the LUT - 4 - - - OSCULP32K - 32kHz oscillator is clocking the LUT - 5 - - - OSCULP1K - 32kHz oscillator after DIV32 is clocking the LUT - 6 - - - - - FILTSEL - Filter Selection - [5:4] - - true - - - - DISABLE - Filter disabled - 0 - - - SYNCH - Synchronizer enabled - 1 - - - FILTER - Filter enabled - 2 - - - - - OUTEN - Output Enable - [6:6] - - - EDGEDET - Edge Detection Enable - [7:7] - - true - - - - DIS - Edge detector is disabled - 0 - - - EN - Edge detector is enabled - 1 - - - - - - - LUT3CTRLB - LUT Control 3 B - 0x15 - - - INSEL0 - LUT Input 0 Source Selection - [3:0] - - true - - - - MASK - Masked input - 0 - - - FEEDBACK - Feedback input source - 1 - - - LINK - Linked LUT input source - 2 - - - EVENTA - Event input source A - 3 - - - EVENTB - Event input source B - 4 - - - IO - IO pin LUTn-IN0 input source - 5 - - - AC0 - AC0 OUT input source - 6 - - - USART0 - USART0 TXD input source - 8 - - - SPI0 - SPI0 MOSI input source - 9 - - - TCA0 - TCA0 WO0 input source - 10 - - - TCB0 - TCB0 WO input source - 12 - - - - - INSEL1 - LUT Input 1 Source Selection - [7:4] - - true - - - - MASK - Masked input - 0 - - - FEEDBACK - Feedback input source - 1 - - - LINK - Linked LUT input source - 2 - - - EVENTA - Event input source A - 3 - - - EVENTB - Event input source B - 4 - - - IO - IO pin LUTn-N1 input source - 5 - - - AC0 - AC0 OUT input source - 6 - - - USART1 - USART1 TXD input source - 8 - - - SPI0 - SPI0 MOSI input source - 9 - - - TCA0 - TCA0 WO1 input source - 10 - - - TCB1 - TCB1 WO input source - 12 - - - - - - - LUT3CTRLC - LUT Control 3 C - 0x16 - - - INSEL2 - LUT Input 2 Source Selection - [3:0] - - true - - - - MASK - Masked input - 0 - - - FEEDBACK - Feedback input source - 1 - - - LINK - Linked LUT input source - 2 - - - EVENTA - Event input source A - 3 - - - EVENTB - Event input source B - 4 - - - IO - IO pin LUTn-IN2 input source - 5 - - - AC0 - AC0 OUT input source - 6 - - - USART2 - USART2 TXD input source - 8 - - - SPI0 - SPI0 SCK input source - 9 - - - TCA0 - TCA0 WO2 input source - 10 - - - TCB2 - TCB2 WO input source - 12 - - - - - - - SEQCTRL0 - Sequential Control 0 - 0x1 - - - SEQSEL0 - Sequential Selection - [2:0] - - true - - - - DISABLE - Sequential logic disabled - 0 - - - DFF - D FlipFlop - 1 - - - JK - JK FlipFlop - 2 - - - LATCH - D Latch - 3 - - - RS - RS Latch - 4 - - - - - - - SEQCTRL1 - Sequential Control 1 - 0x2 - - - SEQSEL1 - Sequential Selection - [2:0] - - true - - - - DISABLE - Sequential logic disabled - 0 - - - DFF - D FlipFlop - 1 - - - JK - JK FlipFlop - 2 - - - LATCH - D Latch - 3 - - - RS - RS Latch - 4 - - - - - - - TRUTH0 - Truth 0 - 0xB - - - 0 - 255 - - - - - TRUTH1 - Truth 1 - 0xF - - - 0 - 255 - - - - - TRUTH2 - Truth 2 - 0x13 - - - 0 - 255 - - - - - TRUTH3 - Truth 3 - 0x17 - - - 0 - 255 - - - - - - - CLKCTRL - Clock controller - 0x60 - - - MCLKCTRLA - MCLK Control A - 0x0 - - - CLKSEL - clock select - [1:0] - - true - - - - OSC20M - 20MHz oscillator - 0 - - - OSCULP32K - 32KHz oscillator - 1 - - - XOSC32K - 32.768kHz crystal oscillator - 2 - - - EXTCLK - External clock - 3 - - - - - CLKOUT - System clock out - [7:7] - - - - - MCLKCTRLB - MCLK Control B - 0x1 - - - PEN - Prescaler enable - [0:0] - - - PDIV - Prescaler division - [4:1] - - true - - - - 2X - 2X - 0 - - - 4X - 4X - 1 - - - 8X - 8X - 2 - - - 16X - 16X - 3 - - - 32X - 32X - 4 - - - 64X - 64X - 5 - - - 6X - 6X - 8 - - - 10X - 10X - 9 - - - 12X - 12X - 10 - - - 24X - 24X - 11 - - - 48X - 48X - 12 - - - - - - - MCLKLOCK - MCLK Lock - 0x2 - - - LOCKEN - lock ebable - [0:0] - - - - - MCLKSTATUS - MCLK Status - 0x3 - - - SOSC - System Oscillator changing - [0:0] - read-only - - - OSC20MS - 20MHz oscillator status - [4:4] - read-only - - - OSC32KS - 32KHz oscillator status - [5:5] - read-only - - - XOSC32KS - 32.768 kHz Crystal Oscillator status - [6:6] - read-only - - - EXTS - External Clock status - [7:7] - read-only - - - - - OSC20MCALIBA - OSC20M Calibration A - 0x11 - - - CAL20M - Calibration - [6:0] - - - 0 - 127 - - - - - - - OSC20MCALIBB - OSC20M Calibration B - 0x12 - - - TEMPCAL20M - Oscillator temperature coefficient - [3:0] - - - 0 - 15 - - - - - LOCK - Lock - [7:7] - - - - - OSC20MCTRLA - OSC20M Control A - 0x10 - - - RUNSTDBY - Run standby - [1:1] - - - - - OSC32KCTRLA - OSC32K Control A - 0x18 - - - RUNSTDBY - Run standby - [1:1] - - - - - XOSC32KCTRLA - XOSC32K Control A - 0x1C - - - ENABLE - Enable - [0:0] - - - RUNSTDBY - Run standby - [1:1] - - - SEL - Select - [2:2] - - - CSUT - Crystal startup time - [5:4] - - true - - - - 1K - 1k cycles - 0 - - - 16K - 16k cycles - 1 - - - 32K - 32k cycles - 2 - - - 64K - 64k cycles - 3 - - - - - - - - - CPU - CPU - 0x34 - - CRCSCAN_NMI - <TBD> - 1 - - - BOD_VLM - <TBD> - 2 - - - RTC_CNT - <TBD> - 3 - - - RTC_PIT - <TBD> - 4 - - - CCL_CCL - <TBD> - 5 - - - PORTA_PORT - <TBD> - 6 - - - TCA0_LUNF_OVF - <TBD> - 7 - - - TCA0_HUNF - <TBD> - 8 - - - TCA0_CMP0_LCMP0 - <TBD> - 9 - - - TCA0_CMP1_LCMP1 - <TBD> - 10 - - - TCA0_CMP2_LCMP2 - <TBD> - 11 - - - TCB0_INT - <TBD> - 12 - - - TCB1_INT - <TBD> - 13 - - - TWI0_TWIS - <TBD> - 14 - - - TWI0_TWIM - <TBD> - 15 - - - SPI0_INT - <TBD> - 16 - - - USART0_RXC - <TBD> - 17 - - - USART0_DRE - <TBD> - 18 - - - USART0_TXC - <TBD> - 19 - - - PORTD_PORT - <TBD> - 20 - - - AC0_AC - <TBD> - 21 - - - ADC0_RESRDY - <TBD> - 22 - - - ADC0_WCOMP - <TBD> - 23 - - - PORTC_PORT - <TBD> - 24 - - - TCB2_INT - <TBD> - 25 - - - USART1_RXC - <TBD> - 26 - - - USART1_DRE - <TBD> - 27 - - - USART1_TXC - <TBD> - 28 - - - PORTF_PORT - <TBD> - 29 - - - NVMCTRL_EE - <TBD> - 30 - - - USART2_RXC - <TBD> - 31 - - - USART2_DRE - <TBD> - 32 - - - USART2_TXC - <TBD> - 33 - - - PORTB_PORT - <TBD> - 34 - - - PORTE_PORT - <TBD> - 35 - - - TCB3_INT - <TBD> - 36 - - - USART3_RXC - <TBD> - 37 - - - USART3_DRE - <TBD> - 38 - - - USART3_TXC - <TBD> - 39 - - - - CCP - Configuration Change Protection - 0x0 - - - CCP - CCP signature - [7:0] - - true - - - - SPM - SPM Instruction Protection - 157 - - - IOREG - IO Register Protection - 216 - - - - - - - SPH - Stack Pointer High - 0xA - - - 0 - 255 - - - - - SPL - Stack Pointer Low - 0x9 - - - 0 - 255 - - - - - - - CPUINT - Interrupt Controller - 0x110 - - - CTRLA - Control A - 0x0 - - - LVL0RR - Round-robin Scheduling Enable - [0:0] - - - CVT - Compact Vector Table - [5:5] - - - IVSEL - Interrupt Vector Select - [6:6] - - - - - LVL0PRI - Interrupt Level 0 Priority - 0x2 - - - LVL0PRI - Interrupt Level Priority - [7:0] - - - 0 - 255 - - - - - - - LVL1VEC - Interrupt Level 1 Priority Vector - 0x3 - - - LVL1VEC - Interrupt Vector with High Priority - [7:0] - - - 0 - 255 - - - - - - - STATUS - Status - 0x1 - - - LVL0EX - Level 0 Interrupt Executing - [0:0] - read-only - - - LVL1EX - Level 1 Interrupt Executing - [1:1] - read-only - - - NMIEX - Non-maskable Interrupt Executing - [7:7] - read-only - - - - - - - CRCSCAN - CRCSCAN - 0x120 - - - CTRLA - Control A - 0x0 - - - ENABLE - Enable CRC scan - [0:0] - - - NMIEN - Enable NMI Trigger - [1:1] - - - RESET - Reset CRC scan - [7:7] - - - - - CTRLB - Control B - 0x1 - - - SRC - CRC Source - [1:0] - - true - - - - FLASH - CRC on entire flash - 0 - - - APPLICATION - CRC on boot and appl section of flash - 1 - - - BOOT - CRC on boot section of flash - 2 - - - - - - - STATUS - Status - 0x2 - - - BUSY - CRC Busy - [0:0] - read-only - - - OK - CRC Ok - [1:1] - read-only - - - - - - - EVSYS - Event System - 0x180 - - - CHANNEL0 - Multiplexer Channel 0 - 0x10 - - - GENERATOR - Generator selector - [7:0] - - true - - - - OFF - Off - 0 - - - UPDI - Unified Program and Debug Interface - 1 - - - RTC_OVF - Real Time Counter overflow - 6 - - - RTC_CMP - Real Time Counter compare - 7 - - - RTC_PIT0 - Periodic Interrupt Timer output 0 - 8 - - - RTC_PIT1 - Periodic Interrupt Timer output 1 - 9 - - - RTC_PIT2 - Periodic Interrupt Timer output 2 - 10 - - - RTC_PIT3 - Periodic Interrupt Timer output 3 - 11 - - - CCL_LUT0 - Configurable Custom Logic LUT0 - 16 - - - CCL_LUT1 - Configurable Custom Logic LUT1 - 17 - - - CCL_LUT2 - Configurable Custom Logic LUT2 - 18 - - - CCL_LUT3 - Configurable Custom Logic LUT3 - 19 - - - AC0_OUT - Analog Comparator 0 out - 32 - - - ADC0_RESRDY - ADC 0 Result Ready Event - 36 - - - PORT0_PIN0 - Port 0 Pin 0 - 64 - - - PORT0_PIN1 - Port 0 Pin 1 - 65 - - - PORT0_PIN2 - Port 0 Pin 2 - 66 - - - PORT0_PIN3 - Port 0 Pin 3 - 67 - - - PORT0_PIN4 - Port 0 Pin 4 - 68 - - - PORT0_PIN5 - Port 0 Pin 5 - 69 - - - PORT0_PIN6 - Port 0 Pin 6 - 70 - - - PORT0_PIN7 - Port 0 Pin 7 - 71 - - - PORT1_PIN0 - Port 1 Pin 0 - 72 - - - PORT1_PIN1 - Port 1 Pin 1 - 73 - - - PORT1_PIN2 - Port 1 Pin 2 - 74 - - - PORT1_PIN3 - Port 1 Pin 3 - 75 - - - PORT1_PIN4 - Port 1 Pin 4 - 76 - - - PORT1_PIN5 - Port 1 Pin 5 - 77 - - - PORT1_PIN6 - Port 1 Pin 6 - 78 - - - PORT1_PIN7 - Port 1 Pin 7 - 79 - - - USART0_XCK - USART 0 Xclock - 96 - - - USART1_XCK - USART 1 Xclock - 97 - - - USART2_XCK - USART 2 Xclock - 98 - - - USART3_XCK - USART 3 Xclock - 99 - - - SPI0_SCK - SPI 0 Sclock - 104 - - - TCA0_OVF_LUNF - Timer/Counter A0 overflow / low byte underflow - 128 - - - TCA0_HUNF - Timer/Counter A0 high byte underflow (split mode) - 129 - - - TCA0_CMP0 - Timer/Counter A0 compare 0 - 132 - - - TCA0_CMP1 - Timer/Counter A0 compare 1 - 133 - - - TCA0_CMP2 - Timer/Counter A0 compare 2 - 134 - - - TCB0_CAPT - Timer/Counter B0 capture - 160 - - - TCB1_CAPT - Timer/Counter B1 capture - 162 - - - TCB2_CAPT - Timer/Counter B2 capture - 164 - - - TCB3_CAPT - Timer/Counter B3 capture - 166 - - - - - - - CHANNEL1 - Multiplexer Channel 1 - 0x11 - - - GENERATOR - Generator selector - [7:0] - - true - - - - OFF - Off - 0 - - - UPDI - Unified Program and Debug Interface - 1 - - - RTC_OVF - Real Time Counter overflow - 6 - - - RTC_CMP - Real Time Counter compare - 7 - - - RTC_PIT0 - Periodic Interrupt Timer output 0 - 8 - - - RTC_PIT1 - Periodic Interrupt Timer output 1 - 9 - - - RTC_PIT2 - Periodic Interrupt Timer output 2 - 10 - - - RTC_PIT3 - Periodic Interrupt Timer output 3 - 11 - - - CCL_LUT0 - Configurable Custom Logic LUT0 - 16 - - - CCL_LUT1 - Configurable Custom Logic LUT1 - 17 - - - CCL_LUT2 - Configurable Custom Logic LUT2 - 18 - - - CCL_LUT3 - Configurable Custom Logic LUT3 - 19 - - - AC0_OUT - Analog Comparator 0 out - 32 - - - ADC0_RESRDY - ADC 0 Result Ready Event - 36 - - - PORT0_PIN0 - Port 0 Pin 0 - 64 - - - PORT0_PIN1 - Port 0 Pin 1 - 65 - - - PORT0_PIN2 - Port 0 Pin 2 - 66 - - - PORT0_PIN3 - Port 0 Pin 3 - 67 - - - PORT0_PIN4 - Port 0 Pin 4 - 68 - - - PORT0_PIN5 - Port 0 Pin 5 - 69 - - - PORT0_PIN6 - Port 0 Pin 6 - 70 - - - PORT0_PIN7 - Port 0 Pin 7 - 71 - - - PORT1_PIN0 - Port 1 Pin 0 - 72 - - - PORT1_PIN1 - Port 1 Pin 1 - 73 - - - PORT1_PIN2 - Port 1 Pin 2 - 74 - - - PORT1_PIN3 - Port 1 Pin 3 - 75 - - - PORT1_PIN4 - Port 1 Pin 4 - 76 - - - PORT1_PIN5 - Port 1 Pin 5 - 77 - - - PORT1_PIN6 - Port 1 Pin 6 - 78 - - - PORT1_PIN7 - Port 1 Pin 7 - 79 - - - USART0_XCK - USART 0 Xclock - 96 - - - USART1_XCK - USART 1 Xclock - 97 - - - USART2_XCK - USART 2 Xclock - 98 - - - USART3_XCK - USART 3 Xclock - 99 - - - SPI0_SCK - SPI 0 Sclock - 104 - - - TCA0_OVF_LUNF - Timer/Counter A0 overflow / low byte underflow - 128 - - - TCA0_HUNF - Timer/Counter A0 high byte underflow (split mode) - 129 - - - TCA0_CMP0 - Timer/Counter A0 compare 0 - 132 - - - TCA0_CMP1 - Timer/Counter A0 compare 1 - 133 - - - TCA0_CMP2 - Timer/Counter A0 compare 2 - 134 - - - TCB0_CAPT - Timer/Counter B0 capture - 160 - - - TCB1_CAPT - Timer/Counter B1 capture - 162 - - - TCB2_CAPT - Timer/Counter B2 capture - 164 - - - TCB3_CAPT - Timer/Counter B3 capture - 166 - - - - - - - CHANNEL2 - Multiplexer Channel 2 - 0x12 - - - GENERATOR - Generator selector - [7:0] - - true - - - - OFF - Off - 0 - - - UPDI - Unified Program and Debug Interface - 1 - - - RTC_OVF - Real Time Counter overflow - 6 - - - RTC_CMP - Real Time Counter compare - 7 - - - RTC_PIT0 - Periodic Interrupt Timer output 0 - 8 - - - RTC_PIT1 - Periodic Interrupt Timer output 1 - 9 - - - RTC_PIT2 - Periodic Interrupt Timer output 2 - 10 - - - RTC_PIT3 - Periodic Interrupt Timer output 3 - 11 - - - CCL_LUT0 - Configurable Custom Logic LUT0 - 16 - - - CCL_LUT1 - Configurable Custom Logic LUT1 - 17 - - - CCL_LUT2 - Configurable Custom Logic LUT2 - 18 - - - CCL_LUT3 - Configurable Custom Logic LUT3 - 19 - - - AC0_OUT - Analog Comparator 0 out - 32 - - - ADC0_RESRDY - ADC 0 Result Ready Event - 36 - - - PORT0_PIN0 - Port 0 Pin 0 - 64 - - - PORT0_PIN1 - Port 0 Pin 1 - 65 - - - PORT0_PIN2 - Port 0 Pin 2 - 66 - - - PORT0_PIN3 - Port 0 Pin 3 - 67 - - - PORT0_PIN4 - Port 0 Pin 4 - 68 - - - PORT0_PIN5 - Port 0 Pin 5 - 69 - - - PORT0_PIN6 - Port 0 Pin 6 - 70 - - - PORT0_PIN7 - Port 0 Pin 7 - 71 - - - PORT1_PIN0 - Port 1 Pin 0 - 72 - - - PORT1_PIN1 - Port 1 Pin 1 - 73 - - - PORT1_PIN2 - Port 1 Pin 2 - 74 - - - PORT1_PIN3 - Port 1 Pin 3 - 75 - - - PORT1_PIN4 - Port 1 Pin 4 - 76 - - - PORT1_PIN5 - Port 1 Pin 5 - 77 - - - PORT1_PIN6 - Port 1 Pin 6 - 78 - - - PORT1_PIN7 - Port 1 Pin 7 - 79 - - - USART0_XCK - USART 0 Xclock - 96 - - - USART1_XCK - USART 1 Xclock - 97 - - - USART2_XCK - USART 2 Xclock - 98 - - - USART3_XCK - USART 3 Xclock - 99 - - - SPI0_SCK - SPI 0 Sclock - 104 - - - TCA0_OVF_LUNF - Timer/Counter A0 overflow / low byte underflow - 128 - - - TCA0_HUNF - Timer/Counter A0 high byte underflow (split mode) - 129 - - - TCA0_CMP0 - Timer/Counter A0 compare 0 - 132 - - - TCA0_CMP1 - Timer/Counter A0 compare 1 - 133 - - - TCA0_CMP2 - Timer/Counter A0 compare 2 - 134 - - - TCB0_CAPT - Timer/Counter B0 capture - 160 - - - TCB1_CAPT - Timer/Counter B1 capture - 162 - - - TCB2_CAPT - Timer/Counter B2 capture - 164 - - - TCB3_CAPT - Timer/Counter B3 capture - 166 - - - - - - - CHANNEL3 - Multiplexer Channel 3 - 0x13 - - - GENERATOR - Generator selector - [7:0] - - true - - - - OFF - Off - 0 - - - UPDI - Unified Program and Debug Interface - 1 - - - RTC_OVF - Real Time Counter overflow - 6 - - - RTC_CMP - Real Time Counter compare - 7 - - - RTC_PIT0 - Periodic Interrupt Timer output 0 - 8 - - - RTC_PIT1 - Periodic Interrupt Timer output 1 - 9 - - - RTC_PIT2 - Periodic Interrupt Timer output 2 - 10 - - - RTC_PIT3 - Periodic Interrupt Timer output 3 - 11 - - - CCL_LUT0 - Configurable Custom Logic LUT0 - 16 - - - CCL_LUT1 - Configurable Custom Logic LUT1 - 17 - - - CCL_LUT2 - Configurable Custom Logic LUT2 - 18 - - - CCL_LUT3 - Configurable Custom Logic LUT3 - 19 - - - AC0_OUT - Analog Comparator 0 out - 32 - - - ADC0_RESRDY - ADC 0 Result Ready Event - 36 - - - PORT0_PIN0 - Port 0 Pin 0 - 64 - - - PORT0_PIN1 - Port 0 Pin 1 - 65 - - - PORT0_PIN2 - Port 0 Pin 2 - 66 - - - PORT0_PIN3 - Port 0 Pin 3 - 67 - - - PORT0_PIN4 - Port 0 Pin 4 - 68 - - - PORT0_PIN5 - Port 0 Pin 5 - 69 - - - PORT0_PIN6 - Port 0 Pin 6 - 70 - - - PORT0_PIN7 - Port 0 Pin 7 - 71 - - - PORT1_PIN0 - Port 1 Pin 0 - 72 - - - PORT1_PIN1 - Port 1 Pin 1 - 73 - - - PORT1_PIN2 - Port 1 Pin 2 - 74 - - - PORT1_PIN3 - Port 1 Pin 3 - 75 - - - PORT1_PIN4 - Port 1 Pin 4 - 76 - - - PORT1_PIN5 - Port 1 Pin 5 - 77 - - - PORT1_PIN6 - Port 1 Pin 6 - 78 - - - PORT1_PIN7 - Port 1 Pin 7 - 79 - - - USART0_XCK - USART 0 Xclock - 96 - - - USART1_XCK - USART 1 Xclock - 97 - - - USART2_XCK - USART 2 Xclock - 98 - - - USART3_XCK - USART 3 Xclock - 99 - - - SPI0_SCK - SPI 0 Sclock - 104 - - - TCA0_OVF_LUNF - Timer/Counter A0 overflow / low byte underflow - 128 - - - TCA0_HUNF - Timer/Counter A0 high byte underflow (split mode) - 129 - - - TCA0_CMP0 - Timer/Counter A0 compare 0 - 132 - - - TCA0_CMP1 - Timer/Counter A0 compare 1 - 133 - - - TCA0_CMP2 - Timer/Counter A0 compare 2 - 134 - - - TCB0_CAPT - Timer/Counter B0 capture - 160 - - - TCB1_CAPT - Timer/Counter B1 capture - 162 - - - TCB2_CAPT - Timer/Counter B2 capture - 164 - - - TCB3_CAPT - Timer/Counter B3 capture - 166 - - - - - - - CHANNEL4 - Multiplexer Channel 4 - 0x14 - - - GENERATOR - Generator selector - [7:0] - - true - - - - OFF - Off - 0 - - - UPDI - Unified Program and Debug Interface - 1 - - - RTC_OVF - Real Time Counter overflow - 6 - - - RTC_CMP - Real Time Counter compare - 7 - - - RTC_PIT0 - Periodic Interrupt Timer output 0 - 8 - - - RTC_PIT1 - Periodic Interrupt Timer output 1 - 9 - - - RTC_PIT2 - Periodic Interrupt Timer output 2 - 10 - - - RTC_PIT3 - Periodic Interrupt Timer output 3 - 11 - - - CCL_LUT0 - Configurable Custom Logic LUT0 - 16 - - - CCL_LUT1 - Configurable Custom Logic LUT1 - 17 - - - CCL_LUT2 - Configurable Custom Logic LUT2 - 18 - - - CCL_LUT3 - Configurable Custom Logic LUT3 - 19 - - - AC0_OUT - Analog Comparator 0 out - 32 - - - ADC0_RESRDY - ADC 0 Result Ready Event - 36 - - - PORT0_PIN0 - Port 0 Pin 0 - 64 - - - PORT0_PIN1 - Port 0 Pin 1 - 65 - - - PORT0_PIN2 - Port 0 Pin 2 - 66 - - - PORT0_PIN3 - Port 0 Pin 3 - 67 - - - PORT0_PIN4 - Port 0 Pin 4 - 68 - - - PORT0_PIN5 - Port 0 Pin 5 - 69 - - - PORT0_PIN6 - Port 0 Pin 6 - 70 - - - PORT0_PIN7 - Port 0 Pin 7 - 71 - - - PORT1_PIN0 - Port 1 Pin 0 - 72 - - - PORT1_PIN1 - Port 1 Pin 1 - 73 - - - PORT1_PIN2 - Port 1 Pin 2 - 74 - - - PORT1_PIN3 - Port 1 Pin 3 - 75 - - - PORT1_PIN4 - Port 1 Pin 4 - 76 - - - PORT1_PIN5 - Port 1 Pin 5 - 77 - - - PORT1_PIN6 - Port 1 Pin 6 - 78 - - - PORT1_PIN7 - Port 1 Pin 7 - 79 - - - USART0_XCK - USART 0 Xclock - 96 - - - USART1_XCK - USART 1 Xclock - 97 - - - USART2_XCK - USART 2 Xclock - 98 - - - USART3_XCK - USART 3 Xclock - 99 - - - SPI0_SCK - SPI 0 Sclock - 104 - - - TCA0_OVF_LUNF - Timer/Counter A0 overflow / low byte underflow - 128 - - - TCA0_HUNF - Timer/Counter A0 high byte underflow (split mode) - 129 - - - TCA0_CMP0 - Timer/Counter A0 compare 0 - 132 - - - TCA0_CMP1 - Timer/Counter A0 compare 1 - 133 - - - TCA0_CMP2 - Timer/Counter A0 compare 2 - 134 - - - TCB0_CAPT - Timer/Counter B0 capture - 160 - - - TCB1_CAPT - Timer/Counter B1 capture - 162 - - - TCB2_CAPT - Timer/Counter B2 capture - 164 - - - TCB3_CAPT - Timer/Counter B3 capture - 166 - - - - - - - CHANNEL5 - Multiplexer Channel 5 - 0x15 - - - GENERATOR - Generator selector - [7:0] - - true - - - - OFF - Off - 0 - - - UPDI - Unified Program and Debug Interface - 1 - - - RTC_OVF - Real Time Counter overflow - 6 - - - RTC_CMP - Real Time Counter compare - 7 - - - RTC_PIT0 - Periodic Interrupt Timer output 0 - 8 - - - RTC_PIT1 - Periodic Interrupt Timer output 1 - 9 - - - RTC_PIT2 - Periodic Interrupt Timer output 2 - 10 - - - RTC_PIT3 - Periodic Interrupt Timer output 3 - 11 - - - CCL_LUT0 - Configurable Custom Logic LUT0 - 16 - - - CCL_LUT1 - Configurable Custom Logic LUT1 - 17 - - - CCL_LUT2 - Configurable Custom Logic LUT2 - 18 - - - CCL_LUT3 - Configurable Custom Logic LUT3 - 19 - - - AC0_OUT - Analog Comparator 0 out - 32 - - - ADC0_RESRDY - ADC 0 Result Ready Event - 36 - - - PORT0_PIN0 - Port 0 Pin 0 - 64 - - - PORT0_PIN1 - Port 0 Pin 1 - 65 - - - PORT0_PIN2 - Port 0 Pin 2 - 66 - - - PORT0_PIN3 - Port 0 Pin 3 - 67 - - - PORT0_PIN4 - Port 0 Pin 4 - 68 - - - PORT0_PIN5 - Port 0 Pin 5 - 69 - - - PORT0_PIN6 - Port 0 Pin 6 - 70 - - - PORT0_PIN7 - Port 0 Pin 7 - 71 - - - PORT1_PIN0 - Port 1 Pin 0 - 72 - - - PORT1_PIN1 - Port 1 Pin 1 - 73 - - - PORT1_PIN2 - Port 1 Pin 2 - 74 - - - PORT1_PIN3 - Port 1 Pin 3 - 75 - - - PORT1_PIN4 - Port 1 Pin 4 - 76 - - - PORT1_PIN5 - Port 1 Pin 5 - 77 - - - PORT1_PIN6 - Port 1 Pin 6 - 78 - - - PORT1_PIN7 - Port 1 Pin 7 - 79 - - - USART0_XCK - USART 0 Xclock - 96 - - - USART1_XCK - USART 1 Xclock - 97 - - - USART2_XCK - USART 2 Xclock - 98 - - - USART3_XCK - USART 3 Xclock - 99 - - - SPI0_SCK - SPI 0 Sclock - 104 - - - TCA0_OVF_LUNF - Timer/Counter A0 overflow / low byte underflow - 128 - - - TCA0_HUNF - Timer/Counter A0 high byte underflow (split mode) - 129 - - - TCA0_CMP0 - Timer/Counter A0 compare 0 - 132 - - - TCA0_CMP1 - Timer/Counter A0 compare 1 - 133 - - - TCA0_CMP2 - Timer/Counter A0 compare 2 - 134 - - - TCB0_CAPT - Timer/Counter B0 capture - 160 - - - TCB1_CAPT - Timer/Counter B1 capture - 162 - - - TCB2_CAPT - Timer/Counter B2 capture - 164 - - - TCB3_CAPT - Timer/Counter B3 capture - 166 - - - - - - - CHANNEL6 - Multiplexer Channel 6 - 0x16 - - - GENERATOR - Generator selector - [7:0] - - true - - - - OFF - Off - 0 - - - UPDI - Unified Program and Debug Interface - 1 - - - RTC_OVF - Real Time Counter overflow - 6 - - - RTC_CMP - Real Time Counter compare - 7 - - - RTC_PIT0 - Periodic Interrupt Timer output 0 - 8 - - - RTC_PIT1 - Periodic Interrupt Timer output 1 - 9 - - - RTC_PIT2 - Periodic Interrupt Timer output 2 - 10 - - - RTC_PIT3 - Periodic Interrupt Timer output 3 - 11 - - - CCL_LUT0 - Configurable Custom Logic LUT0 - 16 - - - CCL_LUT1 - Configurable Custom Logic LUT1 - 17 - - - CCL_LUT2 - Configurable Custom Logic LUT2 - 18 - - - CCL_LUT3 - Configurable Custom Logic LUT3 - 19 - - - AC0_OUT - Analog Comparator 0 out - 32 - - - ADC0_RESRDY - ADC 0 Result Ready Event - 36 - - - PORT0_PIN0 - Port 0 Pin 0 - 64 - - - PORT0_PIN1 - Port 0 Pin 1 - 65 - - - PORT0_PIN2 - Port 0 Pin 2 - 66 - - - PORT0_PIN3 - Port 0 Pin 3 - 67 - - - PORT0_PIN4 - Port 0 Pin 4 - 68 - - - PORT0_PIN5 - Port 0 Pin 5 - 69 - - - PORT0_PIN6 - Port 0 Pin 6 - 70 - - - PORT0_PIN7 - Port 0 Pin 7 - 71 - - - PORT1_PIN0 - Port 1 Pin 0 - 72 - - - PORT1_PIN1 - Port 1 Pin 1 - 73 - - - PORT1_PIN2 - Port 1 Pin 2 - 74 - - - PORT1_PIN3 - Port 1 Pin 3 - 75 - - - PORT1_PIN4 - Port 1 Pin 4 - 76 - - - PORT1_PIN5 - Port 1 Pin 5 - 77 - - - PORT1_PIN6 - Port 1 Pin 6 - 78 - - - PORT1_PIN7 - Port 1 Pin 7 - 79 - - - USART0_XCK - USART 0 Xclock - 96 - - - USART1_XCK - USART 1 Xclock - 97 - - - USART2_XCK - USART 2 Xclock - 98 - - - USART3_XCK - USART 3 Xclock - 99 - - - SPI0_SCK - SPI 0 Sclock - 104 - - - TCA0_OVF_LUNF - Timer/Counter A0 overflow / low byte underflow - 128 - - - TCA0_HUNF - Timer/Counter A0 high byte underflow (split mode) - 129 - - - TCA0_CMP0 - Timer/Counter A0 compare 0 - 132 - - - TCA0_CMP1 - Timer/Counter A0 compare 1 - 133 - - - TCA0_CMP2 - Timer/Counter A0 compare 2 - 134 - - - TCB0_CAPT - Timer/Counter B0 capture - 160 - - - TCB1_CAPT - Timer/Counter B1 capture - 162 - - - TCB2_CAPT - Timer/Counter B2 capture - 164 - - - TCB3_CAPT - Timer/Counter B3 capture - 166 - - - - - - - CHANNEL7 - Multiplexer Channel 7 - 0x17 - - - GENERATOR - Generator selector - [7:0] - - true - - - - OFF - Off - 0 - - - UPDI - Unified Program and Debug Interface - 1 - - - RTC_OVF - Real Time Counter overflow - 6 - - - RTC_CMP - Real Time Counter compare - 7 - - - RTC_PIT0 - Periodic Interrupt Timer output 0 - 8 - - - RTC_PIT1 - Periodic Interrupt Timer output 1 - 9 - - - RTC_PIT2 - Periodic Interrupt Timer output 2 - 10 - - - RTC_PIT3 - Periodic Interrupt Timer output 3 - 11 - - - CCL_LUT0 - Configurable Custom Logic LUT0 - 16 - - - CCL_LUT1 - Configurable Custom Logic LUT1 - 17 - - - CCL_LUT2 - Configurable Custom Logic LUT2 - 18 - - - CCL_LUT3 - Configurable Custom Logic LUT3 - 19 - - - AC0_OUT - Analog Comparator 0 out - 32 - - - ADC0_RESRDY - ADC 0 Result Ready Event - 36 - - - PORT0_PIN0 - Port 0 Pin 0 - 64 - - - PORT0_PIN1 - Port 0 Pin 1 - 65 - - - PORT0_PIN2 - Port 0 Pin 2 - 66 - - - PORT0_PIN3 - Port 0 Pin 3 - 67 - - - PORT0_PIN4 - Port 0 Pin 4 - 68 - - - PORT0_PIN5 - Port 0 Pin 5 - 69 - - - PORT0_PIN6 - Port 0 Pin 6 - 70 - - - PORT0_PIN7 - Port 0 Pin 7 - 71 - - - PORT1_PIN0 - Port 1 Pin 0 - 72 - - - PORT1_PIN1 - Port 1 Pin 1 - 73 - - - PORT1_PIN2 - Port 1 Pin 2 - 74 - - - PORT1_PIN3 - Port 1 Pin 3 - 75 - - - PORT1_PIN4 - Port 1 Pin 4 - 76 - - - PORT1_PIN5 - Port 1 Pin 5 - 77 - - - PORT1_PIN6 - Port 1 Pin 6 - 78 - - - PORT1_PIN7 - Port 1 Pin 7 - 79 - - - USART0_XCK - USART 0 Xclock - 96 - - - USART1_XCK - USART 1 Xclock - 97 - - - USART2_XCK - USART 2 Xclock - 98 - - - USART3_XCK - USART 3 Xclock - 99 - - - SPI0_SCK - SPI 0 Sclock - 104 - - - TCA0_OVF_LUNF - Timer/Counter A0 overflow / low byte underflow - 128 - - - TCA0_HUNF - Timer/Counter A0 high byte underflow (split mode) - 129 - - - TCA0_CMP0 - Timer/Counter A0 compare 0 - 132 - - - TCA0_CMP1 - Timer/Counter A0 compare 1 - 133 - - - TCA0_CMP2 - Timer/Counter A0 compare 2 - 134 - - - TCB0_CAPT - Timer/Counter B0 capture - 160 - - - TCB1_CAPT - Timer/Counter B1 capture - 162 - - - TCB2_CAPT - Timer/Counter B2 capture - 164 - - - TCB3_CAPT - Timer/Counter B3 capture - 166 - - - - - - - STROBE - Channel Strobe - 0x0 - - - STROBE0 - Software event on channels - [7:0] - write-only - - true - - - - EV_STROBE_CH0 - <TBD> - 1 - - - EV_STROBE_CH1 - <TBD> - 2 - - - EV_STROBE_CH2 - <TBD> - 4 - - - EV_STROBE_CH3 - <TBD> - 8 - - - EV_STROBE_CH4 - <TBD> - 16 - - - EV_STROBE_CH5 - <TBD> - 32 - - - EV_STROBE_CH6 - <TBD> - 64 - - - EV_STROBE_CH7 - <TBD> - 128 - - - - - - - USERADC0 - User ADC0 - 0x28 - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USERCCLLUT0A - User CCL LUT0 Event A - 0x20 - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USERCCLLUT0B - User CCL LUT0 Event B - 0x21 - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USERCCLLUT1A - User CCL LUT1 Event A - 0x22 - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USERCCLLUT1B - User CCL LUT1 Event B - 0x23 - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USERCCLLUT2A - User CCL LUT2 Event A - 0x24 - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USERCCLLUT2B - User CCL LUT2 Event B - 0x25 - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USERCCLLUT3A - User CCL LUT3 Event A - 0x26 - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USERCCLLUT3B - User CCL LUT3 Event B - 0x27 - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USEREVOUTA - User EVOUT Port A - 0x29 - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USEREVOUTB - User EVOUT Port B - 0x2A - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USEREVOUTC - User EVOUT Port C - 0x2B - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USEREVOUTD - User EVOUT Port D - 0x2C - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USEREVOUTE - User EVOUT Port E - 0x2D - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USEREVOUTF - User EVOUT Port F - 0x2E - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USERTCA0 - User TCA0 - 0x33 - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USERTCB0 - User TCB0 - 0x34 - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USERTCB1 - User TCB1 - 0x35 - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USERTCB2 - User TCB2 - 0x36 - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USERTCB3 - User TCB3 - 0x37 - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USERUSART0 - User USART0 - 0x2F - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USERUSART1 - User USART1 - 0x30 - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USERUSART2 - User USART2 - 0x31 - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - USERUSART3 - User USART3 - 0x32 - - - CHANNEL - Channel selector - [7:0] - - true - - - - OFF - Off - 0 - - - CHANNEL0 - Connect user to event channel 0 - 1 - - - CHANNEL1 - Connect user to event channel 1 - 2 - - - CHANNEL2 - Connect user to event channel 2 - 3 - - - CHANNEL3 - Connect user to event channel 3 - 4 - - - CHANNEL4 - Connect user to event channel 4 - 5 - - - CHANNEL5 - Connect user to event channel 5 - 6 - - - CHANNEL6 - Connect user to event channel 6 - 7 - - - CHANNEL7 - Connect user to event channel 7 - 8 - - - - - - - - - FUSE - Fuses - 0x1280 - - - APPEND - Application Code Section End - 0x7 - - - 0 - 255 - - - - - BODCFG - BOD Configuration - 0x1 - - - SLEEP - BOD Operation in Sleep Mode - [1:0] - - true - - - - DIS - Disabled - 0 - - - ENABLED - Enabled - 1 - - - SAMPLED - Sampled - 2 - - - - - ACTIVE - BOD Operation in Active Mode - [3:2] - - true - - - - DIS - Disabled - 0 - - - ENABLED - Enabled - 1 - - - SAMPLED - Sampled - 2 - - - ENWAKE - Enabled with wake-up halted until BOD is ready - 3 - - - - - SAMPFREQ - BOD Sample Frequency - [4:4] - - true - - - - 1KHZ - 1kHz sampling frequency - 0 - - - 125HZ - 125Hz sampling frequency - 1 - - - - - LVL - BOD Level - [7:5] - - true - - - - BODLEVEL0 - 1.8 V - 0 - - - BODLEVEL2 - 2.6 V - 2 - - - BODLEVEL7 - 4.2 V - 7 - - - - - - - BOOTEND - Boot Section End - 0x8 - - - 0 - 255 - - - - - OSCCFG - Oscillator Configuration - 0x2 - - - FREQSEL - Frequency Select - [1:0] - - true - - - - 16MHZ - 16 MHz - 1 - - - 20MHZ - 20 MHz - 2 - - - - - OSCLOCK - Oscillator Lock - [7:7] - - - - - SYSCFG0 - System Configuration 0 - 0x5 - - - EESAVE - EEPROM Save - [0:0] - - - RSTPINCFG - Reset Pin Configuration - [3:3] - - true - - - - GPIO - GPIO mode - 0 - - - RST - Reset mode - 1 - - - - - CRCSRC - CRC Source - [7:6] - - true - - - - FLASH - The CRC is performed on the entire Flash (boot, application code and application data section). - 0 - - - BOOT - The CRC is performed on the boot section of Flash - 1 - - - BOOTAPP - The CRC is performed on the boot and application code section of Flash - 2 - - - NOCRC - Disable CRC. - 3 - - - - - - - SYSCFG1 - System Configuration 1 - 0x6 - - - SUT - Startup Time - [2:0] - - true - - - - 0MS - 0 ms - 0 - - - 1MS - 1 ms - 1 - - - 2MS - 2 ms - 2 - - - 4MS - 4 ms - 3 - - - 8MS - 8 ms - 4 - - - 16MS - 16 ms - 5 - - - 32MS - 32 ms - 6 - - - 64MS - 64 ms - 7 - - - - - - - WDTCFG - Watchdog Configuration - 0x0 - - - PERIOD - Watchdog Timeout Period - [3:0] - - true - - - - OFF - Off - 0 - - - 8CLK - 8 cycles (8ms) - 1 - - - 16CLK - 16 cycles (16ms) - 2 - - - 32CLK - 32 cycles (32ms) - 3 - - - 64CLK - 64 cycles (64ms) - 4 - - - 128CLK - 128 cycles (0.128s) - 5 - - - 256CLK - 256 cycles (0.256s) - 6 - - - 512CLK - 512 cycles (0.512s) - 7 - - - 1KCLK - 1K cycles (1.0s) - 8 - - - 2KCLK - 2K cycles (2.0s) - 9 - - - 4KCLK - 4K cycles (4.1s) - 10 - - - 8KCLK - 8K cycles (8.2s) - 11 - - - - - WINDOW - Watchdog Window Timeout Period - [7:4] - - true - - - - OFF - Off - 0 - - - 8CLK - 8 cycles (8ms) - 1 - - - 16CLK - 16 cycles (16ms) - 2 - - - 32CLK - 32 cycles (32ms) - 3 - - - 64CLK - 64 cycles (64ms) - 4 - - - 128CLK - 128 cycles (0.128s) - 5 - - - 256CLK - 256 cycles (0.256s) - 6 - - - 512CLK - 512 cycles (0.512s) - 7 - - - 1KCLK - 1K cycles (1.0s) - 8 - - - 2KCLK - 2K cycles (2.0s) - 9 - - - 4KCLK - 4K cycles (4.1s) - 10 - - - 8KCLK - 8K cycles (8.2s) - 11 - - - - - - - - - GPIO - General Purpose IO - 0x1C - - - GPIOR0 - General Purpose IO Register 0 - 0x0 - - - 0 - 255 - - - - - GPIOR1 - General Purpose IO Register 1 - 0x1 - - - 0 - 255 - - - - - GPIOR2 - General Purpose IO Register 2 - 0x2 - - - 0 - 255 - - - - - GPIOR3 - General Purpose IO Register 3 - 0x3 - - - 0 - 255 - - - - - - - LOCKBIT - Lockbit - 0x128A - - - LOCKBIT - Lock Bits - 0x0 - - - LB - Lock Bits - [7:0] - - true - - - - RWLOCK - Read and write lock - 58 - - - NOLOCK - No locks - 197 - - - - - - - - - NVMCTRL - Non-volatile Memory Controller - 0x1000 - - - ADDR - Address - 0x8 - 16 - - - 0 - 65535 - - - - - CTRLA - Control A - 0x0 - - - CMD - Command - [2:0] - - true - - - - NONE - No Command - 0 - - - PAGEWRITE - Write page - 1 - - - PAGEERASE - Erase page - 2 - - - PAGEERASEWRITE - Erase and write page - 3 - - - PAGEBUFCLR - Page buffer clear - 4 - - - CHIPERASE - Chip erase - 5 - - - EEERASE - EEPROM erase - 6 - - - FUSEWRITE - Write fuse (PDI only) - 7 - - - - - - - CTRLB - Control B - 0x1 - - - APCWP - Application code write protect - [0:0] - - - BOOTLOCK - Boot Lock - [1:1] - - - - - DATA - Data - 0x6 - 16 - - - 0 - 65535 - - - - - INTCTRL - Interrupt Control - 0x3 - - - EEREADY - EEPROM Ready - [0:0] - - - - - INTFLAGS - Interrupt Flags - 0x4 - - - EEREADY - EEPROM Ready - [0:0] - - - - - STATUS - Status - 0x2 - - - FBUSY - Flash busy - [0:0] - read-only - - - EEBUSY - EEPROM busy - [1:1] - read-only - - - WRERROR - Write error - [2:2] - read-only - - - - - - - PORTA - I/O Ports - 0x400 - - - DIR - Data Direction - 0x0 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - DIRCLR - Data Direction Clear - 0x2 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - DIRSET - Data Direction Set - 0x1 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - DIRTGL - Data Direction Toggle - 0x3 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - IN - Input Value - 0x8 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - INTFLAGS - Interrupt Flags - 0x9 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - OUT - Output Value - 0x4 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - OUTCLR - Output Value Clear - 0x6 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - OUTSET - Output Value Set - 0x5 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - OUTTGL - Output Value Toggle - 0x7 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - PIN0CTRL - Pin 0 Control - 0x10 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN1CTRL - Pin 1 Control - 0x11 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN2CTRL - Pin 2 Control - 0x12 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN3CTRL - Pin 3 Control - 0x13 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN4CTRL - Pin 4 Control - 0x14 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN5CTRL - Pin 5 Control - 0x15 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN6CTRL - Pin 6 Control - 0x16 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN7CTRL - Pin 7 Control - 0x17 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PORTCTRL - Port Control - 0xA - - - SRL - Slew Rate Limit Enable - [0:0] - - - - - - - PORTB - I/O Ports - 0x420 - - - DIR - Data Direction - 0x0 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - - - DIRCLR - Data Direction Clear - 0x2 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - - - DIRSET - Data Direction Set - 0x1 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - - - DIRTGL - Data Direction Toggle - 0x3 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - - - IN - Input Value - 0x8 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - - - INTFLAGS - Interrupt Flags - 0x9 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - - - OUT - Output Value - 0x4 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - - - OUTCLR - Output Value Clear - 0x6 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - - - OUTSET - Output Value Set - 0x5 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - - - OUTTGL - Output Value Toggle - 0x7 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - - - PIN0CTRL - Pin 0 Control - 0x10 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN1CTRL - Pin 1 Control - 0x11 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN2CTRL - Pin 2 Control - 0x12 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN3CTRL - Pin 3 Control - 0x13 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN4CTRL - Pin 4 Control - 0x14 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN5CTRL - Pin 5 Control - 0x15 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN6CTRL - Pin 6 Control - 0x16 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN7CTRL - Pin 7 Control - 0x17 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PORTCTRL - Port Control - 0xA - - - SRL - Slew Rate Limit Enable - [0:0] - - - - - - - PORTC - I/O Ports - 0x440 - - - DIR - Data Direction - 0x0 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - DIRCLR - Data Direction Clear - 0x2 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - DIRSET - Data Direction Set - 0x1 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - DIRTGL - Data Direction Toggle - 0x3 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - IN - Input Value - 0x8 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - INTFLAGS - Interrupt Flags - 0x9 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - OUT - Output Value - 0x4 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - OUTCLR - Output Value Clear - 0x6 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - OUTSET - Output Value Set - 0x5 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - OUTTGL - Output Value Toggle - 0x7 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - PIN0CTRL - Pin 0 Control - 0x10 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN1CTRL - Pin 1 Control - 0x11 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN2CTRL - Pin 2 Control - 0x12 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN3CTRL - Pin 3 Control - 0x13 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN4CTRL - Pin 4 Control - 0x14 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN5CTRL - Pin 5 Control - 0x15 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN6CTRL - Pin 6 Control - 0x16 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN7CTRL - Pin 7 Control - 0x17 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PORTCTRL - Port Control - 0xA - - - SRL - Slew Rate Limit Enable - [0:0] - - - - - - - PORTD - I/O Ports - 0x460 - - - DIR - Data Direction - 0x0 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - DIRCLR - Data Direction Clear - 0x2 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - DIRSET - Data Direction Set - 0x1 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - DIRTGL - Data Direction Toggle - 0x3 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - IN - Input Value - 0x8 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - INTFLAGS - Interrupt Flags - 0x9 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - OUT - Output Value - 0x4 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - OUTCLR - Output Value Clear - 0x6 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - OUTSET - Output Value Set - 0x5 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - OUTTGL - Output Value Toggle - 0x7 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PIN0CTRL - Pin 0 Control - 0x10 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN1CTRL - Pin 1 Control - 0x11 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN2CTRL - Pin 2 Control - 0x12 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN3CTRL - Pin 3 Control - 0x13 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN4CTRL - Pin 4 Control - 0x14 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN5CTRL - Pin 5 Control - 0x15 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN6CTRL - Pin 6 Control - 0x16 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN7CTRL - Pin 7 Control - 0x17 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PORTCTRL - Port Control - 0xA - - - SRL - Slew Rate Limit Enable - [0:0] - - - - - - - PORTE - I/O Ports - 0x480 - - - DIR - Data Direction - 0x0 - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - - - DIRCLR - Data Direction Clear - 0x2 - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - - - DIRSET - Data Direction Set - 0x1 - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - - - DIRTGL - Data Direction Toggle - 0x3 - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - - - IN - Input Value - 0x8 - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - - - INTFLAGS - Interrupt Flags - 0x9 - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - - - OUT - Output Value - 0x4 - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - - - OUTCLR - Output Value Clear - 0x6 - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - - - OUTSET - Output Value Set - 0x5 - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - - - OUTTGL - Output Value Toggle - 0x7 - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - - - PIN0CTRL - Pin 0 Control - 0x10 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN1CTRL - Pin 1 Control - 0x11 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN2CTRL - Pin 2 Control - 0x12 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN3CTRL - Pin 3 Control - 0x13 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN4CTRL - Pin 4 Control - 0x14 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN5CTRL - Pin 5 Control - 0x15 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN6CTRL - Pin 6 Control - 0x16 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN7CTRL - Pin 7 Control - 0x17 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PORTCTRL - Port Control - 0xA - - - SRL - Slew Rate Limit Enable - [0:0] - - - - - - - PORTF - I/O Ports - 0x4A0 - - - DIR - Data Direction - 0x0 - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF2 - Pin F2 - [2:2] - - - PF3 - Pin F3 - [3:3] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - - - DIRCLR - Data Direction Clear - 0x2 - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF2 - Pin F2 - [2:2] - - - PF3 - Pin F3 - [3:3] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - - - DIRSET - Data Direction Set - 0x1 - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF2 - Pin F2 - [2:2] - - - PF3 - Pin F3 - [3:3] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - - - DIRTGL - Data Direction Toggle - 0x3 - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF2 - Pin F2 - [2:2] - - - PF3 - Pin F3 - [3:3] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - - - IN - Input Value - 0x8 - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF2 - Pin F2 - [2:2] - - - PF3 - Pin F3 - [3:3] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - - - INTFLAGS - Interrupt Flags - 0x9 - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF2 - Pin F2 - [2:2] - - - PF3 - Pin F3 - [3:3] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - - - OUT - Output Value - 0x4 - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF2 - Pin F2 - [2:2] - - - PF3 - Pin F3 - [3:3] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - - - OUTCLR - Output Value Clear - 0x6 - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF2 - Pin F2 - [2:2] - - - PF3 - Pin F3 - [3:3] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - - - OUTSET - Output Value Set - 0x5 - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF2 - Pin F2 - [2:2] - - - PF3 - Pin F3 - [3:3] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - - - OUTTGL - Output Value Toggle - 0x7 - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF2 - Pin F2 - [2:2] - - - PF3 - Pin F3 - [3:3] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - - - PIN0CTRL - Pin 0 Control - 0x10 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN1CTRL - Pin 1 Control - 0x11 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN2CTRL - Pin 2 Control - 0x12 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN3CTRL - Pin 3 Control - 0x13 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN4CTRL - Pin 4 Control - 0x14 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN5CTRL - Pin 5 Control - 0x15 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN6CTRL - Pin 6 Control - 0x16 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PIN7CTRL - Pin 7 Control - 0x17 - - - ISC - Input/Sense Configuration - [2:0] - - true - - - - INTDISABLE - Interrupt disabled but input buffer enabled - 0 - - - BOTHEDGES - Sense Both Edges - 1 - - - RISING - Sense Rising Edge - 2 - - - FALLING - Sense Falling Edge - 3 - - - INPUT_DISABLE - Digital Input Buffer disabled - 4 - - - LEVEL - Sense low Level - 5 - - - - - PULLUPEN - Pullup enable - [3:3] - - - INVEN - Inverted I/O Enable - [7:7] - - - - - PORTCTRL - Port Control - 0xA - - - SRL - Slew Rate Limit Enable - [0:0] - - - - - - - PORTMUX - Port Multiplexer - 0x5E0 - - - CCLROUTEA - Port Multiplexer CCL - 0x1 - - - LUT0 - CCL LUT0 - [0:0] - - - LUT1 - CCL LUT1 - [1:1] - - - LUT2 - CCL LUT2 - [2:2] - - - LUT3 - CCL LUT3 - [3:3] - - - - - EVSYSROUTEA - Port Multiplexer EVSYS - 0x0 - - - EVOUT0 - Event Output 0 - [0:0] - - - EVOUT1 - Event Output 1 - [1:1] - - - EVOUT2 - Event Output 2 - [2:2] - - - EVOUT3 - Event Output 3 - [3:3] - - - EVOUT4 - Event Output 4 - [4:4] - - - EVOUT5 - Event Output 5 - [5:5] - - - - - TCAROUTEA - Port Multiplexer TCA - 0x4 - - - TCA0 - Port Multiplexer TCA0 - [2:0] - - true - - - - PORTA - TCA0 pins on PA[5:0] - 0 - - - PORTB - TCA0 pins on PB[5:0] - 1 - - - PORTC - TCA0 pins on PC[5:0] - 2 - - - PORTD - TCA0 pins on PD[5:0] - 3 - - - PORTE - TCA0 pins on PE[5:0] - 4 - - - PORTF - TCA0 pins on PF[5:0] - 5 - - - - - - - TCBROUTEA - Port Multiplexer TCB - 0x5 - - - TCB0 - Port Multiplexer TCB0 - [0:0] - - - TCB1 - Port Multiplexer TCB1 - [1:1] - - - TCB2 - Port Multiplexer TCB2 - [2:2] - - - TCB3 - Port Multiplexer TCB3 - [3:3] - - - - - TWISPIROUTEA - Port Multiplexer TWI and SPI - 0x3 - - - SPI0 - Port Multiplexer SPI0 - [1:0] - - true - - - - DEFAULT - SPI0 on PA[7:4] - 0 - - - ALT1 - SPI0 on PC[3:0] - 1 - - - ALT2 - SPI0 on PE[3:0] - 2 - - - NONE - Not connected to any pins - 3 - - - - - TWI0 - Port Multiplexer TWI0 - [5:4] - - true - - - - DEFAULT - SCL/SDA on PA[3:2], Slave mode on PC[3:2] in dual TWI mode - 0 - - - ALT1 - SCL/SDA on PA[3:2], Slave mode on PF[3:2] in dual TWI mode - 1 - - - ALT2 - SCL/SDA on PC[3:2], Slave mode on PF[3:2] in dual TWI mode - 2 - - - NONE - Not connected to any pins - 3 - - - - - - - USARTROUTEA - Port Multiplexer USART register A - 0x2 - - - USART0 - Port Multiplexer USART0 - [1:0] - - true - - - - DEFAULT - USART0 on PA[3:0] - 0 - - - ALT1 - USART0 on PA[7:4] - 1 - - - NONE - Not connected to any pins - 3 - - - - - USART1 - Port Multiplexer USART1 - [3:2] - - true - - - - DEFAULT - USART1 on PC[3:0] - 0 - - - ALT1 - USART1 on PC[7:4] - 1 - - - NONE - Not connected to any pins - 3 - - - - - USART2 - Port Multiplexer USART2 - [5:4] - - true - - - - DEFAULT - USART2 on PF[3:0] - 0 - - - ALT1 - USART2 on PF[6:4] - 1 - - - NONE - Not connected to any pins - 3 - - - - - USART3 - Port Multiplexer USART3 - [7:6] - - true - - - - DEFAULT - USART3 on PB[3:0] - 0 - - - ALT1 - USART3 on PB[5:4] - 1 - - - NONE - Not connected to any pins - 3 - - - - - - - - - RSTCTRL - Reset controller - 0x40 - - - RSTFR - Reset Flags - 0x0 - - - PORF - Power on Reset flag - [0:0] - - - BORF - Brown out detector Reset flag - [1:1] - - - EXTRF - External Reset flag - [2:2] - - - WDRF - Watch dog Reset flag - [3:3] - - - SWRF - Software Reset flag - [4:4] - - - UPDIRF - UPDI Reset flag - [5:5] - - - - - SWRR - Software Reset - 0x1 - - - SWRE - Software reset enable - [0:0] - - - - - - - RTC - Real-Time Counter - 0x140 - - - CALIB - Calibration - 0x6 - - - ERROR - Error Correction Value - [6:0] - - - 0 - 127 - - - - - SIGN - Error Correction Sign Bit - [7:7] - - - - - CLKSEL - Clock Select - 0x7 - - - CLKSEL - Clock Select - [1:0] - - true - - - - INT32K - Internal 32kHz OSC - 0 - - - INT1K - Internal 1kHz OSC - 1 - - - TOSC32K - 32KHz Crystal OSC - 2 - - - EXTCLK - External Clock - 3 - - - - - - - CMP - Compare - 0xC - 16 - - - 0 - 65535 - - - - - CNT - Counter - 0x8 - 16 - - - 0 - 65535 - - - - - CTRLA - Control A - 0x0 - - - RTCEN - Enable - [0:0] - - - CORREN - Correction enable - [2:2] - - - PRESCALER - Prescaling Factor - [6:3] - - true - - - - DIV1 - RTC Clock / 1 - 0 - - - DIV2 - RTC Clock / 2 - 1 - - - DIV4 - RTC Clock / 4 - 2 - - - DIV8 - RTC Clock / 8 - 3 - - - DIV16 - RTC Clock / 16 - 4 - - - DIV32 - RTC Clock / 32 - 5 - - - DIV64 - RTC Clock / 64 - 6 - - - DIV128 - RTC Clock / 128 - 7 - - - DIV256 - RTC Clock / 256 - 8 - - - DIV512 - RTC Clock / 512 - 9 - - - DIV1024 - RTC Clock / 1024 - 10 - - - DIV2048 - RTC Clock / 2048 - 11 - - - DIV4096 - RTC Clock / 4096 - 12 - - - DIV8192 - RTC Clock / 8192 - 13 - - - DIV16384 - RTC Clock / 16384 - 14 - - - DIV32768 - RTC Clock / 32768 - 15 - - - - - RUNSTDBY - Run In Standby - [7:7] - - - - - DBGCTRL - Debug control - 0x5 - - - DBGRUN - Run in debug - [0:0] - - - - - INTCTRL - Interrupt Control - 0x2 - - - OVF - Overflow Interrupt enable - [0:0] - - - CMP - Compare Match Interrupt enable - [1:1] - - - - - INTFLAGS - Interrupt Flags - 0x3 - - - OVF - Overflow Interrupt Flag - [0:0] - - - CMP - Compare Match Interrupt - [1:1] - - - - - PER - Period - 0xA - 16 - - - 0 - 65535 - - - - - PITCTRLA - PIT Control A - 0x10 - - - PITEN - Enable - [0:0] - - - PERIOD - Period - [6:3] - - true - - - - OFF - Off - 0 - - - CYC4 - RTC Clock Cycles 4 - 1 - - - CYC8 - RTC Clock Cycles 8 - 2 - - - CYC16 - RTC Clock Cycles 16 - 3 - - - CYC32 - RTC Clock Cycles 32 - 4 - - - CYC64 - RTC Clock Cycles 64 - 5 - - - CYC128 - RTC Clock Cycles 128 - 6 - - - CYC256 - RTC Clock Cycles 256 - 7 - - - CYC512 - RTC Clock Cycles 512 - 8 - - - CYC1024 - RTC Clock Cycles 1024 - 9 - - - CYC2048 - RTC Clock Cycles 2048 - 10 - - - CYC4096 - RTC Clock Cycles 4096 - 11 - - - CYC8192 - RTC Clock Cycles 8192 - 12 - - - CYC16384 - RTC Clock Cycles 16384 - 13 - - - CYC32768 - RTC Clock Cycles 32768 - 14 - - - - - - - PITDBGCTRL - PIT Debug control - 0x15 - - - DBGRUN - Run in debug - [0:0] - - - - - PITINTCTRL - PIT Interrupt Control - 0x12 - - - PI - Periodic Interrupt - [0:0] - - - - - PITINTFLAGS - PIT Interrupt Flags - 0x13 - - - PI - Periodic Interrupt - [0:0] - - - - - PITSTATUS - PIT Status - 0x11 - - - CTRLBUSY - CTRLA Synchronization Busy Flag - [0:0] - read-only - - - - - STATUS - Status - 0x1 - - - CTRLABUSY - CTRLA Synchronization Busy Flag - [0:0] - read-only - - - CNTBUSY - Count Synchronization Busy Flag - [1:1] - read-only - - - PERBUSY - Period Synchronization Busy Flag - [2:2] - read-only - - - CMPBUSY - Comparator Synchronization Busy Flag - [3:3] - read-only - - - - - TEMP - Temporary - 0x4 - - - 0 - 255 - - - - - - - SIGROW - Signature row - 0x1100 - - - CHECKSUM1 - CRC Checksum Byte 1 - 0x2F - - - 0 - 255 - - - - - DEVICEID0 - Device ID Byte 0 - 0x0 - - - 0 - 255 - - - - - DEVICEID1 - Device ID Byte 1 - 0x1 - - - 0 - 255 - - - - - DEVICEID2 - Device ID Byte 2 - 0x2 - - - 0 - 255 - - - - - OSC16ERR3V - OSC16 error at 3V - 0x22 - - - 0 - 255 - - - - - OSC16ERR5V - OSC16 error at 5V - 0x23 - - - 0 - 255 - - - - - OSC20ERR3V - OSC20 error at 3V - 0x24 - - - 0 - 255 - - - - - OSC20ERR5V - OSC20 error at 5V - 0x25 - - - 0 - 255 - - - - - OSCCAL16M0 - Oscillator Calibration 16 MHz Byte 0 - 0x18 - - - 0 - 255 - - - - - OSCCAL16M1 - Oscillator Calibration 16 MHz Byte 1 - 0x19 - - - 0 - 255 - - - - - OSCCAL20M0 - Oscillator Calibration 20 MHz Byte 0 - 0x1A - - - 0 - 255 - - - - - OSCCAL20M1 - Oscillator Calibration 20 MHz Byte 1 - 0x1B - - - 0 - 255 - - - - - OSCCAL32K - Oscillator Calibration for 32kHz ULP - 0x14 - - - 0 - 255 - - - - - SERNUM0 - Serial Number Byte 0 - 0x3 - - - 0 - 255 - - - - - SERNUM1 - Serial Number Byte 1 - 0x4 - - - 0 - 255 - - - - - SERNUM2 - Serial Number Byte 2 - 0x5 - - - 0 - 255 - - - - - SERNUM3 - Serial Number Byte 3 - 0x6 - - - 0 - 255 - - - - - SERNUM4 - Serial Number Byte 4 - 0x7 - - - 0 - 255 - - - - - SERNUM5 - Serial Number Byte 5 - 0x8 - - - 0 - 255 - - - - - SERNUM6 - Serial Number Byte 6 - 0x9 - - - 0 - 255 - - - - - SERNUM7 - Serial Number Byte 7 - 0xA - - - 0 - 255 - - - - - SERNUM8 - Serial Number Byte 8 - 0xB - - - 0 - 255 - - - - - SERNUM9 - Serial Number Byte 9 - 0xC - - - 0 - 255 - - - - - TEMPSENSE0 - Temperature Sensor Calibration Byte 0 - 0x20 - - - 0 - 255 - - - - - TEMPSENSE1 - Temperature Sensor Calibration Byte 1 - 0x21 - - - 0 - 255 - - - - - - - SLPCTRL - Sleep Controller - 0x50 - - - CTRLA - Control - 0x0 - - - SEN - Sleep enable - [0:0] - - - SMODE - Sleep mode - [2:1] - - true - - - - IDLE - Idle mode - 0 - - - STDBY - Standby Mode - 1 - - - PDOWN - Power-down Mode - 2 - - - - - - - - - SPI0 - Serial Peripheral Interface - 0x8C0 - - - CTRLA - Control A - 0x0 - - - ENABLE - Enable Module - [0:0] - - - PRESC - Prescaler - [2:1] - - true - - - - DIV4 - System Clock / 4 - 0 - - - DIV16 - System Clock / 16 - 1 - - - DIV64 - System Clock / 64 - 2 - - - DIV128 - System Clock / 128 - 3 - - - - - CLK2X - Enable Double Speed - [4:4] - - - MASTER - Master Operation Enable - [5:5] - - - DORD - Data Order Setting - [6:6] - - - - - CTRLB - Control B - 0x1 - - - MODE - SPI Mode - [1:0] - - true - - - - 0 - SPI Mode 0 - 0 - - - 1 - SPI Mode 1 - 1 - - - 2 - SPI Mode 2 - 2 - - - 3 - SPI Mode 3 - 3 - - - - - SSD - Slave Select Disable - [2:2] - - - BUFWR - Buffer Write Mode - [6:6] - - - BUFEN - Buffer Mode Enable - [7:7] - - - - - DATA - Data - 0x4 - - - 0 - 255 - - - - - INTCTRL - Interrupt Control - 0x2 - - - IE - Interrupt Enable - [0:0] - - - SSIE - Slave Select Trigger Interrupt Enable - [4:4] - - - DREIE - Data Register Empty Interrupt Enable - [5:5] - - - TXCIE - Transfer Complete Interrupt Enable - [6:6] - - - RXCIE - Receive Complete Interrupt Enable - [7:7] - - - - - INTFLAGS - Interrupt Flags - 0x3 - - - 0 - 255 - - - - - - - SYSCFG - System Configuration Registers - 0xF01 - - - EXTBRK - External Break - 0x1 - - - ENEXTBRK - External break enable - [0:0] - - - - - OCDM - OCD Message Register - 0x17 - - - 0 - 255 - - - - - OCDMS - OCD Message Status - 0x18 - - - OCDMR - OCD Message Read - [0:0] - - - - - REVID - Revision ID - 0x0 - - - 0 - 255 - - - - - - - TCB0 - 16-bit Timer Type B - 0xA80 - - - CCMP - Compare or Capture - 0xC - 16 - - - 0 - 65535 - - - - - CNT - Count - 0xA - 16 - - - 0 - 65535 - - - - - CTRLA - Control A - 0x0 - - - ENABLE - Enable - [0:0] - - - CLKSEL - Clock Select - [2:1] - - true - - - - CLKDIV1 - CLK_PER (No Prescaling) - 0 - - - CLKDIV2 - CLK_PER/2 (From Prescaler) - 1 - - - CLKTCA - Use Clock from TCA - 2 - - - - - SYNCUPD - Synchronize Update - [4:4] - - - RUNSTDBY - Run Standby - [6:6] - - - - - CTRLB - Control Register B - 0x1 - - - CNTMODE - Timer Mode - [2:0] - - true - - - - INT - Periodic Interrupt - 0 - - - TIMEOUT - Periodic Timeout - 1 - - - CAPT - Input Capture Event - 2 - - - FRQ - Input Capture Frequency measurement - 3 - - - PW - Input Capture Pulse-Width measurement - 4 - - - FRQPW - Input Capture Frequency and Pulse-Width measurement - 5 - - - SINGLE - Single Shot - 6 - - - PWM8 - 8-bit PWM - 7 - - - - - CCMPEN - Pin Output Enable - [4:4] - - - CCMPINIT - Pin Initial State - [5:5] - - - ASYNC - Asynchronous Enable - [6:6] - - - - - DBGCTRL - Debug Control - 0x8 - - - DBGRUN - Debug Run - [0:0] - - - - - EVCTRL - Event Control - 0x4 - - - CAPTEI - Event Input Enable - [0:0] - - - EDGE - Event Edge - [4:4] - - - FILTER - Input Capture Noise Cancellation Filter - [6:6] - - - - - INTCTRL - Interrupt Control - 0x5 - - - CAPT - Capture or Timeout - [0:0] - - - - - INTFLAGS - Interrupt Flags - 0x6 - - - CAPT - Capture or Timeout - [0:0] - - - - - STATUS - Status - 0x7 - - - RUN - Run - [0:0] - read-only - - - - - TEMP - Temporary Value - 0x9 - - - 0 - 255 - - - - - - - TCB1 - 16-bit Timer Type B - 0xA90 - - - CCMP - Compare or Capture - 0xC - 16 - - - 0 - 65535 - - - - - CNT - Count - 0xA - 16 - - - 0 - 65535 - - - - - CTRLA - Control A - 0x0 - - - ENABLE - Enable - [0:0] - - - CLKSEL - Clock Select - [2:1] - - true - - - - CLKDIV1 - CLK_PER (No Prescaling) - 0 - - - CLKDIV2 - CLK_PER/2 (From Prescaler) - 1 - - - CLKTCA - Use Clock from TCA - 2 - - - - - SYNCUPD - Synchronize Update - [4:4] - - - RUNSTDBY - Run Standby - [6:6] - - - - - CTRLB - Control Register B - 0x1 - - - CNTMODE - Timer Mode - [2:0] - - true - - - - INT - Periodic Interrupt - 0 - - - TIMEOUT - Periodic Timeout - 1 - - - CAPT - Input Capture Event - 2 - - - FRQ - Input Capture Frequency measurement - 3 - - - PW - Input Capture Pulse-Width measurement - 4 - - - FRQPW - Input Capture Frequency and Pulse-Width measurement - 5 - - - SINGLE - Single Shot - 6 - - - PWM8 - 8-bit PWM - 7 - - - - - CCMPEN - Pin Output Enable - [4:4] - - - CCMPINIT - Pin Initial State - [5:5] - - - ASYNC - Asynchronous Enable - [6:6] - - - - - DBGCTRL - Debug Control - 0x8 - - - DBGRUN - Debug Run - [0:0] - - - - - EVCTRL - Event Control - 0x4 - - - CAPTEI - Event Input Enable - [0:0] - - - EDGE - Event Edge - [4:4] - - - FILTER - Input Capture Noise Cancellation Filter - [6:6] - - - - - INTCTRL - Interrupt Control - 0x5 - - - CAPT - Capture or Timeout - [0:0] - - - - - INTFLAGS - Interrupt Flags - 0x6 - - - CAPT - Capture or Timeout - [0:0] - - - - - STATUS - Status - 0x7 - - - RUN - Run - [0:0] - read-only - - - - - TEMP - Temporary Value - 0x9 - - - 0 - 255 - - - - - - - TCB2 - 16-bit Timer Type B - 0xAA0 - - - CCMP - Compare or Capture - 0xC - 16 - - - 0 - 65535 - - - - - CNT - Count - 0xA - 16 - - - 0 - 65535 - - - - - CTRLA - Control A - 0x0 - - - ENABLE - Enable - [0:0] - - - CLKSEL - Clock Select - [2:1] - - true - - - - CLKDIV1 - CLK_PER (No Prescaling) - 0 - - - CLKDIV2 - CLK_PER/2 (From Prescaler) - 1 - - - CLKTCA - Use Clock from TCA - 2 - - - - - SYNCUPD - Synchronize Update - [4:4] - - - RUNSTDBY - Run Standby - [6:6] - - - - - CTRLB - Control Register B - 0x1 - - - CNTMODE - Timer Mode - [2:0] - - true - - - - INT - Periodic Interrupt - 0 - - - TIMEOUT - Periodic Timeout - 1 - - - CAPT - Input Capture Event - 2 - - - FRQ - Input Capture Frequency measurement - 3 - - - PW - Input Capture Pulse-Width measurement - 4 - - - FRQPW - Input Capture Frequency and Pulse-Width measurement - 5 - - - SINGLE - Single Shot - 6 - - - PWM8 - 8-bit PWM - 7 - - - - - CCMPEN - Pin Output Enable - [4:4] - - - CCMPINIT - Pin Initial State - [5:5] - - - ASYNC - Asynchronous Enable - [6:6] - - - - - DBGCTRL - Debug Control - 0x8 - - - DBGRUN - Debug Run - [0:0] - - - - - EVCTRL - Event Control - 0x4 - - - CAPTEI - Event Input Enable - [0:0] - - - EDGE - Event Edge - [4:4] - - - FILTER - Input Capture Noise Cancellation Filter - [6:6] - - - - - INTCTRL - Interrupt Control - 0x5 - - - CAPT - Capture or Timeout - [0:0] - - - - - INTFLAGS - Interrupt Flags - 0x6 - - - CAPT - Capture or Timeout - [0:0] - - - - - STATUS - Status - 0x7 - - - RUN - Run - [0:0] - read-only - - - - - TEMP - Temporary Value - 0x9 - - - 0 - 255 - - - - - - - TCB3 - 16-bit Timer Type B - 0xAB0 - - - CCMP - Compare or Capture - 0xC - 16 - - - 0 - 65535 - - - - - CNT - Count - 0xA - 16 - - - 0 - 65535 - - - - - CTRLA - Control A - 0x0 - - - ENABLE - Enable - [0:0] - - - CLKSEL - Clock Select - [2:1] - - true - - - - CLKDIV1 - CLK_PER (No Prescaling) - 0 - - - CLKDIV2 - CLK_PER/2 (From Prescaler) - 1 - - - CLKTCA - Use Clock from TCA - 2 - - - - - SYNCUPD - Synchronize Update - [4:4] - - - RUNSTDBY - Run Standby - [6:6] - - - - - CTRLB - Control Register B - 0x1 - - - CNTMODE - Timer Mode - [2:0] - - true - - - - INT - Periodic Interrupt - 0 - - - TIMEOUT - Periodic Timeout - 1 - - - CAPT - Input Capture Event - 2 - - - FRQ - Input Capture Frequency measurement - 3 - - - PW - Input Capture Pulse-Width measurement - 4 - - - FRQPW - Input Capture Frequency and Pulse-Width measurement - 5 - - - SINGLE - Single Shot - 6 - - - PWM8 - 8-bit PWM - 7 - - - - - CCMPEN - Pin Output Enable - [4:4] - - - CCMPINIT - Pin Initial State - [5:5] - - - ASYNC - Asynchronous Enable - [6:6] - - - - - DBGCTRL - Debug Control - 0x8 - - - DBGRUN - Debug Run - [0:0] - - - - - EVCTRL - Event Control - 0x4 - - - CAPTEI - Event Input Enable - [0:0] - - - EDGE - Event Edge - [4:4] - - - FILTER - Input Capture Noise Cancellation Filter - [6:6] - - - - - INTCTRL - Interrupt Control - 0x5 - - - CAPT - Capture or Timeout - [0:0] - - - - - INTFLAGS - Interrupt Flags - 0x6 - - - CAPT - Capture or Timeout - [0:0] - - - - - STATUS - Status - 0x7 - - - RUN - Run - [0:0] - read-only - - - - - TEMP - Temporary Value - 0x9 - - - 0 - 255 - - - - - - - TWI0 - Two-Wire Interface - 0x8A0 - - - CTRLA - Control A - 0x0 - - - 0 - 255 - - - - - DBGCTRL - Debug Control Register - 0x2 - - - 0 - 255 - - - - - DUALCTRL - Dual Control - 0x1 - - - 0 - 255 - - - - - MADDR - Master Address - 0x7 - - - 0 - 255 - - - - - MBAUD - Master Baurd Rate Control - 0x6 - - - 0 - 255 - - - - - MCTRLA - Master Control A - 0x3 - - - ENABLE - Enable TWI Master - [0:0] - - - SMEN - Smart Mode Enable - [1:1] - - - TIMEOUT - Inactive Bus Timeout - [3:2] - - true - - - - DISABLED - Bus Timeout Disabled - 0 - - - 50US - 50 Microseconds - 1 - - - 100US - 100 Microseconds - 2 - - - 200US - 200 Microseconds - 3 - - - - - QCEN - Quick Command Enable - [4:4] - - - WIEN - Write Interrupt Enable - [6:6] - - - RIEN - Read Interrupt Enable - [7:7] - - - - - MCTRLB - Master Control B - 0x4 - - - MCMD - Command - [1:0] - - true - - - - NOACT - No Action - 0 - - - REPSTART - Issue Repeated Start Condition - 1 - - - RECVTRANS - Receive or Transmit Data, depending on DIR - 2 - - - STOP - Issue Stop Condition - 3 - - - - - ACKACT - Acknowledge Action - [2:2] - - true - - - - ACK - Send ACK - 0 - - - NACK - Send NACK - 1 - - - - - FLUSH - Flush - [3:3] - - - - - MDATA - Master Data - 0x8 - - - 0 - 255 - - - - - MSTATUS - Master Status - 0x5 - - - BUSSTATE - Bus State - [1:0] - - true - - - - UNKNOWN - Unknown Bus State - 0 - - - IDLE - Bus is Idle - 1 - - - OWNER - This Module Controls The Bus - 2 - - - BUSY - The Bus is Busy - 3 - - - - - BUSERR - Bus Error - [2:2] - - - ARBLOST - Arbitration Lost - [3:3] - - - RXACK - Received Acknowledge - [4:4] - read-only - - - CLKHOLD - Clock Hold - [5:5] - - - WIF - Write Interrupt Flag - [6:6] - - - RIF - Read Interrupt Flag - [7:7] - - - - - SADDR - Slave Address - 0xC - - - 0 - 255 - - - - - SADDRMASK - Slave Address Mask - 0xE - - - ADDREN - Address Enable - [0:0] - - - ADDRMASK - Address Mask - [7:1] - - - 0 - 127 - - - - - - - SCTRLA - Slave Control A - 0x9 - - - ENABLE - Enable TWI Slave - [0:0] - - - SMEN - Smart Mode Enable - [1:1] - - - PMEN - Promiscuous Mode Enable - [2:2] - - - PIEN - Stop Interrupt Enable - [5:5] - - - APIEN - Address/Stop Interrupt Enable - [6:6] - - - DIEN - Data Interrupt Enable - [7:7] - - - - - SCTRLB - Slave Control B - 0xA - - - SCMD - Command - [1:0] - - true - - - - NOACT - No Action - 0 - - - COMPTRANS - Used To Complete a Transaction - 2 - - - RESPONSE - Used in Response to Address/Data Interrupt - 3 - - - - - ACKACT - Acknowledge Action - [2:2] - - true - - - - ACK - Send ACK - 0 - - - NACK - Send NACK - 1 - - - - - - - SDATA - Slave Data - 0xD - - - 0 - 255 - - - - - SSTATUS - Slave Status - 0xB - - - AP - Slave Address or Stop - [0:0] - read-only - - true - - - - STOP - Stop condition generated APIF - 0 - - - ADR - Address detection generated APIF - 1 - - - - - DIR - Read/Write Direction - [1:1] - read-only - - - BUSERR - Bus Error - [2:2] - - - COLL - Collision - [3:3] - - - RXACK - Received Acknowledge - [4:4] - read-only - - - CLKHOLD - Clock Hold - [5:5] - read-only - - - APIF - Address/Stop Interrupt Flag - [6:6] - - - DIF - Data Interrupt Flag - [7:7] - - - - - - - USART0 - Universal Synchronous and Asynchronous Receiver and Transmitter - 0x800 - - - BAUD - Baud Rate - 0x8 - 16 - - - 0 - 65535 - - - - - CTRLA - Control A - 0x5 - - - RS485 - RS485 Mode internal transmitter - [1:0] - - true - - - - OFF - RS485 Mode disabled - 0 - - - EXT - RS485 Mode External drive - 1 - - - INT - RS485 Mode Internal drive - 2 - - - - - ABEIE - Auto-baud Error Interrupt Enable - [2:2] - - - LBME - Loop-back Mode Enable - [3:3] - - - RXSIE - Receiver Start Frame Interrupt Enable - [4:4] - - - DREIE - Data Register Empty Interrupt Enable - [5:5] - - - TXCIE - Transmit Complete Interrupt Enable - [6:6] - - - RXCIE - Receive Complete Interrupt Enable - [7:7] - - - - - CTRLB - Control B - 0x6 - - - MPCM - Multi-processor Communication Mode - [0:0] - - - RXMODE - Receiver Mode - [2:1] - - true - - - - NORMAL - Normal mode - 0 - - - CLK2X - CLK2x mode - 1 - - - GENAUTO - Generic autobaud mode - 2 - - - LINAUTO - LIN constrained autobaud mode - 3 - - - - - ODME - Open Drain Mode Enable - [3:3] - - - SFDEN - Start Frame Detection Enable - [4:4] - - - TXEN - Transmitter Enable - [6:6] - - - RXEN - Reciever enable - [7:7] - - - - - CTRLC - Control C - 0x7 - - - 0 - 255 - - - - - CTRLD - Control D - 0xA - - - ABW - Auto Baud Window - [7:6] - - true - - - - WDW0 - 18% tolerance - 0 - - - WDW1 - 15% tolerance - 1 - - - WDW2 - 21% tolerance - 2 - - - WDW3 - 25% tolerance - 3 - - - - - - - DBGCTRL - Debug Control - 0xB - - - DBGRUN - Debug Run - [0:0] - - - ABMBP - Autobaud majority voter bypass - [7:7] - - - - - EVCTRL - Event Control - 0xC - - - IREI - IrDA Event Input Enable - [0:0] - - - - - RXDATAH - Receive Data High Byte - 0x1 - - - DATA8 - Receiver Data Register - [0:0] - read-only - - - PERR - Parity Error - [1:1] - read-only - - - FERR - Frame Error - [2:2] - read-only - - - BUFOVF - Buffer Overflow - [6:6] - read-only - - - RXCIF - Receive Complete Interrupt Flag - [7:7] - read-only - - - - - RXDATAL - Receive Data Low Byte - 0x0 - - - DATA - RX Data - [7:0] - read-only - - - 0 - 255 - - - - - - - RXPLCTRL - IRCOM Receiver Pulse Length Control - 0xE - - - RXPL - Receiver Pulse Lenght - [6:0] - - - 0 - 127 - - - - - - - STATUS - Status - 0x4 - - - WFB - Wait For Break - [0:0] - - - BDF - Break Detected Flag - [1:1] - - - ISFIF - Inconsistent Sync Field Interrupt Flag - [3:3] - - - RXSIF - Receive Start Interrupt - [4:4] - read-only - - - DREIF - Data Register Empty Flag - [5:5] - read-only - - - TXCIF - Transmit Interrupt Flag - [6:6] - - - RXCIF - Receive Complete Interrupt Flag - [7:7] - read-only - - - - - TXDATAH - Transmit Data High Byte - 0x3 - - - DATA8 - Transmit Data Register (CHSIZE=9bit) - [0:0] - - - - - TXDATAL - Transmit Data Low Byte - 0x2 - - - DATA - Transmit Data Register - [7:0] - - - 0 - 255 - - - - - - - TXPLCTRL - IRCOM Transmitter Pulse Length Control - 0xD - - - TXPL - Transmit pulse length - [7:0] - - - 0 - 255 - - - - - - - - - USART1 - Universal Synchronous and Asynchronous Receiver and Transmitter - 0x820 - - - BAUD - Baud Rate - 0x8 - 16 - - - 0 - 65535 - - - - - CTRLA - Control A - 0x5 - - - RS485 - RS485 Mode internal transmitter - [1:0] - - true - - - - OFF - RS485 Mode disabled - 0 - - - EXT - RS485 Mode External drive - 1 - - - INT - RS485 Mode Internal drive - 2 - - - - - ABEIE - Auto-baud Error Interrupt Enable - [2:2] - - - LBME - Loop-back Mode Enable - [3:3] - - - RXSIE - Receiver Start Frame Interrupt Enable - [4:4] - - - DREIE - Data Register Empty Interrupt Enable - [5:5] - - - TXCIE - Transmit Complete Interrupt Enable - [6:6] - - - RXCIE - Receive Complete Interrupt Enable - [7:7] - - - - - CTRLB - Control B - 0x6 - - - MPCM - Multi-processor Communication Mode - [0:0] - - - RXMODE - Receiver Mode - [2:1] - - true - - - - NORMAL - Normal mode - 0 - - - CLK2X - CLK2x mode - 1 - - - GENAUTO - Generic autobaud mode - 2 - - - LINAUTO - LIN constrained autobaud mode - 3 - - - - - ODME - Open Drain Mode Enable - [3:3] - - - SFDEN - Start Frame Detection Enable - [4:4] - - - TXEN - Transmitter Enable - [6:6] - - - RXEN - Reciever enable - [7:7] - - - - - CTRLC - Control C - 0x7 - - - 0 - 255 - - - - - CTRLD - Control D - 0xA - - - ABW - Auto Baud Window - [7:6] - - true - - - - WDW0 - 18% tolerance - 0 - - - WDW1 - 15% tolerance - 1 - - - WDW2 - 21% tolerance - 2 - - - WDW3 - 25% tolerance - 3 - - - - - - - DBGCTRL - Debug Control - 0xB - - - DBGRUN - Debug Run - [0:0] - - - ABMBP - Autobaud majority voter bypass - [7:7] - - - - - EVCTRL - Event Control - 0xC - - - IREI - IrDA Event Input Enable - [0:0] - - - - - RXDATAH - Receive Data High Byte - 0x1 - - - DATA8 - Receiver Data Register - [0:0] - read-only - - - PERR - Parity Error - [1:1] - read-only - - - FERR - Frame Error - [2:2] - read-only - - - BUFOVF - Buffer Overflow - [6:6] - read-only - - - RXCIF - Receive Complete Interrupt Flag - [7:7] - read-only - - - - - RXDATAL - Receive Data Low Byte - 0x0 - - - DATA - RX Data - [7:0] - read-only - - - 0 - 255 - - - - - - - RXPLCTRL - IRCOM Receiver Pulse Length Control - 0xE - - - RXPL - Receiver Pulse Lenght - [6:0] - - - 0 - 127 - - - - - - - STATUS - Status - 0x4 - - - WFB - Wait For Break - [0:0] - - - BDF - Break Detected Flag - [1:1] - - - ISFIF - Inconsistent Sync Field Interrupt Flag - [3:3] - - - RXSIF - Receive Start Interrupt - [4:4] - read-only - - - DREIF - Data Register Empty Flag - [5:5] - read-only - - - TXCIF - Transmit Interrupt Flag - [6:6] - - - RXCIF - Receive Complete Interrupt Flag - [7:7] - read-only - - - - - TXDATAH - Transmit Data High Byte - 0x3 - - - DATA8 - Transmit Data Register (CHSIZE=9bit) - [0:0] - - - - - TXDATAL - Transmit Data Low Byte - 0x2 - - - DATA - Transmit Data Register - [7:0] - - - 0 - 255 - - - - - - - TXPLCTRL - IRCOM Transmitter Pulse Length Control - 0xD - - - TXPL - Transmit pulse length - [7:0] - - - 0 - 255 - - - - - - - - - USART2 - Universal Synchronous and Asynchronous Receiver and Transmitter - 0x840 - - - BAUD - Baud Rate - 0x8 - 16 - - - 0 - 65535 - - - - - CTRLA - Control A - 0x5 - - - RS485 - RS485 Mode internal transmitter - [1:0] - - true - - - - OFF - RS485 Mode disabled - 0 - - - EXT - RS485 Mode External drive - 1 - - - INT - RS485 Mode Internal drive - 2 - - - - - ABEIE - Auto-baud Error Interrupt Enable - [2:2] - - - LBME - Loop-back Mode Enable - [3:3] - - - RXSIE - Receiver Start Frame Interrupt Enable - [4:4] - - - DREIE - Data Register Empty Interrupt Enable - [5:5] - - - TXCIE - Transmit Complete Interrupt Enable - [6:6] - - - RXCIE - Receive Complete Interrupt Enable - [7:7] - - - - - CTRLB - Control B - 0x6 - - - MPCM - Multi-processor Communication Mode - [0:0] - - - RXMODE - Receiver Mode - [2:1] - - true - - - - NORMAL - Normal mode - 0 - - - CLK2X - CLK2x mode - 1 - - - GENAUTO - Generic autobaud mode - 2 - - - LINAUTO - LIN constrained autobaud mode - 3 - - - - - ODME - Open Drain Mode Enable - [3:3] - - - SFDEN - Start Frame Detection Enable - [4:4] - - - TXEN - Transmitter Enable - [6:6] - - - RXEN - Reciever enable - [7:7] - - - - - CTRLC - Control C - 0x7 - - - 0 - 255 - - - - - CTRLD - Control D - 0xA - - - ABW - Auto Baud Window - [7:6] - - true - - - - WDW0 - 18% tolerance - 0 - - - WDW1 - 15% tolerance - 1 - - - WDW2 - 21% tolerance - 2 - - - WDW3 - 25% tolerance - 3 - - - - - - - DBGCTRL - Debug Control - 0xB - - - DBGRUN - Debug Run - [0:0] - - - ABMBP - Autobaud majority voter bypass - [7:7] - - - - - EVCTRL - Event Control - 0xC - - - IREI - IrDA Event Input Enable - [0:0] - - - - - RXDATAH - Receive Data High Byte - 0x1 - - - DATA8 - Receiver Data Register - [0:0] - read-only - - - PERR - Parity Error - [1:1] - read-only - - - FERR - Frame Error - [2:2] - read-only - - - BUFOVF - Buffer Overflow - [6:6] - read-only - - - RXCIF - Receive Complete Interrupt Flag - [7:7] - read-only - - - - - RXDATAL - Receive Data Low Byte - 0x0 - - - DATA - RX Data - [7:0] - read-only - - - 0 - 255 - - - - - - - RXPLCTRL - IRCOM Receiver Pulse Length Control - 0xE - - - RXPL - Receiver Pulse Lenght - [6:0] - - - 0 - 127 - - - - - - - STATUS - Status - 0x4 - - - WFB - Wait For Break - [0:0] - - - BDF - Break Detected Flag - [1:1] - - - ISFIF - Inconsistent Sync Field Interrupt Flag - [3:3] - - - RXSIF - Receive Start Interrupt - [4:4] - read-only - - - DREIF - Data Register Empty Flag - [5:5] - read-only - - - TXCIF - Transmit Interrupt Flag - [6:6] - - - RXCIF - Receive Complete Interrupt Flag - [7:7] - read-only - - - - - TXDATAH - Transmit Data High Byte - 0x3 - - - DATA8 - Transmit Data Register (CHSIZE=9bit) - [0:0] - - - - - TXDATAL - Transmit Data Low Byte - 0x2 - - - DATA - Transmit Data Register - [7:0] - - - 0 - 255 - - - - - - - TXPLCTRL - IRCOM Transmitter Pulse Length Control - 0xD - - - TXPL - Transmit pulse length - [7:0] - - - 0 - 255 - - - - - - - - - USART3 - Universal Synchronous and Asynchronous Receiver and Transmitter - 0x860 - - - BAUD - Baud Rate - 0x8 - 16 - - - 0 - 65535 - - - - - CTRLA - Control A - 0x5 - - - RS485 - RS485 Mode internal transmitter - [1:0] - - true - - - - OFF - RS485 Mode disabled - 0 - - - EXT - RS485 Mode External drive - 1 - - - INT - RS485 Mode Internal drive - 2 - - - - - ABEIE - Auto-baud Error Interrupt Enable - [2:2] - - - LBME - Loop-back Mode Enable - [3:3] - - - RXSIE - Receiver Start Frame Interrupt Enable - [4:4] - - - DREIE - Data Register Empty Interrupt Enable - [5:5] - - - TXCIE - Transmit Complete Interrupt Enable - [6:6] - - - RXCIE - Receive Complete Interrupt Enable - [7:7] - - - - - CTRLB - Control B - 0x6 - - - MPCM - Multi-processor Communication Mode - [0:0] - - - RXMODE - Receiver Mode - [2:1] - - true - - - - NORMAL - Normal mode - 0 - - - CLK2X - CLK2x mode - 1 - - - GENAUTO - Generic autobaud mode - 2 - - - LINAUTO - LIN constrained autobaud mode - 3 - - - - - ODME - Open Drain Mode Enable - [3:3] - - - SFDEN - Start Frame Detection Enable - [4:4] - - - TXEN - Transmitter Enable - [6:6] - - - RXEN - Reciever enable - [7:7] - - - - - CTRLC - Control C - 0x7 - - - 0 - 255 - - - - - CTRLD - Control D - 0xA - - - ABW - Auto Baud Window - [7:6] - - true - - - - WDW0 - 18% tolerance - 0 - - - WDW1 - 15% tolerance - 1 - - - WDW2 - 21% tolerance - 2 - - - WDW3 - 25% tolerance - 3 - - - - - - - DBGCTRL - Debug Control - 0xB - - - DBGRUN - Debug Run - [0:0] - - - ABMBP - Autobaud majority voter bypass - [7:7] - - - - - EVCTRL - Event Control - 0xC - - - IREI - IrDA Event Input Enable - [0:0] - - - - - RXDATAH - Receive Data High Byte - 0x1 - - - DATA8 - Receiver Data Register - [0:0] - read-only - - - PERR - Parity Error - [1:1] - read-only - - - FERR - Frame Error - [2:2] - read-only - - - BUFOVF - Buffer Overflow - [6:6] - read-only - - - RXCIF - Receive Complete Interrupt Flag - [7:7] - read-only - - - - - RXDATAL - Receive Data Low Byte - 0x0 - - - DATA - RX Data - [7:0] - read-only - - - 0 - 255 - - - - - - - RXPLCTRL - IRCOM Receiver Pulse Length Control - 0xE - - - RXPL - Receiver Pulse Lenght - [6:0] - - - 0 - 127 - - - - - - - STATUS - Status - 0x4 - - - WFB - Wait For Break - [0:0] - - - BDF - Break Detected Flag - [1:1] - - - ISFIF - Inconsistent Sync Field Interrupt Flag - [3:3] - - - RXSIF - Receive Start Interrupt - [4:4] - read-only - - - DREIF - Data Register Empty Flag - [5:5] - read-only - - - TXCIF - Transmit Interrupt Flag - [6:6] - - - RXCIF - Receive Complete Interrupt Flag - [7:7] - read-only - - - - - TXDATAH - Transmit Data High Byte - 0x3 - - - DATA8 - Transmit Data Register (CHSIZE=9bit) - [0:0] - - - - - TXDATAL - Transmit Data Low Byte - 0x2 - - - DATA - Transmit Data Register - [7:0] - - - 0 - 255 - - - - - - - TXPLCTRL - IRCOM Transmitter Pulse Length Control - 0xD - - - TXPL - Transmit pulse length - [7:0] - - - 0 - 255 - - - - - - - - - USERROW - User Row - 0x1300 - - - USERROW0 - User Row Byte 0 - 0x0 - - - 0 - 255 - - - - - USERROW1 - User Row Byte 1 - 0x1 - - - 0 - 255 - - - - - USERROW10 - User Row Byte 10 - 0xA - - - 0 - 255 - - - - - USERROW11 - User Row Byte 11 - 0xB - - - 0 - 255 - - - - - USERROW12 - User Row Byte 12 - 0xC - - - 0 - 255 - - - - - USERROW13 - User Row Byte 13 - 0xD - - - 0 - 255 - - - - - USERROW14 - User Row Byte 14 - 0xE - - - 0 - 255 - - - - - USERROW15 - User Row Byte 15 - 0xF - - - 0 - 255 - - - - - USERROW16 - User Row Byte 16 - 0x10 - - - 0 - 255 - - - - - USERROW17 - User Row Byte 17 - 0x11 - - - 0 - 255 - - - - - USERROW18 - User Row Byte 18 - 0x12 - - - 0 - 255 - - - - - USERROW19 - User Row Byte 19 - 0x13 - - - 0 - 255 - - - - - USERROW2 - User Row Byte 2 - 0x2 - - - 0 - 255 - - - - - USERROW20 - User Row Byte 20 - 0x14 - - - 0 - 255 - - - - - USERROW21 - User Row Byte 21 - 0x15 - - - 0 - 255 - - - - - USERROW22 - User Row Byte 22 - 0x16 - - - 0 - 255 - - - - - USERROW23 - User Row Byte 23 - 0x17 - - - 0 - 255 - - - - - USERROW24 - User Row Byte 24 - 0x18 - - - 0 - 255 - - - - - USERROW25 - User Row Byte 25 - 0x19 - - - 0 - 255 - - - - - USERROW26 - User Row Byte 26 - 0x1A - - - 0 - 255 - - - - - USERROW27 - User Row Byte 27 - 0x1B - - - 0 - 255 - - - - - USERROW28 - User Row Byte 28 - 0x1C - - - 0 - 255 - - - - - USERROW29 - User Row Byte 29 - 0x1D - - - 0 - 255 - - - - - USERROW3 - User Row Byte 3 - 0x3 - - - 0 - 255 - - - - - USERROW30 - User Row Byte 30 - 0x1E - - - 0 - 255 - - - - - USERROW31 - User Row Byte 31 - 0x1F - - - 0 - 255 - - - - - USERROW32 - User Row Byte 32 - 0x20 - - - 0 - 255 - - - - - USERROW33 - User Row Byte 33 - 0x21 - - - 0 - 255 - - - - - USERROW34 - User Row Byte 34 - 0x22 - - - 0 - 255 - - - - - USERROW35 - User Row Byte 35 - 0x23 - - - 0 - 255 - - - - - USERROW36 - User Row Byte 36 - 0x24 - - - 0 - 255 - - - - - USERROW37 - User Row Byte 37 - 0x25 - - - 0 - 255 - - - - - USERROW38 - User Row Byte 38 - 0x26 - - - 0 - 255 - - - - - USERROW39 - User Row Byte 39 - 0x27 - - - 0 - 255 - - - - - USERROW4 - User Row Byte 4 - 0x4 - - - 0 - 255 - - - - - USERROW40 - User Row Byte 40 - 0x28 - - - 0 - 255 - - - - - USERROW41 - User Row Byte 41 - 0x29 - - - 0 - 255 - - - - - USERROW42 - User Row Byte 42 - 0x2A - - - 0 - 255 - - - - - USERROW43 - User Row Byte 43 - 0x2B - - - 0 - 255 - - - - - USERROW44 - User Row Byte 44 - 0x2C - - - 0 - 255 - - - - - USERROW45 - User Row Byte 45 - 0x2D - - - 0 - 255 - - - - - USERROW46 - User Row Byte 46 - 0x2E - - - 0 - 255 - - - - - USERROW47 - User Row Byte 47 - 0x2F - - - 0 - 255 - - - - - USERROW48 - User Row Byte 48 - 0x30 - - - 0 - 255 - - - - - USERROW49 - User Row Byte 49 - 0x31 - - - 0 - 255 - - - - - USERROW5 - User Row Byte 5 - 0x5 - - - 0 - 255 - - - - - USERROW50 - User Row Byte 50 - 0x32 - - - 0 - 255 - - - - - USERROW51 - User Row Byte 51 - 0x33 - - - 0 - 255 - - - - - USERROW52 - User Row Byte 52 - 0x34 - - - 0 - 255 - - - - - USERROW53 - User Row Byte 53 - 0x35 - - - 0 - 255 - - - - - USERROW54 - User Row Byte 54 - 0x36 - - - 0 - 255 - - - - - USERROW55 - User Row Byte 55 - 0x37 - - - 0 - 255 - - - - - USERROW56 - User Row Byte 56 - 0x38 - - - 0 - 255 - - - - - USERROW57 - User Row Byte 57 - 0x39 - - - 0 - 255 - - - - - USERROW58 - User Row Byte 58 - 0x3A - - - 0 - 255 - - - - - USERROW59 - User Row Byte 59 - 0x3B - - - 0 - 255 - - - - - USERROW6 - User Row Byte 6 - 0x6 - - - 0 - 255 - - - - - USERROW60 - User Row Byte 60 - 0x3C - - - 0 - 255 - - - - - USERROW61 - User Row Byte 61 - 0x3D - - - 0 - 255 - - - - - USERROW62 - User Row Byte 62 - 0x3E - - - 0 - 255 - - - - - USERROW63 - User Row Byte 63 - 0x3F - - - 0 - 255 - - - - - USERROW7 - User Row Byte 7 - 0x7 - - - 0 - 255 - - - - - USERROW8 - User Row Byte 8 - 0x8 - - - 0 - 255 - - - - - USERROW9 - User Row Byte 9 - 0x9 - - - 0 - 255 - - - - - - - VPORTA - Virtual Ports - 0x0 - - - DIR - Data Direction - 0x0 - - - 0 - 255 - - - - - IN - Input Value - 0x2 - - - 0 - 255 - - - - - INTFLAGS - Interrupt Flags - 0x3 - - - INT - Pin Interrupt - [7:0] - - - 0 - 255 - - - - - - - OUT - Output Value - 0x1 - - - 0 - 255 - - - - - - - VPORTB - Virtual Ports - 0x4 - - - DIR - Data Direction - 0x0 - - - 0 - 255 - - - - - IN - Input Value - 0x2 - - - 0 - 255 - - - - - INTFLAGS - Interrupt Flags - 0x3 - - - INT - Pin Interrupt - [7:0] - - - 0 - 255 - - - - - - - OUT - Output Value - 0x1 - - - 0 - 255 - - - - - - - VPORTC - Virtual Ports - 0x8 - - - DIR - Data Direction - 0x0 - - - 0 - 255 - - - - - IN - Input Value - 0x2 - - - 0 - 255 - - - - - INTFLAGS - Interrupt Flags - 0x3 - - - INT - Pin Interrupt - [7:0] - - - 0 - 255 - - - - - - - OUT - Output Value - 0x1 - - - 0 - 255 - - - - - - - VPORTD - Virtual Ports - 0xC - - - DIR - Data Direction - 0x0 - - - 0 - 255 - - - - - IN - Input Value - 0x2 - - - 0 - 255 - - - - - INTFLAGS - Interrupt Flags - 0x3 - - - INT - Pin Interrupt - [7:0] - - - 0 - 255 - - - - - - - OUT - Output Value - 0x1 - - - 0 - 255 - - - - - - - VPORTE - Virtual Ports - 0x10 - - - DIR - Data Direction - 0x0 - - - 0 - 255 - - - - - IN - Input Value - 0x2 - - - 0 - 255 - - - - - INTFLAGS - Interrupt Flags - 0x3 - - - INT - Pin Interrupt - [7:0] - - - 0 - 255 - - - - - - - OUT - Output Value - 0x1 - - - 0 - 255 - - - - - - - VPORTF - Virtual Ports - 0x14 - - - DIR - Data Direction - 0x0 - - - 0 - 255 - - - - - IN - Input Value - 0x2 - - - 0 - 255 - - - - - INTFLAGS - Interrupt Flags - 0x3 - - - INT - Pin Interrupt - [7:0] - - - 0 - 255 - - - - - - - OUT - Output Value - 0x1 - - - 0 - 255 - - - - - - - VREF - Voltage reference - 0xA0 - - - CTRLA - Control A - 0x0 - - - AC0REFSEL - AC0 reference select - [2:0] - - true - - - - 0V55 - Voltage reference at 0.55V - 0 - - - 1V1 - Voltage reference at 1.1V - 1 - - - 2V5 - Voltage reference at 2.5V - 2 - - - 4V34 - Voltage reference at 4.34V - 3 - - - 1V5 - Voltage reference at 1.5V - 4 - - - AVDD - AVDD - 7 - - - - - ADC0REFSEL - ADC0 reference select - [6:4] - - true - - - - 0V55 - Voltage reference at 0.55V - 0 - - - 1V1 - Voltage reference at 1.1V - 1 - - - 2V5 - Voltage reference at 2.5V - 2 - - - 4V34 - Voltage reference at 4.34V - 3 - - - 1V5 - Voltage reference at 1.5V - 4 - - - - - - - CTRLB - Control B - 0x1 - - - AC0REFEN - AC0 DACREF reference enable - [0:0] - - - ADC0REFEN - ADC0 reference enable - [1:1] - - - - - - - WDT - Watch-Dog Timer - 0x100 - - - CTRLA - Control A - 0x0 - - - PERIOD - Period - [3:0] - - true - - - - OFF - Off - 0 - - - 8CLK - 8 cycles (8ms) - 1 - - - 16CLK - 16 cycles (16ms) - 2 - - - 32CLK - 32 cycles (32ms) - 3 - - - 64CLK - 64 cycles (64ms) - 4 - - - 128CLK - 128 cycles (0.128s) - 5 - - - 256CLK - 256 cycles (0.256s) - 6 - - - 512CLK - 512 cycles (0.512s) - 7 - - - 1KCLK - 1K cycles (1.0s) - 8 - - - 2KCLK - 2K cycles (2.0s) - 9 - - - 4KCLK - 4K cycles (4.1s) - 10 - - - 8KCLK - 8K cycles (8.2s) - 11 - - - - - WINDOW - Window - [7:4] - - true - - - - OFF - Off - 0 - - - 8CLK - 8 cycles (8ms) - 1 - - - 16CLK - 16 cycles (16ms) - 2 - - - 32CLK - 32 cycles (32ms) - 3 - - - 64CLK - 64 cycles (64ms) - 4 - - - 128CLK - 128 cycles (0.128s) - 5 - - - 256CLK - 256 cycles (0.256s) - 6 - - - 512CLK - 512 cycles (0.512s) - 7 - - - 1KCLK - 1K cycles (1.0s) - 8 - - - 2KCLK - 2K cycles (2.0s) - 9 - - - 4KCLK - 4K cycles (4.1s) - 10 - - - 8KCLK - 8K cycles (8.2s) - 11 - - - - - - - STATUS - Status - 0x1 - - - SYNCBUSY - Syncronization busy - [0:0] - read-only - - - LOCK - Lock enable - [7:7] - - - - - - - \ No newline at end of file diff --git a/misc/svd/atmega48p.svd b/misc/svd/atmega48p.svd deleted file mode 100644 index b2e2120..0000000 --- a/misc/svd/atmega48p.svd +++ /dev/null @@ -1,2944 +0,0 @@ - - Atmel - ATmega48P - 8 - 8 - read-write - 0 - 0xff - - - AC - Analog Comparator - 0x50 - - - ACSR - Analog Comparator Control And Status Register - 0x0 - read-write - - - ACIS - Analog Comparator Interrupt Mode Select - [1:0] - - true - - ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 - - - ACIC - Analog Comparator Input Capture Enable - [2:2] - - - ACIE - Analog Comparator Interrupt Enable - [3:3] - - - ACI - Analog Comparator Interrupt Flag - [4:4] - - - ACO - Analog Compare Output - [5:5] - read-only - - ACBG - Analog Comparator Bandgap Select - [6:6] - - - ACD - Analog Comparator Disable - [7:7] - - - - - DIDR1 - Digital Input Disable Register 1 - 0x2F - - - AIN0D - AIN0 Digital Input Disable - [0:0] - - - AIN1D - AIN1 Digital Input Disable - [1:1] - - - - - - - ADC - Analog-to-Digital Converter - 0x78 - - - ADC - ADC Data Register Bytes - 0x0 - 16 - - - 0 - 65535 - - - - - ADCSRA - The ADC Control and Status register A - 0x2 - read-write - - - ADPS - ADC Prescaler Select Bits - [2:0] - - true - - ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 - - - ADIE - ADC Interrupt Enable - [3:3] - - - ADIF - ADC Interrupt Flag - [4:4] - - - ADATE - ADC Auto Trigger Enable - [5:5] - - - ADSC - ADC Start Conversion - [6:6] - - - ADEN - ADC Enable - [7:7] - - - - - ADCSRB - The ADC Control and Status register B - 0x3 - - - ADTS - ADC Auto Trigger Source bits - [2:0] - - true - - - - VAL_0x00 - Free Running mode - 0 - - - VAL_0x01 - Analog Comparator - 1 - - - VAL_0x02 - External Interrupt Request 0 - 2 - - - VAL_0x03 - Timer/Counter0 Compare Match A - 3 - - - VAL_0x04 - Timer/Counter0 Overflow - 4 - - - VAL_0x05 - Timer/Counter1 Compare Match B - 5 - - - VAL_0x06 - Timer/Counter1 Overflow - 6 - - - VAL_0x07 - Timer/Counter1 Capture Event - 7 - - - - - ACME - <TBD> - [6:6] - - - - - ADMUX - The ADC multiplexer Selection Register - 0x4 - - - MUX - Analog Channel Selection Bits - [3:0] - - true - - - - ADC0 - ADC Single Ended Input pin 0 - 0 - - - ADC1 - ADC Single Ended Input pin 1 - 1 - - - ADC2 - ADC Single Ended Input pin 2 - 2 - - - ADC3 - ADC Single Ended Input pin 3 - 3 - - - ADC4 - ADC Single Ended Input pin 4 - 4 - - - ADC5 - ADC Single Ended Input pin 5 - 5 - - - ADC6 - ADC Single Ended Input pin 6 - 6 - - - ADC7 - ADC Single Ended Input pin 7 - 7 - - - TEMPSENS - Temperature sensor - 8 - - - ADC_VBG - Internal Reference (VBG) - 14 - - - ADC_GND - 0V (GND) - 15 - - - - - ADLAR - Left Adjust Result - [5:5] - - - REFS - Reference Selection Bits - [7:6] - - true - - REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 - - - - - DIDR0 - Digital Input Disable Register - 0x6 - - - ADC0D - <TBD> - [0:0] - - - ADC1D - <TBD> - [1:1] - - - ADC2D - <TBD> - [2:2] - - - ADC3D - <TBD> - [3:3] - - - ADC4D - <TBD> - [4:4] - - - ADC5D - <TBD> - [5:5] - - - - - - - CPU - CPU Registers - 0x3E - - RESET - External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset - 0 - - - INT0 - External Interrupt Request 0 - 1 - - - INT1 - External Interrupt Request 1 - 2 - - - PCINT0 - Pin Change Interrupt Request 0 - 3 - - - PCINT1 - Pin Change Interrupt Request 0 - 4 - - - PCINT2 - Pin Change Interrupt Request 1 - 5 - - - WDT - Watchdog Time-out Interrupt - 6 - - - TIMER2_COMPA - Timer/Counter2 Compare Match A - 7 - - - TIMER2_COMPB - Timer/Counter2 Compare Match A - 8 - - - TIMER2_OVF - Timer/Counter2 Overflow - 9 - - - TIMER1_CAPT - Timer/Counter1 Capture Event - 10 - - - TIMER1_COMPA - Timer/Counter1 Compare Match A - 11 - - - TIMER1_COMPB - Timer/Counter1 Compare Match B - 12 - - - TIMER1_OVF - Timer/Counter1 Overflow - 13 - - - TIMER0_COMPA - TimerCounter0 Compare Match A - 14 - - - TIMER0_COMPB - TimerCounter0 Compare Match B - 15 - - - TIMER0_OVF - Timer/Couner0 Overflow - 16 - - - SPI_STC - SPI Serial Transfer Complete - 17 - - - USART_RX - USART Rx Complete - 18 - - - USART_UDRE - USART, Data Register Empty - 19 - - - USART_TX - USART Tx Complete - 20 - - - ADC - ADC Conversion Complete - 21 - - - EE_READY - EEPROM Ready - 22 - - - ANALOG_COMP - Analog Comparator - 23 - - - TWI - Two-wire Serial Interface - 24 - - - SPM_Ready - Store Program Memory Read - 25 - - - - CLKPR - Clock Prescale Register - 0x23 - read-only - - - CLKPS - Clock Prescaler Select Bits - [3:0] - - true - - - - VAL_0x00 - 1 - 0 - - - VAL_0x01 - 2 - 1 - - - VAL_0x02 - 4 - 2 - - - VAL_0x03 - 8 - 3 - - - VAL_0x04 - 16 - 4 - - - VAL_0x05 - 32 - 5 - - - VAL_0x06 - 64 - 6 - - - VAL_0x07 - 128 - 7 - - - VAL_0x08 - 256 - 8 - - - - - CLKPCE - Clock Prescaler Change Enable - [7:7] - - - - - GPIOR0 - General Purpose I/O Register 0 - 0x0 - - - 0 - 255 - - - - - GPIOR1 - General Purpose I/O Register 1 - 0xC - - - 0 - 255 - - - - - GPIOR2 - General Purpose I/O Register 2 - 0xD - - - 0 - 255 - - - - - MCUCR - MCU Control Register - 0x17 - - - PUD - <TBD> - [4:4] - - - BODSE - BOD Sleep Enable - [5:5] - - - BODS - BOD Sleep - [6:6] - - - - - MCUSR - MCU Status Register - 0x16 - - - PORF - Power-on reset flag - [0:0] - - - EXTRF - External Reset Flag - [1:1] - - - BORF - Brown-out Reset Flag - [2:2] - - - WDRF - Watchdog Reset Flag - [3:3] - - - - - OSCCAL - Oscillator Calibration Value - 0x28 - read-only - - - OSCCAL - Oscillator Calibration - [7:0] - - - 0 - 255 - - - - - - - PRR - Power Reduction Register - 0x26 - read-only - - - PRADC - Power Reduction ADC - [0:0] - - - PRUSART0 - Power Reduction USART - [1:1] - - - PRSPI - Power Reduction Serial Peripheral Interface - [2:2] - - - PRTIM1 - Power Reduction Timer/Counter1 - [3:3] - - - PRTIM0 - Power Reduction Timer/Counter0 - [5:5] - - - PRTIM2 - Power Reduction Timer/Counter2 - [6:6] - - - PRTWI - Power Reduction TWI - [7:7] - - - - - SMCR - Sleep Mode Control Register - 0x15 - - - SE - Sleep Enable - [0:0] - - - SM - Sleep Mode Select Bits - [3:1] - - true - - - - IDLE - Idle - 0 - - - ADC - ADC Noise Reduction (If Available) - 1 - - - PDOWN - Power Down - 2 - - - PSAVE - Power Save - 3 - - - VAL_0x04 - Reserved - 4 - - - VAL_0x05 - Reserved - 5 - - - STDBY - Standby - 6 - - - ESTDBY - Extended Standby - 7 - - - - - - - SPMCSR - Store Program Memory Control and Status Register - 0x19 - - - SELFPRGEN - Self Programming Enable - [0:0] - - - PGERS - Page Erase - [1:1] - - - PGWRT - Page Write - [2:2] - - - BLBSET - Boot Lock Bit Set - [3:3] - - - RWWSRE - Read-While-Write section read enable - [4:4] - - - RWWSB - Read-While-Write Section Busy - [6:6] - - - SPMIE - SPM Interrupt Enable - [7:7] - - - - - - - EEPROM - EEPROM - 0x3F - - - EEARL - EEPROM Address Register Low Byte - 0x2 - - - 0 - 255 - - - - - EECR - EEPROM Control Register - 0x0 - - - EERE - EEPROM Read Enable - [0:0] - - - EEPE - EEPROM Write Enable - [1:1] - - - EEMPE - EEPROM Master Write Enable - [2:2] - - - EERIE - EEPROM Ready Interrupt Enable - [3:3] - - - EEPM - EEPROM Programming Mode Bits - [5:4] - - true - - - - VAL_0x00 - Erase and Write in one operation - 0 - - - VAL_0x01 - Erase Only - 1 - - - VAL_0x02 - Write Only - 2 - - - - - - - EEDR - EEPROM Data Register - 0x1 - - - 0 - 255 - - - - - - - EXINT - External Interrupts - 0x3B - - - EICRA - External Interrupt Control Register - 0x2E - - - ISC0 - External Interrupt Sense Control 0 Bits - [1:0] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC1 - External Interrupt Sense Control 1 Bits - [3:2] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - - - EIFR - External Interrupt Flag Register - 0x1 - read-only - - - INTF - External Interrupt Flags - [1:0] - - - 0 - 3 - - - - - - - EIMSK - External Interrupt Mask Register - 0x2 - - - INT - External Interrupt Request 1 Enable - [1:0] - - - 0 - 3 - - - - - - - PCICR - Pin Change Interrupt Control Register - 0x2D - - - PCIE - Pin Change Interrupt Enables - [2:0] - - - 0 - 7 - - - - - - - PCIFR - Pin Change Interrupt Flag Register - 0x0 - read-only - - - PCIF - Pin Change Interrupt Flags - [2:0] - - - 0 - 7 - - - - - - - PCMSK0 - Pin Change Mask Register 0 - 0x30 - - - PCINT - Pin Change Enable Masks - [7:0] - - - 0 - 255 - - - - - - - PCMSK1 - Pin Change Mask Register 1 - 0x31 - - - PCINT - Pin Change Enable Masks - [6:0] - - - 0 - 127 - - - - - - - PCMSK2 - Pin Change Mask Register 2 - 0x32 - - - PCINT - Pin Change Enable Masks - [7:0] - - - 0 - 255 - - - - - - - - - FUSE - Fuses - 0x0 - - - EXTENDED - <TBD> - 0x2 - - - SELFPRGEN - Self Programming enable - [0:0] - - - - - HIGH - <TBD> - 0x1 - - - BODLEVEL - Brown-out Detector trigger level - [2:0] - - true - - - - 4V3 - Brown-out detection at VCC=4.3 V - 4 - - - 2V7 - Brown-out detection at VCC=2.7 V - 5 - - - 1V8 - Brown-out detection at VCC=1.8 V - 6 - - - DISABLED - Brown-out detection disabled - 7 - - - - - EESAVE - Preserve EEPROM through the Chip Erase cycle - [3:3] - - - WDTON - Watch-dog Timer always on - [4:4] - - - SPIEN - Serial program downloading (SPI) enabled - [5:5] - - - DWEN - Debug Wire enable - [6:6] - - - RSTDISBL - Reset Disabled (Enable PC6 as i/o pin) - [7:7] - - - - - LOW - <TBD> - 0x0 - - - SUT_CKSEL - Select Clock Source - [5:0] - - true - - - - EXTCLK_6CK_14CK_0MS - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 0 - - - INTRCOSC_8MHZ_6CK_14CK_0MS - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 2 - - - INTRCOSC_128KHZ_6CK_14CK_0MS - Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 3 - - - EXTLOFXTAL_1KCK_14CK_0MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms - 4 - - - EXTLOFXTAL_32KCK_14CK_0MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms - 5 - - - EXTFSXTAL_258CK_14CK_4MS1 - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 6 - - - EXTFSXTAL_1KCK_14CK_65MS - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 7 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 8 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 9 - - - EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 10 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 11 - - - EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 12 - - - EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 13 - - - EXTXOSC_8MHZ_XX_258CK_14CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 14 - - - EXTXOSC_8MHZ_XX_1KCK_14CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 15 - - - EXTCLK_6CK_14CK_4MS1 - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - 16 - - - INTRCOSC_8MHZ_6CK_14CK_4MS1 - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - 18 - - - INTRCOSC_128KHZ_6CK_14CK_4MS1 - Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - 19 - - - EXTLOFXTAL_1KCK_14CK_4MS1 - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms - 20 - - - EXTLOFXTAL_32KCK_14CK_4MS1 - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms - 21 - - - EXTFSXTAL_258CK_14CK_65MS - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 22 - - - EXTFSXTAL_16KCK_14CK_0MS - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 23 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 24 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 25 - - - EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 26 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 27 - - - EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 28 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 29 - - - EXTXOSC_8MHZ_XX_258CK_14CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 30 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 31 - - - EXTCLK_6CK_14CK_65MS - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms - 32 - - - INTRCOSC_8MHZ_6CK_14CK_65MS_DEFAULT - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; default value - 34 - - - INTRCOSC_128KHZ_6CK_14CK_65MS - Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms - 35 - - - EXTLOFXTAL_1KCK_14CK_65MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms - 36 - - - EXTLOFXTAL_32KCK_14CK_65MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms - 37 - - - EXTFSXTAL_1KCK_14CK_0MS - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 38 - - - EXTFSXTAL_16KCK_14CK_4MS1 - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 39 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 40 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 41 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 42 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 43 - - - EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 44 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 45 - - - EXTXOSC_8MHZ_XX_1KCK_14CK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 46 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 47 - - - EXTFSXTAL_1KCK_14CK_4MS1 - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 54 - - - EXTFSXTAL_16KCK_14CK_65MS - Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 55 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 56 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 57 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 58 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 59 - - - EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 60 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 61 - - - EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 62 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 63 - - - - - CKOUT - Clock output on PORTB0 - [6:6] - - - CKDIV8 - Divide clock by 8 internally - [7:7] - - - - - - - LOCKBIT - Lockbits - 0x0 - - - LOCKBIT - <TBD> - 0x0 - - - LB - Memory Lock - [1:0] - - true - - - - PROG_VER_DISABLED - Further programming and verification disabled - 0 - - - PROG_DISABLED - Further programming disabled - 2 - - - NO_LOCK - No memory lock features enabled - 3 - - - - - - - - - PORTB - I/O Port - 0x23 - - - DDRB - Port B Data Direction Register - 0x1 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PINB - Port B Input Pins - 0x0 - read-write - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PORTB - Port B Data Register - 0x2 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - - - PORTC - I/O Port - 0x26 - - - DDRC - Port C Data Direction Register - 0x1 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - - - PINC - Port C Input Pins - 0x0 - read-write - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - - - PORTC - Port C Data Register - 0x2 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - - - - - PORTD - I/O Port - 0x29 - - - DDRD - Port D Data Direction Register - 0x1 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PIND - Port D Input Pins - 0x0 - read-write - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PORTD - Port D Data Register - 0x2 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - - - SPI - Serial Peripheral Interface - 0x4C - - - SPCR - SPI Control Register - 0x0 - - - SPR - SPI Clock Rate Selects - [1:0] - - true - - SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 - - - CPHA - Clock Phase - [2:2] - - - CPOL - Clock polarity - [3:3] - - - MSTR - Master/Slave Select - [4:4] - - - DORD - Data Order - [5:5] - - - SPE - SPI Enable - [6:6] - - - SPIE - SPI Interrupt Enable - [7:7] - - - - - SPDR - SPI Data Register - 0x2 - - - 0 - 255 - - - - - SPSR - SPI Status Register - 0x1 - read-write - - - SPI2X - Double SPI Speed Bit - [0:0] - read-write - - WCOL - Write Collision Flag - [6:6] - read-only - - SPIF - SPI Interrupt Flag - [7:7] - read-only - - - - - - TC0 - Timer/Counter, 8-bit - 0x35 - - - GTCCR - General Timer/Counter Control Register - 0xE - - - PSRSYNC - Prescaler Reset Timer/Counter1 and Timer/Counter0 - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - OCR0A - Timer/Counter0 Output Compare Register - 0x12 - - - 0 - 255 - - - - - OCR0B - Timer/Counter0 Output Compare Register - 0x13 - - - 0 - 255 - - - - - TCCR0A - Timer/Counter Control Register A - 0xF - - - WGM0 - Waveform Generation Mode - [1:0] - - true - WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 - - - COM0B - Compare Output B Mode - [5:4] - - true - COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 - - - COM0A - Compare Output A Mode - [7:6] - - true - - - - - - TCCR0B - Timer/Counter Control Register B - 0x10 - - - CS0 - Clock Select - [2:0] - - true - - CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM02 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) - [3:3] - - - FOC0B - Force Output Compare B - [6:6] - write-only - - FOC0A - Force Output Compare A - [7:7] - write-only - - - - TCNT0 - Timer/Counter0 - 0x11 - - - 0 - 255 - - - - - TIFR0 - Timer/Counter0 Interrupt Flag register - 0x0 - read-write - - - TOV0 - Timer/Counter0 Overflow Flag - [0:0] - - - OCF0A - Timer/Counter0 Output Compare Flag 0A - [1:1] - - - OCF0B - Timer/Counter0 Output Compare Flag 0B - [2:2] - - - - - TIMSK0 - Timer/Counter0 Interrupt Mask Register - 0x39 - - - TOIE0 - Timer/Counter0 Overflow Interrupt Enable - [0:0] - - - OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable - [2:2] - - - - - - - TC1 - Timer/Counter, 16-bit - 0x36 - - - GTCCR - General Timer/Counter Control Register - 0xD - - - PSRSYNC - Prescaler Reset Timer/Counter1 and Timer/Counter0 - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - ICR1 - Timer/Counter1 Input Capture Register Bytes - 0x50 - 16 - - - 0 - 65535 - - - - - OCR1A - Timer/Counter1 Output Compare Register Bytes - 0x52 - 16 - - - 0 - 65535 - - - - - OCR1B - Timer/Counter1 Output Compare Register Bytes - 0x54 - 16 - - - 0 - 65535 - - - - - TCCR1A - Timer/Counter1 Control Register A - 0x4A - - - WGM1 - Waveform Generation Mode - [1:0] - - - 0 - 3 - - - - - COM1B - Compare Output Mode 1B, bits - [5:4] - - true - COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM1A - Compare Output Mode 1A, bits - [7:6] - - true - - - - - - TCCR1B - Timer/Counter1 Control Register B - 0x4B - - - CS1 - Prescaler source of Timer/Counter 1 - [2:0] - - true - CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM1 - Waveform Generation Mode - [4:3] - - - 0 - 3 - - - - - ICES1 - Input Capture 1 Edge Select - [6:6] - - - ICNC1 - Input Capture 1 Noise Canceler - [7:7] - - - - - TCCR1C - Timer/Counter1 Control Register C - 0x4C - - - FOC1B - <TBD> - [6:6] - write-only - - FOC1A - <TBD> - [7:7] - write-only - - - - TCNT1 - Timer/Counter1 Bytes - 0x4E - 16 - - - 0 - 65535 - - - - - TIFR1 - Timer/Counter Interrupt Flag register - 0x0 - read-write - - - TOV1 - Timer/Counter1 Overflow Flag - [0:0] - - - OCF1A - Output Compare Flag 1A - [1:1] - - - OCF1B - Output Compare Flag 1B - [2:2] - - - ICF1 - Input Capture Flag 1 - [5:5] - - - - - TIMSK1 - Timer/Counter Interrupt Mask Register - 0x39 - - - TOIE1 - Timer/Counter1 Overflow Interrupt Enable - [0:0] - - - OCIE1A - Timer/Counter1 Output CompareA Match Interrupt Enable - [1:1] - - - OCIE1B - Timer/Counter1 Output CompareB Match Interrupt Enable - [2:2] - - - ICIE1 - Timer/Counter1 Input Capture Interrupt Enable - [5:5] - - - - - - - TC2 - Timer/Counter, 8-bit Async - 0x37 - - - ASSR - Asynchronous Status Register - 0x7F - - - TCR2BUB - Timer/Counter Control Register2 Update Busy - [0:0] - - - TCR2AUB - Timer/Counter Control Register2 Update Busy - [1:1] - - - OCR2BUB - Output Compare Register 2 Update Busy - [2:2] - - - OCR2AUB - Output Compare Register2 Update Busy - [3:3] - - - TCN2UB - Timer/Counter2 Update Busy - [4:4] - - - AS2 - Asynchronous Timer/Counter2 - [5:5] - - - EXCLK - Enable External Clock Input - [6:6] - - - - - GTCCR - General Timer Counter Control register - 0xC - - - PSRASY - Prescaler Reset Timer/Counter2 - [1:1] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - OCR2A - Timer/Counter2 Output Compare Register A - 0x7C - - - 0 - 255 - - - - - OCR2B - Timer/Counter2 Output Compare Register B - 0x7D - - - 0 - 255 - - - - - TCCR2A - Timer/Counter2 Control Register A - 0x79 - - - WGM2 - Waveform Genration Mode - [1:0] - - true - WGM2read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 - - - COM2B - Compare Output B Mode - [5:4] - - true - COM2Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 - - - COM2A - Compare Output A Mode - [7:6] - - true - - - - - - TCCR2B - Timer/Counter2 Control Register B - 0x7A - - - CS2 - Clock Select bits - [2:0] - - true - - CS2read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_32Running, CLK/323PRESCALE_64Running, CLK/644PRESCALE_128Running, CLK/1285PRESCALE_256Running, CLK/2566PRESCALE_1024Running, CLK/10247 - - - WGM22 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) - [3:3] - - - FOC2B - Force Output Compare B - [6:6] - write-only - - FOC2A - Force Output Compare A - [7:7] - write-only - - - - TCNT2 - Timer/Counter2 - 0x7B - - - 0 - 255 - - - - - TIFR2 - Timer/Counter Interrupt Flag Register - 0x0 - read-write - - - TOV2 - Timer/Counter2 Overflow Flag - [0:0] - - - OCF2A - Output Compare Flag 2A - [1:1] - - - OCF2B - Output Compare Flag 2B - [2:2] - - - - - TIMSK2 - Timer/Counter Interrupt Mask register - 0x39 - - - TOIE2 - Timer/Counter2 Overflow Interrupt Enable - [0:0] - - - OCIE2A - Timer/Counter2 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE2B - Timer/Counter2 Output Compare Match B Interrupt Enable - [2:2] - - - - - - - TWI - Two Wire Serial Interface - 0xB8 - - - TWAMR - TWI (Slave) Address Mask Register - 0x5 - - - TWAM - TWI (Slave) Address Mask Bits - [7:1] - - - 0 - 127 - - - - - - - TWAR - TWI (Slave) Address register - 0x2 - - - TWGCE - TWI General Call Recognition Enable Bit - [0:0] - - - TWA - TWI (Slave) Address register Bits - [7:1] - - - 0 - 127 - - - - - - - TWBR - TWI Bit Rate register - 0x0 - - - 0 - 255 - - - - - TWCR - TWI Control Register - 0x4 - read-write - - - TWIE - TWI Interrupt Enable - [0:0] - - - TWEN - TWI Enable Bit - [2:2] - - - TWWC - TWI Write Collition Flag - [3:3] - read-only - - TWSTO - TWI Stop Condition Bit - [4:4] - - - TWSTA - TWI Start Condition Bit - [5:5] - - - TWEA - TWI Enable Acknowledge Bit - [6:6] - - - TWINT - TWI Interrupt Flag - [7:7] - - - - - TWDR - TWI Data register - 0x3 - - - 0 - 255 - - - - - TWSR - TWI Status Register - 0x1 - - - TWPS - TWI Prescaler - [1:0] - - true - - TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 - - - TWS - TWI Status - [7:3] - read-only - - 0 - 31 - - - - - - - - - USART0 - USART - 0xC0 - - - UBRR0 - USART Baud Rate Register Bytes - 0x4 - 16 - - - 0 - 65535 - - - - - UCSR0A - USART Control and Status Register A - 0x0 - read-write - - - MPCM0 - Multi-processor Communication Mode - [0:0] - - - U2X0 - Double the USART transmission speed - [1:1] - - - UPE0 - Parity Error - [2:2] - read-only - - DOR0 - Data overRun - [3:3] - read-only - - FE0 - Framing Error - [4:4] - read-only - - UDRE0 - USART Data Register Empty - [5:5] - read-only - - TXC0 - USART Transmit Complete - [6:6] - - - RXC0 - USART Receive Complete - [7:7] - read-only - - - - UCSR0B - USART Control and Status Register B - 0x1 - - - TXB80 - Transmit Data Bit 8 - [0:0] - - - RXB80 - Receive Data Bit 8 - [1:1] - read-only - - UCSZ02 - Character Size - together with UCSZ0 in UCSR0C - [2:2] - - - TXEN0 - Transmitter Enable - [3:3] - - - RXEN0 - Receiver Enable - [4:4] - - - UDRIE0 - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE0 - TX Complete Interrupt Enable - [6:6] - - - RXCIE0 - RX Complete Interrupt Enable - [7:7] - - - - - UCSR0C - USART Control and Status Register C - 0x2 - - - UCPOL0 - Clock Polarity - [0:0] - UCPOL0read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 - - - UCSZ0 - Character Size - together with UCSZ2 in UCSR0B - [2:1] - - - 0 - 3 - - - UCSZ0read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 - - - USBS0 - Stop Bit Select - [3:3] - - true - - USBS0read-writeSTOP11-bit0STOP22-bit1 - - - UPM0 - Parity Mode Bits - [5:4] - - true - - UPM0read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 - - - UMSEL0 - USART Mode Select - [7:6] - - true - - UMSEL0read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 - - - - - UDR0 - USART I/O Data Register - 0x6 - - - 0 - 255 - - - - - - - WDT - Watchdog Timer - 0x60 - - - WDTCSR - Watchdog Timer Control Register - 0x0 - read-write - - - WDE - Watch Dog Enable - [3:3] - - - WDCE - Watchdog Change Enable - [4:4] - - - WDIE - Watchdog Timeout Interrupt Enable - [6:6] - - - WDIF - Watchdog Timeout Interrupt Flag - [7:7] - - WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 - - WDPHWatchdog Timer Prescaler - High Bit[5:5] - - - - - - \ No newline at end of file diff --git a/misc/svd/atmega64.svd b/misc/svd/atmega64.svd deleted file mode 100644 index 60a69bf..0000000 --- a/misc/svd/atmega64.svd +++ /dev/null @@ -1,4326 +0,0 @@ - - Atmel - ATmega64 - 8 - 8 - read-write - 0 - 0xff - - - AC - Analog Comparator - 0x28 - - - ACSR - Analog Comparator Control And Status Register - 0x0 - read-write - - - ACIS - Analog Comparator Interrupt Mode Select - [1:0] - - true - - ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 - - - ACIC - Analog Comparator Input Capture Enable - [2:2] - - - ACIE - Analog Comparator Interrupt Enable - [3:3] - - - ACI - Analog Comparator Interrupt Flag - [4:4] - - - ACO - Analog Compare Output - [5:5] - read-only - - ACBG - Analog Comparator Bandgap Select - [6:6] - - - ACD - Analog Comparator Disable - [7:7] - - - - - SFIOR - Special Function IO Register - 0x18 - - - ACME - Analog Comparator Multiplexer Enable - [3:3] - - - - - - - ADC - Analog-to-Digital Converter - 0x24 - - - ADC - ADC Data Register Bytes - 0x0 - 16 - - - 0 - 65535 - - - - - ADCSRA - The ADC Control and Status register A - 0x2 - read-write - - - ADPS - ADC Prescaler Select Bits - [2:0] - - true - - ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 - - - ADIE - ADC Interrupt Enable - [3:3] - - - ADIF - ADC Interrupt Flag - [4:4] - - - ADATE - ADC Auto Trigger Enable - [5:5] - - - ADSC - ADC Start Conversion - [6:6] - - - ADEN - ADC Enable - [7:7] - - - - - ADCSRB - The ADC Control and Status register B - 0x6A - - - ADTS - ADC Auto Trigger Source bits - [2:0] - - true - - - - VAL_0x00 - Free Running mode - 0 - - - VAL_0x01 - Analog Comparator - 1 - - - VAL_0x02 - External Interrupt Request 0 - 2 - - - VAL_0x03 - Timer/Counter0 Compare Match A - 3 - - - VAL_0x04 - Timer/Counter0 Overflow - 4 - - - VAL_0x05 - Timer/Counter1 Compare Match B - 5 - - - VAL_0x06 - Timer/Counter1 Overflow - 6 - - - VAL_0x07 - Timer/Counter1 Capture Event - 7 - - - - - - - ADMUX - The ADC multiplexer Selection Register - 0x3 - - - MUX - Analog Channel and Gain Selection Bits - [4:0] - - - 0 - 31 - - - - - ADLAR - Left Adjust Result - [5:5] - - - REFS - Reference Selection Bits - [7:6] - - true - - REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 - - - - - - - BOOT_LOAD - Bootloader - 0x68 - - - SPMCSR - Store Program Memory Control Register - 0x0 - - - SPMEN - Store Program Memory Enable - [0:0] - - - PGERS - Page Erase - [1:1] - - - PGWRT - Page Write - [2:2] - - - BLBSET - Boot Lock Bit Set - [3:3] - - - RWWSRE - Read While Write section read enable - [4:4] - - - RWWSB - Read While Write Section Busy - [6:6] - - - SPMIE - SPM Interrupt Enable - [7:7] - - - - - - - CPU - CPU Registers - 0x54 - - RESET - External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset - 0 - - - INT0 - External Interrupt Request 0 - 1 - - - INT1 - External Interrupt Request 1 - 2 - - - INT2 - External Interrupt Request 2 - 3 - - - INT3 - External Interrupt Request 3 - 4 - - - INT4 - External Interrupt Request 4 - 5 - - - INT5 - External Interrupt Request 5 - 6 - - - INT6 - External Interrupt Request 6 - 7 - - - INT7 - External Interrupt Request 7 - 8 - - - TIMER2_COMP - Timer/Counter2 Compare Match - 9 - - - TIMER2_OVF - Timer/Counter2 Overflow - 10 - - - TIMER1_CAPT - Timer/Counter1 Capture Event - 11 - - - TIMER1_COMPA - Timer/Counter1 Compare Match A - 12 - - - TIMER1_COMPB - Timer/Counter Compare Match B - 13 - - - TIMER1_OVF - Timer/Counter1 Overflow - 14 - - - TIMER0_COMP - Timer/Counter0 Compare Match - 15 - - - TIMER0_OVF - Timer/Counter0 Overflow - 16 - - - SPI_STC - SPI Serial Transfer Complete - 17 - - - USART0_RX - USART0, Rx Complete - 18 - - - USART0_UDRE - USART0 Data Register Empty - 19 - - - USART0_TX - USART0, Tx Complete - 20 - - - ADC - ADC Conversion Complete - 21 - - - EE_READY - EEPROM Ready - 22 - - - ANALOG_COMP - Analog Comparator - 23 - - - TIMER1_COMPC - Timer/Counter1 Compare Match C - 24 - - - TIMER3_CAPT - Timer/Counter3 Capture Event - 25 - - - TIMER3_COMPA - Timer/Counter3 Compare Match A - 26 - - - TIMER3_COMPB - Timer/Counter3 Compare Match B - 27 - - - TIMER3_COMPC - Timer/Counter3 Compare Match C - 28 - - - TIMER3_OVF - Timer/Counter3 Overflow - 29 - - - USART1_RX - USART1, Rx Complete - 30 - - - USART1_UDRE - USART1, Data Register Empty - 31 - - - USART1_TX - USART1, Tx Complete - 32 - - - TWI - 2-wire Serial Interface - 33 - - - SPM_READY - Store Program Memory Read - 34 - - - - MCUCR - MCU Control Register - 0x1 - - - IVCE - Interrupt Vector Change Enable - [0:0] - - - IVSEL - Interrupt Vector Select - [1:1] - - - SM2 - Sleep Mode Select - [2:2] - - true - - - - IDLE - Idle - 0 - - - - - SM - Sleep Mode Select - [4:3] - - - 0 - 3 - - - - - SE - Sleep Enable - [5:5] - - - SRW10 - External SRAM Wait State Select - [6:6] - - - SRE - External SRAM Enable - [7:7] - - - - - MCUCSR - MCU Control And Status Register - 0x0 - - - PORF - Power-on reset flag - [0:0] - - - EXTRF - External Reset Flag - [1:1] - - - BORF - Brown-out Reset Flag - [2:2] - - - WDRF - Watchdog Reset Flag - [3:3] - - - JTRF - JTAG Reset Flag - [4:4] - - - JTD - JTAG Interface Disable - [7:7] - - - - - OSCCAL - Oscillator Calibration Value - 0x1B - - - OSCCAL - Oscillator Calibration - [7:0] - - - 0 - 255 - - - - - - - XDIV - XTAL Divide Control Register - 0x8 - - - XDIV - XTAl Divide Select Bits - [6:0] - - - 0 - 127 - - - - - XDIVEN - XTAL Divide Enable - [7:7] - - - - - XMCRA - External Memory Control Register A - 0x19 - - - SRW11 - Wait state select bit upper page - [1:1] - - - SRW0 - Wait state select bit lower page - [3:2] - - true - - - - VAL_0x00 - No wait-states - 0 - - - VAL_0x01 - Wait one cycle during read/write strobe - 1 - - - VAL_0x02 - Wait two cycles during read/write strobe - 2 - - - VAL_0x03 - Wait two cycles during read/write and wait one cycle before driving out new address - 3 - - - - - SRL - Wait state page limit - [6:4] - - true - - - - VAL_0x00 - LS = N/A, US = 0x1100 - 0xFFFF - 0 - - - VAL_0x01 - LS = 0x1100 - 0x1FFF, US = 0x2000 - 0xFFFF - 1 - - - VAL_0x02 - LS = 0x1100 - 0x3FFF, US = 0x4000 - 0xFFFF - 2 - - - VAL_0x03 - LS = 0x1100 - 0x5FFF, US = 0x6000 - 0xFFFF - 3 - - - VAL_0x04 - LS = 0x1100 - 0x7FFF, US = 0x8000 - 0xFFFF - 4 - - - VAL_0x05 - LS = 0x1100 - 0x9FFF, US = 0xA000 - 0xFFFF - 5 - - - VAL_0x06 - LS = 0x1100 - 0xBFFF, US = 0xC000 - 0xFFFF - 6 - - - VAL_0x07 - LS = 0x1100 - 0xDFFF, US = 0xE000 - 0xFFFF - 7 - - - - - - - XMCRB - External Memory Control Register B - 0x18 - - - XMM - External Memory High Mask - [2:0] - - - 0 - 7 - - - - - XMBK - External Memory Bus Keeper Enable - [7:7] - - - - - - - EEPROM - EEPROM - 0x3C - - - EEAR - EEPROM Read/Write Access Bytes - 0x2 - 16 - - - 0 - 65535 - - - - - EECR - EEPROM Control Register - 0x0 - - - EERE - EEPROM Read Enable - [0:0] - - - EEWE - EEPROM Write Enable - [1:1] - - - EEMWE - EEPROM Master Write Enable - [2:2] - - - EERIE - EEPROM Ready Interrupt Enable - [3:3] - - - - - EEDR - EEPROM Data Register - 0x1 - - - 0 - 255 - - - - - - - EXINT - External Interrupts - 0x58 - - - EICRA - External Interrupt Control Register A - 0x12 - - - ISC0 - External Interrupt Sense Control Bit - [1:0] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC1 - External Interrupt Sense Control Bit - [3:2] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC2 - External Interrupt Sense Control Bit - [5:4] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC3 - External Interrupt Sense Control Bit - [7:6] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - - - EICRB - External Interrupt Control Register B - 0x2 - - - ISC4 - External Interrupt 7-4 Sense Control Bit - [1:0] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC5 - External Interrupt 7-4 Sense Control Bit - [3:2] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC6 - External Interrupt 7-4 Sense Control Bit - [5:4] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC7 - External Interrupt 7-4 Sense Control Bit - [7:6] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - - - EIFR - External Interrupt Flag Register - 0x0 - read-only - - - INTF - External Interrupt Flags - [7:0] - - - 0 - 255 - - - - - - - EIMSK - External Interrupt Mask Register - 0x1 - - - INT - External Interrupt Request 7 Enable - [7:0] - - - 0 - 255 - - - - - - - - - FUSE - Fuses - 0x0 - - - EXTENDED - <TBD> - 0x2 - - - WDTON - Watchdog Timer always on - [0:0] - - - M103C - ATmega103 Compatibility Mode - [1:1] - - - - - HIGH - <TBD> - 0x1 - - - BOOTRST - Boot Reset vector Enabled - [0:0] - - - BOOTSZ - Select Boot Size - [2:1] - - true - - - - 4096W_7000 - Boot Flash size=4096 words Boot address=$7000 - 0 - - - 2048W_7800 - Boot Flash size=2048 words Boot address=$7800 - 1 - - - 1024W_7C00 - Boot Flash size=1024 words Boot address=$7C00 - 2 - - - 512W_7E00 - Boot Flash size=512 words Boot address=$7E00 - 3 - - - - - EESAVE - Preserve EEPROM through the Chip Erase cycle - [3:3] - - - CKOPT - CKOPT fuse (operation dependent of CKSEL fuses) - [4:4] - - - SPIEN - Serial program downloading (SPI) enabled - [5:5] - - - JTAGEN - JTAG Interface Enabled - [6:6] - - - OCDEN - On-Chip Debug Enabled - [7:7] - - - - - LOW - <TBD> - 0x0 - - - SUT_CKSEL - Select Clock Source - [5:0] - - true - - - - EXTCLK_6CK_0MS - Ext. Clock; Start-up time: 6 CK + 0 ms - 0 - - - INTRCOSC_1MHZ_6CK_0MS - Int. RC Osc. 1 MHz; Start-up time: 6 CK + 0 ms - 1 - - - INTRCOSC_2MHZ_6CK_0MS - Int. RC Osc. 2 MHz; Start-up time: 6 CK + 0 ms - 2 - - - INTRCOSC_4MHZ_6CK_0MS - Int. RC Osc. 4 MHz; Start-up time: 6 CK + 0 ms - 3 - - - INTRCOSC_8MHZ_6CK_0MS - Int. RC Osc. 8 MHz; Start-up time: 6 CK + 0 ms - 4 - - - EXTRCOSC_XX_0MHZ9_18CK_0MS - Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 0 ms - 5 - - - EXTRCOSC_0MHZ9_3MHZ_18CK_0MS - Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 0 ms - 6 - - - EXTRCOSC_3MHZ_8MHZ_18CK_0MS - Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 0 ms - 7 - - - EXTRCOSC_8MHZ_12MHZ_18CK_0MS - Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 0 ms - 8 - - - EXTLOFXTAL_1KCK_4MS - Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4 ms - 9 - - - EXTLOFXTALRES_258CK_4MS - Ext. Crystal/Resonator Low Freq.; Start-up time: 258 CK + 4 ms - 10 - - - EXTLOFXTALRES_1KCK_64MS - Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 64 ms - 11 - - - EXTMEDFXTALRES_258CK_4MS - Ext. Crystal/Resonator Medium Freq.; Start-up time: 258 CK + 4 ms - 12 - - - EXTMEDFXTALRES_1KCK_64MS - Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 64 ms - 13 - - - EXTHIFXTALRES_258CK_4MS - Ext. Crystal/Resonator High Freq.; Start-up time: 258 CK + 4 ms - 14 - - - EXTHIFXTALRES_1KCK_64MS - Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 64 ms - 15 - - - EXTCLK_6CK_4MS - Ext. Clock; Start-up time: 6 CK + 4 ms - 16 - - - INTRCOSC_1MHZ_6CK_4MS - Int. RC Osc. 1 MHz; Start-up time: 6 CK + 4 ms - 17 - - - INTRCOSC_2MHZ_6CK_4MS - Int. RC Osc. 2 MHz; Start-up time: 6 CK + 4 ms - 18 - - - INTRCOSC_4MHZ_6CK_4MS - Int. RC Osc. 4 MHz; Start-up time: 6 CK + 4 ms - 19 - - - INTRCOSC_8MHZ_6CK_4MS - Int. RC Osc. 8 MHz; Start-up time: 6 CK + 4 ms - 20 - - - EXTRCOSC_XX_0MHZ9_18CK_4MS - Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 4 ms - 21 - - - EXTRCOSC_0MHZ9_3MHZ_18CK_4MS - Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 4 ms - 22 - - - EXTRCOSC_3MHZ_8MHZ_18CK_4MS - Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 4 ms - 23 - - - EXTRCOSC_8MHZ_12MHZ_18CK_4MS - Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 4 ms - 24 - - - EXTLOFXTAL_1KCK_64MS - Ext. Low-Freq. Crystal; Start-up time: 1K CK + 64 ms - 25 - - - EXTLOFXTALRES_258CK_64MS - Ext. Crystal/Resonator Low Freq.; Start-up time: 258 CK + 64 ms - 26 - - - EXTLOFXTALRES_16KCK_0MS - Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 0 ms - 27 - - - EXTMEDFXTALRES_258CK_64MS - Ext. Crystal/Resonator Medium Freq.; Start-up time: 258 CK + 64 ms - 28 - - - EXTMEDFXTALRES_16KCK_0MS - Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 0 ms - 29 - - - EXTHIFXTALRES_258CK_64MS - Ext. Crystal/Resonator High Freq.; Start-up time: 258 CK + 64 ms - 30 - - - EXTHIFXTALRES_16KCK_0MS - Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 0 ms - 31 - - - EXTCLK_6CK_64MS - Ext. Clock; Start-up time: 6 CK + 64 ms - 32 - - - INTRCOSC_1MHZ_6CK_64MS - Int. RC Osc. 1 MHz; Start-up time: 6 CK + 64 ms - 33 - - - INTRCOSC_2MHZ_6CK_64MS - Int. RC Osc. 2 MHz; Start-up time: 6 CK + 64 ms - 34 - - - INTRCOSC_4MHZ_6CK_64MS - Int. RC Osc. 4 MHz; Start-up time: 6 CK + 64 ms - 35 - - - INTRCOSC_8MHZ_6CK_64MS - Int. RC Osc. 8 MHz; Start-up time: 6 CK + 64 ms - 36 - - - EXTRCOSC_XX_0MHZ9_18CK_64MS - Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 64 ms - 37 - - - EXTRCOSC_0MHZ9_3MHZ_18CK_64MS - Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 64 ms - 38 - - - EXTRCOSC_3MHZ_8MHZ_18CK_64MS - Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 64 ms - 39 - - - EXTRCOSC_8MHZ_12MHZ_18CK_64MS - Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 64 ms - 40 - - - EXTLOFXTAL_32KCK_64MS - Ext. Low-Freq. Crystal; Start-up time: 32K CK + 64 ms - 41 - - - EXTLOFXTALRES_1KCK_0MS - Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 0 ms - 42 - - - EXTLOFXTALRES_16KCK_4MS - Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 4 ms - 43 - - - EXTMEDFXTALRES_1KCK_0MS - Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 0 ms - 44 - - - EXTMEDFXTALRES_16KCK_4MS - Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 4 ms - 45 - - - EXTHIFXTALRES_1KCK_0MS - Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 0 ms - 46 - - - EXTHIFXTALRES_16KCK_4MS - Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 4 ms - 47 - - - EXTRCOSC_XX_0MHZ9_6CK_4MS - Ext. RC Osc. - 0.9 MHz; Start-up time: 6 CK + 4 ms - 53 - - - EXTRCOSC_0MHZ9_3MHZ_6CK_4MS - Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 6 CK + 4 ms - 54 - - - EXTRCOSC_3MHZ_8MHZ_6CK_4MS - Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 6 CK + 4 ms - 55 - - - EXTRCOSC_8MHZ_12MHZ_6CK_4MS - Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 6 CK + 4 ms - 56 - - - EXTLOFXTALRES_1KCK_4MS - Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 4 ms - 58 - - - EXTLOFXTALRES_16KCK_64MS - Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 64 ms - 59 - - - EXTMEDFXTALRES_1KCK_4MS - Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 4 ms - 60 - - - EXTMEDFXTALRES_16KCK_64MS - Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 64 ms - 61 - - - EXTHIFXTALRES_1KCK_4MS - Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 4 ms - 62 - - - EXTHIFXTALRES_16KCK_64MS - Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 64 ms - 63 - - - - - BODEN - Brown-out detection enabled - [6:6] - - - BODLEVEL - Brownout detector trigger level - [7:7] - - true - - - - 4V0 - Brown-out detection at VCC=4.0 V - 0 - - - 2V7 - Brown-out detection at VCC=2.7 V - 1 - - - - - - - - - JTAG - JTAG Interface - 0x42 - - - MCUCSR - MCU Control And Status Register - 0x12 - - - JTRF - JTAG Reset Flag - [4:4] - - - JTD - JTAG Interface Disable - [7:7] - - - - - OCDR - On-Chip Debug Related Register in I/O Memory - 0x0 - - - OCDR - On-Chip Debug Register Bits - [7:0] - - - 0 - 255 - - - - - - - - - LOCKBIT - Lockbits - 0x0 - - - LOCKBIT - <TBD> - 0x0 - - - LB - Memory Lock - [1:0] - - true - - - - PROG_VER_DISABLED - Further programming and verification disabled - 0 - - - PROG_DISABLED - Further programming disabled - 2 - - - NO_LOCK - No memory lock features enabled - 3 - - - - - BLB0 - Boot Loader Protection Mode - [3:2] - - true - - - - LPM_SPM_DISABLE - LPM and SPM prohibited in Application Section - 0 - - - LPM_DISABLE - LPM prohibited in Application Section - 1 - - - SPM_DISABLE - SPM prohibited in Application Section - 2 - - - NO_LOCK - No lock on SPM and LPM in Application Section - 3 - - - - - BLB1 - Boot Loader Protection Mode - [5:4] - - true - - - - LPM_SPM_DISABLE - LPM and SPM prohibited in Boot Section - 0 - - - LPM_DISABLE - LPM prohibited in Boot Section - 1 - - - SPM_DISABLE - SPM prohibited in Boot Section - 2 - - - NO_LOCK - No lock on SPM and LPM in Boot Section - 3 - - - - - - - - - MISC - Other Registers - 0x40 - - - SFIOR - Special Function IO Register - 0x0 - - - PSR321 - Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1 - [0:0] - - - PSR0 - Prescaler Reset Timer/Counter0 - [1:1] - - - PUD - Pull Up Disable - [2:2] - - - ACME - Analog Comparator Multiplexer Enable - [3:3] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - - - PORTA - I/O Port - 0x39 - - - DDRA - Port A Data Direction Register - 0x1 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - PINA - Port A Input Pins - 0x0 - read-write - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - PORTA - Port A Data Register - 0x2 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - - - PORTB - I/O Port - 0x36 - - - DDRB - Port B Data Direction Register - 0x1 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PINB - Port B Input Pins - 0x0 - read-write - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PORTB - Port B Data Register - 0x2 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - - - PORTC - I/O Port - 0x33 - - - DDRC - Port C Data Direction Register - 0x1 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - PINC - Port C Input Pins - 0x0 - read-write - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - PORTC - Port C Data Register - 0x2 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - - - PORTD - I/O Port - 0x30 - - - DDRD - Port D Data Direction Register - 0x1 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PIND - Port D Input Pins - 0x0 - read-write - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PORTD - Port D Data Register - 0x2 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - - - PORTE - I/O Port - 0x21 - - - DDRE - Data Direction Register, Port E - 0x1 - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - PE4 - Pin E4 - [4:4] - - - PE5 - Pin E5 - [5:5] - - - PE6 - Pin E6 - [6:6] - - - PE7 - Pin E7 - [7:7] - - - - - PINE - Input Pins, Port E - 0x0 - read-write - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - PE4 - Pin E4 - [4:4] - - - PE5 - Pin E5 - [5:5] - - - PE6 - Pin E6 - [6:6] - - - PE7 - Pin E7 - [7:7] - - - - - PORTE - Data Register, Port E - 0x2 - - - PE0 - Pin E0 - [0:0] - - - PE1 - Pin E1 - [1:1] - - - PE2 - Pin E2 - [2:2] - - - PE3 - Pin E3 - [3:3] - - - PE4 - Pin E4 - [4:4] - - - PE5 - Pin E5 - [5:5] - - - PE6 - Pin E6 - [6:6] - - - PE7 - Pin E7 - [7:7] - - - - - - - PORTF - I/O Port - 0x20 - - - DDRF - Data Direction Register, Port F - 0x41 - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF2 - Pin F2 - [2:2] - - - PF3 - Pin F3 - [3:3] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - PF7 - Pin F7 - [7:7] - - - - - PINF - Input Pins, Port F - 0x0 - read-write - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF2 - Pin F2 - [2:2] - - - PF3 - Pin F3 - [3:3] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - PF7 - Pin F7 - [7:7] - - - - - PORTF - Data Register, Port F - 0x42 - - - PF0 - Pin F0 - [0:0] - - - PF1 - Pin F1 - [1:1] - - - PF2 - Pin F2 - [2:2] - - - PF3 - Pin F3 - [3:3] - - - PF4 - Pin F4 - [4:4] - - - PF5 - Pin F5 - [5:5] - - - PF6 - Pin F6 - [6:6] - - - PF7 - Pin F7 - [7:7] - - - - - - - PORTG - I/O Port - 0x63 - - - DDRG - Data Direction Register, Port G - 0x1 - - - PG0 - Pin G0 - [0:0] - - - PG1 - Pin G1 - [1:1] - - - PG2 - Pin G2 - [2:2] - - - PG3 - Pin G3 - [3:3] - - - PG4 - Pin G4 - [4:4] - - - - - PING - Input Pins, Port G - 0x0 - read-write - - - PG0 - Pin G0 - [0:0] - - - PG1 - Pin G1 - [1:1] - - - PG2 - Pin G2 - [2:2] - - - PG3 - Pin G3 - [3:3] - - - PG4 - Pin G4 - [4:4] - - - - - PORTG - Data Register, Port G - 0x2 - - - PG0 - Pin G0 - [0:0] - - - PG1 - Pin G1 - [1:1] - - - PG2 - Pin G2 - [2:2] - - - PG3 - Pin G3 - [3:3] - - - PG4 - Pin G4 - [4:4] - - - - - - - SPI - Serial Peripheral Interface - 0x2D - - - SPCR - SPI Control Register - 0x0 - - - SPR - SPI Clock Rate Selects - [1:0] - - true - - SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 - - - CPHA - Clock Phase - [2:2] - - - CPOL - Clock polarity - [3:3] - - - MSTR - Master/Slave Select - [4:4] - - - DORD - Data Order - [5:5] - - - SPE - SPI Enable - [6:6] - - - SPIE - SPI Interrupt Enable - [7:7] - - - - - SPDR - SPI Data Register - 0x2 - - - 0 - 255 - - - - - SPSR - SPI Status Register - 0x1 - read-write - - - SPI2X - Double SPI Speed Bit - [0:0] - read-write - - WCOL - Write Collision Flag - [6:6] - read-only - - SPIF - SPI Interrupt Flag - [7:7] - read-only - - - - - - TC0 - Timer/Counter, 8-bit Async - 0x40 - - - ASSR - Asynchronus Status Register - 0x10 - - - TCR0UB - Timer/Counter Control Register 0 Update Busy - [0:0] - - - OCR0UB - Output Compare register 0 Busy - [1:1] - - - TCN0UB - Timer/Counter0 Update Busy - [2:2] - - - AS0 - Asynchronus Timer/Counter 0 - [3:3] - - - - - OCR0 - Output Compare Register - 0x11 - - - 0 - 255 - - - - - SFIOR - Special Function IO Register - 0x0 - - - PSR0 - Prescaler Reset Timer/Counter0 - [1:1] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - TCCR0 - Timer/Counter Control Register - 0x13 - - - CS0 - Clock Selects - [2:0] - - true - - - - VAL_0x00 - No Clock Source (Stopped) - 0 - - - VAL_0x01 - Running, No Prescaling - 1 - - - VAL_0x02 - Running, CLK/8 - 2 - - - VAL_0x03 - Running, CLK/32 - 3 - - - VAL_0x04 - Running, CLK/64 - 4 - - - VAL_0x05 - Running, CLK/128 - 5 - - - VAL_0x06 - Running, CLK/256 - 6 - - - VAL_0x07 - Running, CLK/1024 - 7 - - - - - WGM01 - Waveform Generation Mode 1 - [3:3] - - - COM0 - Compare Match Output Modes - [5:4] - - - 0 - 3 - - - - - WGM00 - Waveform Generation Mode 0 - [6:6] - - true - - - - VAL_0x00 - Normal - 0 - - - VAL_0x01 - CTC - 1 - - - - - FOC0 - Force Output Compare - [7:7] - - - - - TCNT0 - Timer/Counter Register - 0x12 - - - 0 - 255 - - - - - TIFR - Timer/Counter Interrupt Flag register - 0x16 - read-only - - - TOV0 - Timer/Counter0 Overflow Flag - [0:0] - - - OCF0 - Output Compare Flag 0 - [1:1] - - - - - TIMSK - Timer/Counter Interrupt Mask Register - 0x17 - - - TOIE0 - Timer/Counter0 Overflow Interrupt Enable - [0:0] - - - OCIE0 - Timer/Counter0 Output Compare Match Interrupt register - [1:1] - - - - - - - TC1 - Timer/Counter, 16-bit - 0x40 - - - ETIFR - Extended Timer/Counter Interrupt Flag register - 0x3C - read-only - - - OCF1C - Timer/Counter 1, Output Compare C Match Flag - [0:0] - - - - - ETIMSK - Extended Timer/Counter Interrupt Mask Register - 0x3D - - - OCIE1C - Timer/Counter 1, Output Compare Match C Interrupt Enable - [0:0] - - - - - ICR1 - Timer/Counter1 Input Capture Register Bytes - 0x6 - 16 - - - 0 - 65535 - - - - - OCR1A - Timer/Counter1 Output Compare Register Bytes - 0xA - 16 - - - 0 - 65535 - - - - - OCR1B - Timer/Counter1 Output Compare Register Bytes - 0x8 - 16 - - - 0 - 65535 - - - - - OCR1C - Timer/Counter1 Output Compare Register Bytes - 0x38 - 16 - - - 0 - 65535 - - - - - SFIOR - Special Function IO Register - 0x0 - - - PSR321 - Prescaler Reset, T/C3, T/C2, T/C1 - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - TCCR1A - Timer/Counter1 Control Register A - 0xF - - - WGM1 - Waveform Generation Mode Bits - [1:0] - - - 0 - 3 - - - - - COM1C - Compare Output Mode 1C, bits - [3:2] - - - 0 - 3 - - - - - COM1B - Compare Output Mode 1B, bits - [5:4] - - - 0 - 3 - - - - - COM1A - Compare Output Mode 1A, bits - [7:6] - - - 0 - 3 - - - - - - - TCCR1B - Timer/Counter1 Control Register B - 0xE - - - CS1 - Clock Select1 bits - [2:0] - - true - - - - VAL_0x00 - No Clock Source (Stopped) - 0 - - - VAL_0x01 - Running, No Prescaling - 1 - - - VAL_0x02 - Running, CLK/8 - 2 - - - VAL_0x03 - Running, CLK/64 - 3 - - - VAL_0x04 - Running, CLK/256 - 4 - - - VAL_0x05 - Running, CLK/1024 - 5 - - - VAL_0x06 - Running, ExtClk Tx Falling Edge - 6 - - - VAL_0x07 - Running, ExtClk Tx Rising Edge - 7 - - - - - WGM1 - Waveform Generation Mode - [4:3] - - - 0 - 3 - - - - - ICES1 - Input Capture 1 Edge Select - [6:6] - - - ICNC1 - Input Capture 1 Noise Canceler - [7:7] - - - - - TCCR1C - Timer/Counter1 Control Register C - 0x3A - - - FOC1C - Force Output Compare for channel C - [5:5] - - - FOC1B - Force Output Compare for channel B - [6:6] - - - FOC1A - Force Output Compare for channel A - [7:7] - - - - - TCNT1 - Timer/Counter1 Bytes - 0xC - 16 - - - 0 - 65535 - - - - - TIFR - Timer/Counter Interrupt Flag register - 0x16 - read-only - - - TOV1 - Timer/Counter1 Overflow Flag - [2:2] - - - OCF1B - Output Compare Flag 1B - [3:3] - - - OCF1A - Output Compare Flag 1A - [4:4] - - - ICF1 - Input Capture Flag 1 - [5:5] - - - - - TIMSK - Timer/Counter Interrupt Mask Register - 0x17 - - - TOIE1 - Timer/Counter1 Overflow Interrupt Enable - [2:2] - - - OCIE1B - Timer/Counter1 Output CompareB Match Interrupt Enable - [3:3] - - - OCIE1A - Timer/Counter1 Output CompareA Match Interrupt Enable - [4:4] - - - TICIE1 - Timer/Counter1 Input Capture Interrupt Enable - [5:5] - - - - - - - TC2 - Timer/Counter, 8-bit - 0x43 - - - OCR2 - Output Compare Register - 0x0 - - - 0 - 255 - - - - - TCCR2 - Timer/Counter Control Register - 0x2 - - - CS2 - Clock Select - [2:0] - - true - - - - VAL_0x00 - No Clock Source (Stopped) - 0 - - - VAL_0x01 - Running, No Prescaling - 1 - - - VAL_0x02 - Running, CLK/8 - 2 - - - VAL_0x03 - Running, CLK/64 - 3 - - - VAL_0x04 - Running, CLK/256 - 4 - - - VAL_0x05 - Running, CLK/1024 - 5 - - - VAL_0x06 - Running, ExtClk Tx Falling Edge - 6 - - - VAL_0x07 - Running, ExtClk Tx Rising Edge - 7 - - - - - WGM21 - Waveform Generation Mode - [3:3] - - - COM2 - Compare Match Output Mode - [5:4] - - - 0 - 3 - - - - - WGM20 - Wafeform Generation Mode - [6:6] - - true - - - - VAL_0x00 - Normal - 0 - - - VAL_0x01 - CTC - 1 - - - - - FOC2 - Force Output Compare - [7:7] - - - - - TCNT2 - Timer/Counter Register - 0x1 - - - 0 - 255 - - - - - TIFR - Timer/Counter Interrupt Flag Register - 0x13 - read-only - - - TOV2 - Timer/Counter2 Overflow Flag - [6:6] - - - OCF2 - Output Compare Flag 2 - [7:7] - - - - - TIMSK - <TBD> - 0x14 - - - TOIE2 - <TBD> - [6:6] - - - OCIE2 - <TBD> - [7:7] - - - - - - - TC3 - Timer/Counter, 16-bit - 0x40 - - - ETIFR - Extended Timer/Counter Interrupt Flag register - 0x3C - read-only - - - OCF3C - Timer/Counter3 Output Compare C Match Flag - [1:1] - - - TOV3 - Timer/Counter3 Overflow Flag - [2:2] - - - OCF3B - Output Compare Flag 3B - [3:3] - - - OCF3A - Output Compare Flag 3A - [4:4] - - - ICF3 - Input Capture Flag 3 - [5:5] - - - - - ETIMSK - Extended Timer/Counter Interrupt Mask Register - 0x3D - - - OCIE3C - Timer/Counter3, Output Compare Match Interrupt Enable - [1:1] - - - TOIE3 - Timer/Counter3 Overflow Interrupt Enable - [2:2] - - - OCIE3B - Timer/Counter3 Output CompareB Match Interrupt Enable - [3:3] - - - OCIE3A - Timer/Counter3 Output CompareA Match Interrupt Enable - [4:4] - - - TICIE3 - Timer/Counter3 Input Capture Interrupt Enable - [5:5] - - - - - ICR3 - Timer/Counter3 Input Capture Register Bytes - 0x40 - 16 - - - 0 - 65535 - - - - - OCR3A - Timer/Counter3 Output Compare Register A Bytes - 0x46 - 16 - - - 0 - 65535 - - - - - OCR3B - Timer/Counter3 Output Compare Register B Bytes - 0x44 - 16 - - - 0 - 65535 - - - - - OCR3C - Timer/Counter3 Output compare Register C Bytes - 0x42 - 16 - - - 0 - 65535 - - - - - SFIOR - Special Function IO Register - 0x0 - - - PSR321 - Prescaler Reset, T/C3, T/C2, T/C1 - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - TCCR3A - Timer/Counter3 Control Register A - 0x4B - - - WGM3 - Waveform Generation Mode Bits - [1:0] - - - 0 - 3 - - - - - COM3C - Compare Output Mode 3C, bits - [3:2] - - - 0 - 3 - - - - - COM3B - Compare Output Mode 3B, bits - [5:4] - - - 0 - 3 - - - - - COM3A - Compare Output Mode 3A, bits - [7:6] - - - 0 - 3 - - - - - - - TCCR3B - Timer/Counter3 Control Register B - 0x4A - - - CS3 - Clock Select3 bits - [2:0] - - true - - - - VAL_0x00 - No Clock Source (Stopped) - 0 - - - VAL_0x01 - Running, No Prescaling - 1 - - - VAL_0x02 - Running, CLK/8 - 2 - - - VAL_0x03 - Running, CLK/64 - 3 - - - VAL_0x04 - Running, CLK/256 - 4 - - - VAL_0x05 - Running, CLK/1024 - 5 - - - VAL_0x06 - Running, ExtClk Tx Falling Edge - 6 - - - VAL_0x07 - Running, ExtClk Tx Rising Edge - 7 - - - - - WGM3 - Waveform Generation Mode - [4:3] - - - 0 - 3 - - - - - ICES3 - Input Capture 3 Edge Select - [6:6] - - - ICNC3 - Input Capture 3 Noise Canceler - [7:7] - - - - - TCCR3C - Timer/Counter3 Control Register C - 0x4C - - - FOC3C - Force Output Compare for channel C - [5:5] - - - FOC3B - Force Output Compare for channel B - [6:6] - - - FOC3A - Force Output Compare for channel A - [7:7] - - - - - TCNT3 - Timer/Counter3 Bytes - 0x48 - 16 - - - 0 - 65535 - - - - - - - TWI - Two Wire Serial Interface - 0x70 - - - TWAR - TWI (Slave) Address register - 0x2 - - - TWGCE - TWI General Call Recognition Enable Bit - [0:0] - - - TWA - TWI (Slave) Address register Bits - [7:1] - - - 0 - 127 - - - - - - - TWBR - TWI Bit Rate register - 0x0 - - - 0 - 255 - - - - - TWCR - TWI Control Register - 0x4 - read-only - - - TWIE - TWI Interrupt Enable - [0:0] - - - TWEN - TWI Enable Bit - [2:2] - - - TWWC - TWI Write Collition Flag - [3:3] - - - TWSTO - TWI Stop Condition Bit - [4:4] - - - TWSTA - TWI Start Condition Bit - [5:5] - - - TWEA - TWI Enable Acknowledge Bit - [6:6] - - - TWINT - TWI Interrupt Flag - [7:7] - - - - - TWDR - TWI Data register - 0x3 - - - 0 - 255 - - - - - TWSR - TWI Status Register - 0x1 - - - TWPS - TWI Prescaler - [1:0] - - true - - - - VAL_0x00 - 1 - 0 - - - VAL_0x01 - 4 - 1 - - - VAL_0x02 - 16 - 2 - - - VAL_0x03 - 64 - 3 - - - - - TWS - TWI Status - [7:3] - - - 0 - 31 - - - - - - - - - USART0 - USART - 0x29 - - - UBRR0H - USART Baud Rate Register Hight Byte - 0x67 - - - 0 - 255 - - - - - UBRR0L - USART Baud Rate Register Low Byte - 0x0 - - - 0 - 255 - - - - - UCSR0A - USART Control and Status Register A - 0x2 - read-write - - - MPCM0 - Multi-processor Communication Mode - [0:0] - - - U2X0 - Double the USART transmission speed - [1:1] - - - UPE0 - Parity Error - [2:2] - read-only - - DOR0 - Data overRun - [3:3] - read-only - - FE0 - Framing Error - [4:4] - read-only - - UDRE0 - USART Data Register Empty - [5:5] - read-only - - TXC0 - USART Transmit Complete - [6:6] - - - RXC0 - USART Receive Complete - [7:7] - read-only - - - - UCSR0B - USART Control and Status Register B - 0x1 - - - TXB80 - Transmit Data Bit 8 - [0:0] - - - RXB80 - Receive Data Bit 8 - [1:1] - read-only - - UCSZ02 - Character Size - [2:2] - - - TXEN0 - Transmitter Enable - [3:3] - - - RXEN0 - Receiver Enable - [4:4] - - - UDRIE0 - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE0 - TX Complete Interrupt Enable - [6:6] - - - RXCIE0 - RX Complete Interrupt Enable - [7:7] - - - - - UCSR0C - USART Control and Status Register C - 0x6C - - - UCPOL0 - Clock Polarity - [0:0] - UCPOL0read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 - - - UCSZ0 - Character Size - [2:1] - - - 0 - 3 - - - UCSZ0read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 - - - USBS0 - Stop Bit Select - [3:3] - - true - - USBS0read-writeSTOP11-bit0STOP22-bit1 - - - UPM0 - Parity Mode Bits - [5:4] - - true - - UPM0read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 - - - UMSEL0 - USART Mode Select - [7:6] - - true - - UMSEL0read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 - - - - - UDR0 - USART I/O Data Register - 0x3 - - - 0 - 255 - - - - - - - USART1 - USART - 0x98 - - - UBRR1H - USART Baud Rate Register Hight Byte - 0x0 - - - 0 - 255 - - - - - UBRR1L - USART Baud Rate Register Low Byte - 0x1 - - - 0 - 255 - - - - - UCSR1A - USART Control and Status Register A - 0x3 - read-write - - - MPCM1 - Multi-processor Communication Mode - [0:0] - - - U2X1 - Double the USART transmission speed - [1:1] - - - UPE1 - Parity Error - [2:2] - read-only - - DOR1 - Data overRun - [3:3] - read-only - - FE1 - Framing Error - [4:4] - read-only - - UDRE1 - USART Data Register Empty - [5:5] - read-only - - TXC1 - USART Transmit Complete - [6:6] - - - RXC1 - USART Receive Complete - [7:7] - read-only - - - - UCSR1B - USART Control and Status Register B - 0x2 - - - TXB81 - Transmit Data Bit 8 - [0:0] - - - RXB81 - Receive Data Bit 8 - [1:1] - read-only - - UCSZ12 - Character Size - [2:2] - - - TXEN1 - Transmitter Enable - [3:3] - - - RXEN1 - Receiver Enable - [4:4] - - - UDRIE1 - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE1 - TX Complete Interrupt Enable - [6:6] - - - RXCIE1 - RX Complete Interrupt Enable - [7:7] - - - - - UCSR1C - USART Control and Status Register C - 0x5 - - - UCPOL1 - Clock Polarity - [0:0] - UCPOL1read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 - - - UCSZ1 - Character Size - [2:1] - - - 0 - 3 - - - UCSZ1read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 - - - USBS1 - Stop Bit Select - [3:3] - - true - - USBS1read-writeSTOP11-bit0STOP22-bit1 - - - UPM1 - Parity Mode Bits - [5:4] - - true - - UPM1read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 - - - UMSEL1 - USART Mode Select - [7:6] - - true - - UMSEL1read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 - - - - - UDR1 - USART I/O Data Register - 0x4 - - - 0 - 255 - - - - - - - WDT - Watchdog Timer - 0x41 - - - WDTCR - Watchdog Timer Control Register - 0x0 - - - WDP - Watch Dog Timer Prescaler bits - [2:0] - - true - - - - VAL_0x00 - Oscillator Cycles 16K - 0 - - - VAL_0x01 - Oscillator Cycles 32K - 1 - - - VAL_0x02 - Oscillator Cycles 64K - 2 - - - VAL_0x03 - Oscillator Cycles 128K - 3 - - - VAL_0x04 - Oscillator Cycles 256K - 4 - - - VAL_0x05 - Oscillator Cycles 512K - 5 - - - VAL_0x06 - Oscillator Cycles 1024K - 6 - - - VAL_0x07 - Oscillator Cycles 2048K - 7 - - - - - WDE - Watch Dog Enable - [3:3] - - - WDCE - Watchdog Change Enable - [4:4] - - - - - - - \ No newline at end of file diff --git a/misc/svd/atmega644.svd b/misc/svd/atmega644.svd deleted file mode 100644 index 59a7402..0000000 --- a/misc/svd/atmega644.svd +++ /dev/null @@ -1,3479 +0,0 @@ - - Atmel - ATmega644 - 8 - 8 - read-write - 0 - 0xff - - - AC - Analog Comparator - 0x50 - - - ACSR - Analog Comparator Control And Status Register - 0x0 - read-write - - - ACIS - Analog Comparator Interrupt Mode Select - [1:0] - - true - - ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 - - - ACIC - Analog Comparator Input Capture Enable - [2:2] - - - ACIE - Analog Comparator Interrupt Enable - [3:3] - - - ACI - Analog Comparator Interrupt Flag - [4:4] - - - ACO - Analog Compare Output - [5:5] - read-only - - ACBG - Analog Comparator Bandgap Select - [6:6] - - - ACD - Analog Comparator Disable - [7:7] - - - - - ADCSRB - ADC Control and Status Register B - 0x2B - - - ACME - Analog Comparator Multiplexer Enable - [6:6] - - - - - DIDR1 - Digital Input Disable Register 1 - 0x2F - - - AIN0D - AIN0 Digital Input Disable - [0:0] - - - AIN1D - AIN1 Digital Input Disable - [1:1] - - - - - - - ADC - Analog-to-Digital Converter - 0x78 - - - ADC - ADC Data Register Bytes - 0x0 - 16 - - - 0 - 65535 - - - - - ADCSRA - The ADC Control and Status register A - 0x2 - read-write - - - ADPS - ADC Prescaler Select Bits - [2:0] - - true - - ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 - - - ADIE - ADC Interrupt Enable - [3:3] - - - ADIF - ADC Interrupt Flag - [4:4] - - - ADATE - ADC Auto Trigger Enable - [5:5] - - - ADSC - ADC Start Conversion - [6:6] - - - ADEN - ADC Enable - [7:7] - - - - - ADCSRB - The ADC Control and Status register B - 0x3 - - - ADTS - ADC Auto Trigger Source bits - [2:0] - - true - - - - VAL_0x00 - Free Running mode - 0 - - - VAL_0x01 - Analog Comparator - 1 - - - VAL_0x02 - External Interrupt Request 0 - 2 - - - VAL_0x03 - Timer/Counter0 Compare Match A - 3 - - - VAL_0x04 - Timer/Counter0 Overflow - 4 - - - VAL_0x05 - Timer/Counter1 Compare Match B - 5 - - - VAL_0x06 - Timer/Counter1 Overflow - 6 - - - VAL_0x07 - Timer/Counter1 Capture Event - 7 - - - - - ACME - <TBD> - [6:6] - - - - - ADMUX - The ADC multiplexer Selection Register - 0x4 - - - MUX - Analog Channel and Gain Selection Bits - [4:0] - - true - - - - ADC0 - ADC Single Ended Input pin 0 - 0 - - - ADC1 - ADC Single Ended Input pin 1 - 1 - - - ADC2 - ADC Single Ended Input pin 2 - 2 - - - ADC3 - ADC Single Ended Input pin 3 - 3 - - - ADC4 - ADC Single Ended Input pin 4 - 4 - - - ADC5 - ADC Single Ended Input pin 5 - 5 - - - ADC6 - ADC Single Ended Input pin 6 - 6 - - - ADC7 - ADC Single Ended Input pin 7 - 7 - - - ADC0_ADC0_10X - ADC Differential Inputs Postive pin 0 Negative pin 0 10x Gain - 8 - - - ADC1_ADC0_10X - ADC Differential Inputs Postive pin 1 Negative pin 0 10x Gain - 9 - - - ADC0_ADC0_200x - ADC Differential Inputs Postive pin 0 Negative pin 0 200x Gain - 10 - - - ADC1_ADC0_200X - ADC Differential Inputs Postive pin 1 Negative pin 0 200x Gain - 11 - - - ADC2_ADC2_10X - ADC Differential Inputs Postive pin 2 Negative pin 2 10x Gain - 12 - - - ADC3_ADC2_10X - ADC Differential Inputs Postive pin 3 Negative pin 2 10x Gain - 13 - - - ADC2_ADC2_200X - ADC Differential Inputs Postive pin 2 Negative pin 2 200x Gain - 14 - - - ADC3_ADC2_200X - ADC Differential Inputs Postive pin 3 Negative pin 2 200x Gain - 15 - - - ADC0_ADC1_1X - ADC Differential Inputs Postive pin 0 Negative pin 1 1x Gain - 16 - - - ADC1_ADC1_1X - ADC Differential Inputs Postive pin 1 Negative pin 1 1x Gain - 17 - - - ADC2_ADC1_1X - ADC Differential Inputs Postive pin 2 Negative pin 1 1x Gain - 18 - - - ADC3_ADC1_1X - ADC Differential Inputs Postive pin 3 Negative pin 1 1x Gain - 19 - - - ADC4_ADC1_1X - ADC Differential Inputs Postive pin 4 Negative pin 1 1x Gain - 20 - - - ADC5_ADC1_1X - ADC Differential Inputs Postive pin 5 Negative pin 1 1x Gain - 21 - - - ADC6_ADC1_1X - ADC Differential Inputs Postive pin 6 Negative pin 1 1x Gain - 22 - - - ADC7_ADC1_1X - ADC Differential Inputs Postive pin 7 Negative pin 1 1x Gain - 23 - - - ADC0_ADC2_1X - ADC Differential Inputs Postive pin 0 Negative pin 2 1x Gain - 24 - - - ADC1_ADC2_1X - ADC Differential Inputs Postive pin 1 Negative pin 2 1x Gain - 25 - - - ADC2_ADC2_1X - ADC Differential Inputs Postive pin 2 Negative pin 2 1x Gain - 26 - - - ADC3_ADC2_1X - ADC Differential Inputs Postive pin 3 Negative pin 2 1x Gain - 27 - - - ADC4_ADC2_1X - ADC Differential Inputs Postive pin 4 Negative pin 2 1x Gain - 28 - - - ADC5_ADC2_1X - ADC Differential Inputs Postive pin 5 Negative pin 2 1x Gain - 29 - - - ADC_VBG - Internal Reference (VBG) - 30 - - - ADC_GND - 0V (GND) - 31 - - - - - ADLAR - Left Adjust Result - [5:5] - - - REFS - Reference Selection Bits - [7:6] - - true - - REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 - - - - - DIDR0 - Digital Input Disable Register - 0x6 - - - ADC0D - <TBD> - [0:0] - - - ADC1D - <TBD> - [1:1] - - - ADC2D - <TBD> - [2:2] - - - ADC3D - <TBD> - [3:3] - - - ADC4D - <TBD> - [4:4] - - - ADC5D - <TBD> - [5:5] - - - ADC6D - <TBD> - [6:6] - - - ADC7D - <TBD> - [7:7] - - - - - - - BOOT_LOAD - Bootloader - 0x57 - - - SPMCSR - Store Program Memory Control Register - 0x0 - - - SPMEN - Store Program Memory Enable - [0:0] - - - PGERS - Page Erase - [1:1] - - - PGWRT - Page Write - [2:2] - - - BLBSET - Boot Lock Bit Set - [3:3] - - - RWWSRE - Read While Write section read enable - [4:4] - - - SIGRD - Signature Row Read - [5:5] - - - RWWSB - Read While Write Section Busy - [6:6] - - - SPMIE - SPM Interrupt Enable - [7:7] - - - - - - - CPU - CPU Registers - 0x3E - - RESET - External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. - 0 - - - INT0 - External Interrupt Request 0 - 1 - - - INT1 - External Interrupt Request 1 - 2 - - - INT2 - External Interrupt Request 2 - 3 - - - PCINT0 - Pin Change Interrupt Request 0 - 4 - - - PCINT1 - Pin Change Interrupt Request 1 - 5 - - - PCINT2 - Pin Change Interrupt Request 2 - 6 - - - PCINT3 - Pin Change Interrupt Request 3 - 7 - - - WDT - Watchdog Time-out Interrupt - 8 - - - TIMER2_COMPA - Timer/Counter2 Compare Match A - 9 - - - TIMER2_COMPB - Timer/Counter2 Compare Match B - 10 - - - TIMER2_OVF - Timer/Counter2 Overflow - 11 - - - TIMER1_CAPT - Timer/Counter1 Capture Event - 12 - - - TIMER1_COMPA - Timer/Counter1 Compare Match A - 13 - - - TIMER1_COMPB - Timer/Counter1 Compare Match B - 14 - - - TIMER1_OVF - Timer/Counter1 Overflow - 15 - - - TIMER0_COMPA - Timer/Counter0 Compare Match A - 16 - - - TIMER0_COMPB - Timer/Counter0 Compare Match B - 17 - - - TIMER0_OVF - Timer/Counter0 Overflow - 18 - - - SPI_STC - SPI Serial Transfer Complete - 19 - - - USART0_RX - USART0, Rx Complete - 20 - - - USART0_UDRE - USART0 Data register Empty - 21 - - - USART0_TX - USART0, Tx Complete - 22 - - - ANALOG_COMP - Analog Comparator - 23 - - - ADC - ADC Conversion Complete - 24 - - - EE_READY - EEPROM Ready - 25 - - - TWI - 2-wire Serial Interface - 26 - - - SPM_READY - Store Program Memory Read - 27 - - - - CLKPR - <TBD> - 0x23 - - - CLKPS - <TBD> - [3:0] - - true - - - - VAL_0x00 - 1 - 0 - - - VAL_0x01 - 2 - 1 - - - VAL_0x02 - 4 - 2 - - - VAL_0x03 - 8 - 3 - - - VAL_0x04 - 16 - 4 - - - VAL_0x05 - 32 - 5 - - - VAL_0x06 - 64 - 6 - - - VAL_0x07 - 128 - 7 - - - VAL_0x08 - 256 - 8 - - - - - CLKPCE - <TBD> - [7:7] - - - - - GPIOR0 - General Purpose IO Register 0 - 0x0 - - - GPIOR00 - General Purpose IO Register 0 bit 0 - [0:0] - - - GPIOR01 - General Purpose IO Register 0 bit 1 - [1:1] - - - GPIOR02 - General Purpose IO Register 0 bit 2 - [2:2] - - - GPIOR03 - General Purpose IO Register 0 bit 3 - [3:3] - - - GPIOR04 - General Purpose IO Register 0 bit 4 - [4:4] - - - GPIOR05 - General Purpose IO Register 0 bit 5 - [5:5] - - - GPIOR06 - General Purpose IO Register 0 bit 6 - [6:6] - - - GPIOR07 - General Purpose IO Register 0 bit 7 - [7:7] - - - - - GPIOR1 - General Purpose IO Register 1 - 0xC - - - GPIOR - General Purpose IO Register 1 bis - [7:0] - - - 0 - 255 - - - - - - - GPIOR2 - General Purpose IO Register 2 - 0xD - - - GPIOR - General Purpose IO Register 2 bis - [7:0] - - - 0 - 255 - - - - - - - MCUCR - MCU Control Register - 0x17 - - - IVCE - Interrupt Vector Change Enable - [0:0] - - - IVSEL - Interrupt Vector Select - [1:1] - - - PUD - Pull-up disable - [4:4] - - - JTD - JTAG Interface Disable - [7:7] - - - - - MCUSR - MCU Status Register - 0x16 - - - PORF - Power-on reset flag - [0:0] - - - EXTRF - External Reset Flag - [1:1] - - - BORF - Brown-out Reset Flag - [2:2] - - - WDRF - Watchdog Reset Flag - [3:3] - - - JTRF - JTAG Reset Flag - [4:4] - - - - - OSCCAL - Oscillator Calibration Value - 0x28 - - - OSCCAL - Oscillator Calibration - [7:0] - - - 0 - 255 - - - - - - - PRR - Power Reduction Register - 0x26 - - - PRADC - Power Reduction ADC - [0:0] - - - PRUSART0 - Power Reduction USART - [1:1] - - - PRSPI - Power Reduction Serial Peripheral Interface - [2:2] - - - PRTIM1 - Power Reduction Timer/Counter1 - [3:3] - - - PRTIM0 - Power Reduction Timer/Counter0 - [5:5] - - - PRTIM2 - Power Reduction Timer/Counter2 - [6:6] - - - PRTWI - Power Reduction TWI - [7:7] - - - - - SMCR - Sleep Mode Control Register - 0x15 - - - SE - Sleep Enable - [0:0] - - - SM - Sleep Mode Select bits - [3:1] - - true - - - - IDLE - Idle - 0 - - - ADC - ADC Noise Reduction (If Available) - 1 - - - PDOWN - Power Down - 2 - - - PSAVE - Power Save - 3 - - - VAL_0x04 - Reserved - 4 - - - VAL_0x05 - Reserved - 5 - - - STDBY - Standby - 6 - - - ESTDBY - Extended Standby - 7 - - - - - - - - - EEPROM - EEPROM - 0x3F - - - EEAR - EEPROM Address Register Low Bytes - 0x2 - 16 - - - 0 - 65535 - - - - - EECR - EEPROM Control Register - 0x0 - - - EERE - EEPROM Read Enable - [0:0] - - - EEPE - EEPROM Write Enable - [1:1] - - - EEMPE - EEPROM Master Write Enable - [2:2] - - - EERIE - EEPROM Ready Interrupt Enable - [3:3] - - - EEPM - EEPROM Programming Mode Bits - [5:4] - - true - - - - VAL_0x00 - Erase and Write in one operation - 0 - - - VAL_0x01 - Erase Only - 1 - - - VAL_0x02 - Write Only - 2 - - - - - - - EEDR - EEPROM Data Register - 0x1 - - - 0 - 255 - - - - - - - EXINT - External Interrupts - 0x3B - - - EICRA - External Interrupt Control Register A - 0x2E - - - ISC0 - External Interrupt Sense Control Bit - [1:0] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC1 - External Interrupt Sense Control Bit - [3:2] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC2 - External Interrupt Sense Control Bit - [5:4] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - - - EIFR - External Interrupt Flag Register - 0x1 - read-only - - - INTF - External Interrupt Flags - [2:0] - - - 0 - 7 - - - - - - - EIMSK - External Interrupt Mask Register - 0x2 - - - INT - External Interrupt Request 2 Enable - [2:0] - - - 0 - 7 - - - - - - - PCICR - Pin Change Interrupt Control Register - 0x2D - - - PCIE - Pin Change Interrupt Enables - [3:0] - - - 0 - 15 - - - - - - - PCIFR - Pin Change Interrupt Flag Register - 0x0 - read-only - - - PCIF - Pin Change Interrupt Flags - [3:0] - - - 0 - 15 - - - - - - - PCMSK0 - Pin Change Mask Register 0 - 0x30 - - - PCINT - Pin Change Enable Masks - [7:0] - - - 0 - 255 - - - - - - - PCMSK1 - Pin Change Mask Register 1 - 0x31 - - - PCINT - Pin Change Enable Masks - [7:0] - - - 0 - 255 - - - - - - - PCMSK2 - Pin Change Mask Register 2 - 0x32 - - - PCINT - Pin Change Enable Masks - [7:0] - - - 0 - 255 - - - - - - - PCMSK3 - Pin Change Mask Register 3 - 0x38 - - - PCINT - Pin Change Enable Masks - [7:0] - - - 0 - 255 - - - - - - - - - FUSE - Fuses - 0x0 - - - EXTENDED - <TBD> - 0x2 - - - BODLEVEL - Brown-out Detector trigger level - [2:0] - - true - - - - 4V3 - Brown-out detection at VCC=4.3 V - 4 - - - 2V7 - Brown-out detection at VCC=2.7 V - 5 - - - 1V8 - Brown-out detection at VCC=1.8 V - 6 - - - DISABLED - Brown-out detection disabled; [BODLEVEL=111] - 7 - - - - - - - HIGH - <TBD> - 0x1 - - - BOOTRST - Boot Reset vector Enabled - [0:0] - - - BOOTSZ - Select Boot Size - [2:1] - - true - - - - 4096W_7000 - Boot Flash size=4096 words Boot address=$7000 - 0 - - - 2048W_7800 - Boot Flash size=2048 words Boot address=$7800 - 1 - - - 1024W_7C00 - Boot Flash size=1024 words Boot address=$7C00 - 2 - - - 512W_7E00 - Boot Flash size=512 words Boot start address=$7E00 - 3 - - - - - EESAVE - Preserve EEPROM through the Chip Erase cycle - [3:3] - - - WDTON - Watchdog timer always on - [4:4] - - - SPIEN - Serial program downloading (SPI) enabled - [5:5] - - - JTAGEN - JTAG Interface Enabled - [6:6] - - - OCDEN - On-Chip Debug Enabled - [7:7] - - - - - LOW - <TBD> - 0x0 - - - SUT_CKSEL - Select Clock Source - [5:0] - - true - - - - EXTCLK_6CK_0MS - Ext. Clock; Start-up time: 6 CK + 0 ms - 0 - - - INTRCOSC_6CK_0MS - Int. RC Osc.; Start-up time: 6 CK + 0 ms - 2 - - - INTRCOSC_128KHZ_6CK_0MS - Int. 128kHz RC Osc.; Start-up time: 6 CK + 0 ms - 3 - - - EXTLOFXTAL_1KCK_0MS - Ext. Low-Freq. Crystal; Start-up time: 1K CK + 0 ms - 4 - - - EXTLOFXTAL_32KCK_0MS - Ext. Low-Freq. Crystal; Start-up time: 32K CK + 0 ms - 5 - - - FSOSC_258CK_4MS1_CRES_FASTPWR - Full Swing Oscillator; Start-up time: 258 CK + 4.1 ms; Ceramic res.; fast rising power - 6 - - - FSOSC_1KCK_65MS_CRES_SLOWPWR - Full Swing Oscillator; Start-up time: 1K CK + 65 ms; Ceramic res.; slowly rising power - 7 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 258 CK + 4.1 ms - 8 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 65 ms - 9 - - - EXTXOSC_0MHZ9_3MHZ_258CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 258 CK + 4.1 ms - 10 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 65 ms - 11 - - - EXTXOSC_3MHZ_8MHZ_258CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 258 CK + 4.1 ms - 12 - - - EXTXOSC_3MHZ_8MHZ_1KCK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 65 ms - 13 - - - EXTXOSC_8MHZ_XX_258CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time: 258 CK + 4.1 ms - 14 - - - EXTXOSC_8MHZ_XX_1KCK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 65 ms - 15 - - - EXTCLK_6CK_4MS1 - Ext. Clock; Start-up time: 6 CK + 4.1 ms - 16 - - - INTRCOSC_6CK_4MS1 - Int. RC Osc.; Start-up time: 6 CK + 4.1 ms - 18 - - - INTRCOSC_128KHZ_6CK_4MS - Int. 128kHz RC Osc.; Start-up time: 6 CK + 4 ms - 19 - - - EXTLOFXTAL_1KCK_4MS1 - Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4.1 ms - 20 - - - EXTLOFXTAL_32KCK_4MS1 - Ext. Low-Freq. Crystal; Start-up time: 32K CK + 4.1 ms - 21 - - - FSOSC_258CK_65MS_CRES_SLOWPWR - Full Swing Oscillator; Start-up time: 258 CK + 65 ms; Ceramic res.; slowly rising power - 22 - - - FSOSC_16KCK_0MS_XOSC_BODEN - Full Swing Oscillator; Start-up time: 16K CK + 0 ms; Crystal Osc.; BOD enabled - 23 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 258 CK + 65 ms - 24 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 0 ms - 25 - - - EXTXOSC_0MHZ9_3MHZ_258CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 258 CK + 65 ms - 26 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 0 ms - 27 - - - EXTXOSC_3MHZ_8MHZ_258CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 258 CK + 65 ms - 28 - - - EXTXOSC_3MHZ_8MHZ_16KCK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 0 ms - 29 - - - EXTXOSC_8MHZ_XX_258CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 258 CK + 65 ms - 30 - - - EXTXOSC_8MHZ_XX_16KCK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 0 ms - 31 - - - EXTCLK_6CK_65MS - Ext. Clock; Start-up time: 6 CK + 65 ms - 32 - - - INTRCOSC_6CK_65MS - Int. RC Osc.; Start-up time: 6 CK + 65 ms - 34 - - - INTRCOSC_128KHZ_6CK_64MS - Int. 128kHz RC Osc.; Start-up time: 6 CK + 64 ms - 35 - - - EXTLOFXTAL_1KCK_65MS - Ext. Low-Freq. Crystal; Start-up time: 1K CK + 65 ms - 36 - - - EXTLOFXTAL_32KCK_65MS - Ext. Low-Freq. Crystal; Start-up time: 32K CK + 65 ms - 37 - - - FSOSC_1KCK_0MS_CRES_BODEN - Full Swing Oscillator; Start-up time: 1K CK + 0 ms; Ceramic res.; BOD enable - 38 - - - FSOSC_16KCK_4MS1_XOSC_FASTPWR - Full Swing Oscillator; Start-up time: 16K CK + 4.1 ms; Crystal Osc.; fast rising power - 39 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 0 ms - 40 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 4.1 ms - 41 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 0 ms - 42 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 4.1 ms - 43 - - - EXTXOSC_3MHZ_8MHZ_1KCK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 0 ms - 44 - - - EXTXOSC_3MHZ_8MHZ_16KCK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 4.1 ms - 45 - - - EXTXOSC_8MHZ_XX_1KCK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 0 ms - 46 - - - EXTXOSC_8MHZ_XX_16KCK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 4.1 ms - 47 - - - FSOSC_1KCK_4MS1_CRES_FASTPWR - Full Swing Oscillator; Start-up time: 1K CK + 4.1 ms; Ceramic res.; fast rising power - 54 - - - FSOSC_16KCK_65MS_XOSC_SLOWPWR - Full Swing Oscillator; Start-up time: 16K CK + 65 ms; Crystal Osc.; slowly rising power - 55 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 1K CK + 4.1 ms - 56 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time: 16K CK + 65 ms - 57 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 1K CK + 4.1 ms - 58 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time: 16K CK + 65 ms - 59 - - - EXTXOSC_3MHZ_8MHZ_1KCK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 1K CK + 4.1 ms - 60 - - - EXTXOSC_3MHZ_8MHZ_16KCK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time: 16K CK + 65 ms - 61 - - - EXTXOSC_8MHZ_XX_1KCK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time: 1K CK + 4.1 ms - 62 - - - EXTXOSC_8MHZ_XX_16KCK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time: 16K CK + 65 ms - 63 - - - - - CKOUT - Clock output on PORTB1 - [6:6] - - - CKDIV8 - Divide clock by 8 internally - [7:7] - - - - - - - JTAG - JTAG Interface - 0x51 - - - MCUCR - MCU Control Register - 0x4 - - - JTD - JTAG Interface Disable - [7:7] - - - - - MCUSR - MCU Status Register - 0x3 - read-only - - - JTRF - JTAG Reset Flag - [4:4] - - - - - OCDR - On-Chip Debug Related Register in I/O Memory - 0x0 - - - 0 - 255 - - - - - - - LOCKBIT - Lockbits - 0x0 - - - LOCKBIT - <TBD> - 0x0 - - - LB - Memory Lock - [1:0] - - true - - - - PROG_VER_DISABLED - Further programming and verification disabled - 0 - - - PROG_DISABLED - Further programming disabled - 2 - - - NO_LOCK - No memory lock features enabled - 3 - - - - - BLB0 - Boot Loader Protection Mode - [3:2] - - true - - - - LPM_SPM_DISABLE - LPM and SPM prohibited in Application Section - 0 - - - LPM_DISABLE - LPM prohibited in Application Section - 1 - - - SPM_DISABLE - SPM prohibited in Application Section - 2 - - - NO_LOCK - No lock on SPM and LPM in Application Section - 3 - - - - - BLB1 - Boot Loader Protection Mode - [5:4] - - true - - - - LPM_SPM_DISABLE - LPM and SPM prohibited in Boot Section - 0 - - - LPM_DISABLE - LPM prohibited in Boot Section - 1 - - - SPM_DISABLE - SPM prohibited in Boot Section - 2 - - - NO_LOCK - No lock on SPM and LPM in Boot Section - 3 - - - - - - - - - PORTA - I/O Port - 0x20 - - - DDRA - Port A Data Direction Register - 0x1 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - PINA - Port A Input Pins - 0x0 - read-write - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - PORTA - Port A Data Register - 0x2 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - - - PORTB - I/O Port - 0x23 - - - DDRB - Port B Data Direction Register - 0x1 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PINB - Port B Input Pins - 0x0 - read-write - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PORTB - Port B Data Register - 0x2 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - - - PORTC - I/O Port - 0x26 - - - DDRC - Port C Data Direction Register - 0x1 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - PINC - Port C Input Pins - 0x0 - read-write - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - PORTC - Port C Data Register - 0x2 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - - - PORTD - I/O Port - 0x29 - - - DDRD - Port D Data Direction Register - 0x1 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PIND - Port D Input Pins - 0x0 - read-write - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PORTD - Port D Data Register - 0x2 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - - - SPI - Serial Peripheral Interface - 0x4C - - - SPCR - SPI Control Register - 0x0 - - - SPR - SPI Clock Rate Selects - [1:0] - - true - - SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 - - - CPHA - Clock Phase - [2:2] - - - CPOL - Clock polarity - [3:3] - - - MSTR - Master/Slave Select - [4:4] - - - DORD - Data Order - [5:5] - - - SPE - SPI Enable - [6:6] - - - SPIE - SPI Interrupt Enable - [7:7] - - - - - SPDR - SPI Data Register - 0x2 - - - 0 - 255 - - - - - SPSR - SPI Status Register - 0x1 - read-write - - - SPI2X - Double SPI Speed Bit - [0:0] - read-write - - WCOL - Write Collision Flag - [6:6] - read-only - - SPIF - SPI Interrupt Flag - [7:7] - read-only - - - - - - TC0 - Timer/Counter, 8-bit - 0x35 - - - GTCCR - General Timer/Counter Control Register - 0xE - - - PSRSYNC - Prescaler Reset Timer/Counter1 and Timer/Counter0 - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - OCR0A - Timer/Counter0 Output Compare Register - 0x12 - - - 0 - 255 - - - - - OCR0B - Timer/Counter0 Output Compare Register - 0x13 - - - 0 - 255 - - - - - TCCR0A - Timer/Counter Control Register A - 0xF - - - WGM0 - Waveform Generation Mode - [1:0] - - true - WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 - - - COM0B - Compare Output B Mode - [5:4] - - true - COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 - - - COM0A - Compare Output A Mode - [7:6] - - true - - - - - - TCCR0B - Timer/Counter Control Register B - 0x10 - - - CS0 - Clock Select - [2:0] - - true - - CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM02 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) - [3:3] - - - FOC0B - Force Output Compare B - [6:6] - write-only - - FOC0A - Force Output Compare A - [7:7] - write-only - - - - TCNT0 - Timer/Counter0 - 0x11 - - - 0 - 255 - - - - - TIFR0 - Timer/Counter0 Interrupt Flag register - 0x0 - read-write - - - TOV0 - Timer/Counter0 Overflow Flag - [0:0] - - - OCF0A - Timer/Counter0 Output Compare Flag 0A - [1:1] - - - OCF0B - Timer/Counter0 Output Compare Flag 0B - [2:2] - - - - - TIMSK0 - Timer/Counter0 Interrupt Mask Register - 0x39 - - - TOIE0 - Timer/Counter0 Overflow Interrupt Enable - [0:0] - - - OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable - [2:2] - - - - - - - TC1 - Timer/Counter, 16-bit - 0x36 - - - ICR1 - Timer/Counter1 Input Capture Register Bytes - 0x50 - 16 - - - 0 - 65535 - - - - - OCR1A - Timer/Counter1 Output Compare Register A Bytes - 0x52 - 16 - - - 0 - 65535 - - - - - OCR1B - Timer/Counter1 Output Compare Register B Bytes - 0x54 - 16 - - - 0 - 65535 - - - - - TCCR1A - Timer/Counter1 Control Register A - 0x4A - - - WGM1 - Pulse Width Modulator Select Bits - [1:0] - - - 0 - 3 - - - - - COM1B - Compare Output Mode 1B, bits - [5:4] - - true - COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM1A - Compare Output Mode 1A, bits - [7:6] - - true - - - - - - TCCR1B - Timer/Counter1 Control Register B - 0x4B - - - CS1 - Clock Select1 bits - [2:0] - - true - CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM1 - Waveform Generation Mode Bits - [4:3] - - - 0 - 3 - - - - - ICES1 - Input Capture 1 Edge Select - [6:6] - - - ICNC1 - Input Capture 1 Noise Canceler - [7:7] - - - - - TCCR1C - Timer/Counter1 Control Register C - 0x4C - - - FOC1B - Force Output Compare for Channel B - [6:6] - write-only - - FOC1A - Force Output Compare for Channel A - [7:7] - write-only - - - - TCNT1 - Timer/Counter1 Bytes - 0x4E - 16 - - - 0 - 65535 - - - - - TIFR1 - Timer/Counter Interrupt Flag register - 0x0 - read-write - - - TOV1 - Timer/Counter1 Overflow Flag - [0:0] - - - OCF1A - Timer/Counter1 Output Compare A Match Flag - [1:1] - - - OCF1B - Timer/Counter1 Output Compare B Match Flag - [2:2] - - - ICF1 - Timer/Counter1 Input Capture Flag - [5:5] - - - - - TIMSK1 - Timer/Counter1 Interrupt Mask Register - 0x39 - - - TOIE1 - Timer/Counter1 Overflow Interrupt Enable - [0:0] - - - OCIE1A - Timer/Counter1 Output Compare A Match Interrupt Enable - [1:1] - - - OCIE1B - Timer/Counter1 Output Compare B Match Interrupt Enable - [2:2] - - - ICIE1 - Timer/Counter1 Input Capture Interrupt Enable - [5:5] - - - - - - - TC2 - Timer/Counter, 8-bit Async - 0x37 - - - ASSR - Asynchronous Status Register - 0x7F - - - TCR2BUB - Timer/Counter Control Register2 Update Busy - [0:0] - - - TCR2AUB - Timer/Counter Control Register2 Update Busy - [1:1] - - - OCR2BUB - Output Compare Register 2 Update Busy - [2:2] - - - OCR2AUB - Output Compare Register2 Update Busy - [3:3] - - - TCN2UB - Timer/Counter2 Update Busy - [4:4] - - - AS2 - Asynchronous Timer/Counter2 - [5:5] - - - EXCLK - Enable External Clock Input - [6:6] - - - - - GTCCR - General Timer Counter Control register - 0xC - - - PSRASY - Prescaler Reset Timer/Counter2 - [1:1] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - OCR2A - Timer/Counter2 Output Compare Register A - 0x7C - - - 0 - 255 - - - - - OCR2B - Timer/Counter2 Output Compare Register B - 0x7D - - - 0 - 255 - - - - - TCCR2A - Timer/Counter2 Control Register A - 0x79 - - - WGM2 - Waveform Genration Mode - [1:0] - - true - WGM2read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *TOP*, Flag: *MAX*3 - - - COM2B - Compare Output B Mode - [5:4] - - true - COM2Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 - - - COM2A - Compare Output A Mode - [7:6] - - true - - - - - - TCCR2B - Timer/Counter2 Control Register B - 0x7A - - - CS2 - Clock Select bits - [2:0] - - true - - CS2read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_32Running, CLK/323PRESCALE_64Running, CLK/644PRESCALE_128Running, CLK/1285PRESCALE_256Running, CLK/2566PRESCALE_1024Running, CLK/10247 - - - WGM22 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) - [3:3] - - - FOC2B - Force Output Compare B - [6:6] - write-only - - FOC2A - Force Output Compare A - [7:7] - write-only - - - - TCNT2 - Timer/Counter2 - 0x7B - - - 0 - 255 - - - - - TIFR2 - Timer/Counter Interrupt Flag Register - 0x0 - read-write - - - TOV2 - Timer/Counter2 Overflow Flag - [0:0] - - - OCF2A - Output Compare Flag 2A - [1:1] - - - OCF2B - Output Compare Flag 2B - [2:2] - - - - - TIMSK2 - Timer/Counter Interrupt Mask register - 0x39 - - - TOIE2 - Timer/Counter2 Overflow Interrupt Enable - [0:0] - - - OCIE2A - Timer/Counter2 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE2B - Timer/Counter2 Output Compare Match B Interrupt Enable - [2:2] - - - - - - - TWI - Two Wire Serial Interface - 0xB8 - - - TWAMR - TWI (Slave) Address Mask Register - 0x5 - - - TWAM - TWI (Slave) Address Mask Bits - [7:1] - - - 0 - 127 - - - - - - - TWAR - TWI (Slave) Address register - 0x2 - - - TWGCE - TWI General Call Recognition Enable Bit - [0:0] - - - TWA - TWI (Slave) Address register Bits - [7:1] - - - 0 - 127 - - - - - - - TWBR - TWI Bit Rate register - 0x0 - - - 0 - 255 - - - - - TWCR - TWI Control Register - 0x4 - read-write - - - TWIE - TWI Interrupt Enable - [0:0] - - - TWEN - TWI Enable Bit - [2:2] - - - TWWC - TWI Write Collition Flag - [3:3] - read-only - - TWSTO - TWI Stop Condition Bit - [4:4] - - - TWSTA - TWI Start Condition Bit - [5:5] - - - TWEA - TWI Enable Acknowledge Bit - [6:6] - - - TWINT - TWI Interrupt Flag - [7:7] - - - - - TWDR - TWI Data register - 0x3 - - - 0 - 255 - - - - - TWSR - TWI Status Register - 0x1 - - - TWPS - TWI Prescaler - [1:0] - - true - - TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 - - - TWS - TWI Status - [7:3] - read-only - - 0 - 31 - - - - - - - - - USART0 - USART - 0xC0 - - - UBRR0 - USART Baud Rate Register Bytes - 0x4 - 16 - - - 0 - 65535 - - - - - UCSR0A - USART Control and Status Register A - 0x0 - read-write - - - MPCM0 - Multi-processor Communication Mode - [0:0] - - - U2X0 - Double the USART transmission speed - [1:1] - - - UPE0 - Parity Error - [2:2] - read-only - - DOR0 - Data overRun - [3:3] - read-only - - FE0 - Framing Error - [4:4] - read-only - - UDRE0 - USART Data Register Empty - [5:5] - read-only - - TXC0 - USART Transmit Complete - [6:6] - - - RXC0 - USART Receive Complete - [7:7] - read-only - - - - UCSR0B - USART Control and Status Register B - 0x1 - - - TXB80 - Transmit Data Bit 8 - [0:0] - - - RXB80 - Receive Data Bit 8 - [1:1] - read-only - - UCSZ02 - Character Size - [2:2] - - - TXEN0 - Transmitter Enable - [3:3] - - - RXEN0 - Receiver Enable - [4:4] - - - UDRIE0 - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE0 - TX Complete Interrupt Enable - [6:6] - - - RXCIE0 - RX Complete Interrupt Enable - [7:7] - - - - - UCSR0C - USART Control and Status Register C - 0x2 - - - UCPOL0 - Clock Polarity - [0:0] - UCPOL0read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 - - - UCSZ0 - Character Size - [2:1] - - - 0 - 3 - - - UCSZ0read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 - - - USBS0 - Stop Bit Select - [3:3] - - true - - USBS0read-writeSTOP11-bit0STOP22-bit1 - - - UPM0 - Parity Mode Bits - [5:4] - - true - - UPM0read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 - - - UMSEL0 - USART Mode Select - [7:6] - - true - - UMSEL0read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 - - - - - UDR0 - USART I/O Data Register - 0x6 - - - 0 - 255 - - - - - - - WDT - Watchdog Timer - 0x60 - - - WDTCSR - Watchdog Timer Control Register - 0x0 - read-write - - - WDE - Watch Dog Enable - [3:3] - - - WDCE - Watchdog Change Enable - [4:4] - - - WDIE - Watchdog Timeout Interrupt Enable - [6:6] - - - WDIF - Watchdog Timeout Interrupt Flag - [7:7] - - WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 - - WDPHWatchdog Timer Prescaler - High Bit[5:5] - - - - - - \ No newline at end of file diff --git a/misc/svd/atmega8.svd b/misc/svd/atmega8.svd deleted file mode 100644 index 0fca25e..0000000 --- a/misc/svd/atmega8.svd +++ /dev/null @@ -1,2775 +0,0 @@ - - Atmel - ATmega8 - 8 - 8 - read-write - 0 - 0xff - - - AC - Analog Comparator - 0x28 - - - ACSR - Analog Comparator Control And Status Register - 0x0 - read-only - - - ACIS - Analog Comparator Interrupt Mode Select bits - [1:0] - - true - - - - VAL_0x00 - Interrupt on Toggle - 0 - - - VAL_0x01 - Reserved - 1 - - - VAL_0x02 - Interrupt on Falling Edge - 2 - - - VAL_0x03 - Interrupt on Rising Edge - 3 - - - - - ACIC - Analog Comparator Input Capture Enable - [2:2] - - - ACIE - Analog Comparator Interrupt Enable - [3:3] - - - ACI - Analog Comparator Interrupt Flag - [4:4] - - - ACO - Analog Compare Output - [5:5] - - - ACBG - Analog Comparator Bandgap Select - [6:6] - - - ACD - Analog Comparator Disable - [7:7] - - - - - SFIOR - Special Function IO Register - 0x28 - - - ACME - Analog Comparator Multiplexer Enable - [3:3] - - - - - - - ADC - Analog-to-Digital Converter - 0x24 - - - ADC - ADC Data Register Bytes - 0x0 - 16 - - - 0 - 65535 - - - - - ADCSRA - The ADC Control and Status register - 0x2 - - - ADPS - ADC Prescaler Select Bits - [2:0] - - true - - - - VAL_0x00 - 2 - 0 - - - VAL_0x01 - 2 - 1 - - - VAL_0x02 - 4 - 2 - - - VAL_0x03 - 8 - 3 - - - VAL_0x04 - 16 - 4 - - - VAL_0x05 - 32 - 5 - - - VAL_0x06 - 64 - 6 - - - VAL_0x07 - 128 - 7 - - - - - ADIE - ADC Interrupt Enable - [3:3] - - - ADIF - ADC Interrupt Flag - [4:4] - - - ADFR - ADC Free Running Select - [5:5] - - - ADSC - ADC Start Conversion - [6:6] - - - ADEN - ADC Enable - [7:7] - - - - - ADMUX - The ADC multiplexer Selection Register - 0x3 - - - MUX - Analog Channel and Gain Selection Bits - [3:0] - - - 0 - 15 - - - - - ADLAR - Left Adjust Result - [5:5] - - - REFS - Reference Selection Bits - [7:6] - - true - - - - VAL_0x00 - AREF, Internal Vref turned off - 0 - - - VAL_0x01 - AVCC with external capacitor at AREF pin - 1 - - - VAL_0x02 - Reserved - 2 - - - VAL_0x03 - Internal 2.56V Voltage Reference with external capacitor at AREF pin - 3 - - - - - - - - - CPU - CPU Registers - 0x50 - - RESET - External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset - 0 - - - INT0 - External Interrupt Request 0 - 1 - - - INT1 - External Interrupt Request 1 - 2 - - - TIMER2_COMP - Timer/Counter2 Compare Match - 3 - - - TIMER2_OVF - Timer/Counter2 Overflow - 4 - - - TIMER1_CAPT - Timer/Counter1 Capture Event - 5 - - - TIMER1_COMPA - Timer/Counter1 Compare Match A - 6 - - - TIMER1_COMPB - Timer/Counter1 Compare Match B - 7 - - - TIMER1_OVF - Timer/Counter1 Overflow - 8 - - - TIMER0_OVF - Timer/Counter0 Overflow - 9 - - - SPI_STC - Serial Transfer Complete - 10 - - - USART_RXC - USART, Rx Complete - 11 - - - USART_UDRE - USART Data Register Empty - 12 - - - USART_TXC - USART, Tx Complete - 13 - - - ADC - ADC Conversion Complete - 14 - - - EE_RDY - EEPROM Ready - 15 - - - ANA_COMP - Analog Comparator - 16 - - - TWI - 2-wire Serial Interface - 17 - - - SPM_RDY - Store Program Memory Ready - 18 - - - - MCUCR - MCU Control Register - 0x5 - - - ISC0 - Interrupt Sense Control 0 Bits - [1:0] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change in INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC1 - Interrupt Sense Control 1 Bits - [3:2] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change in INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - SM - Sleep Mode Select - [6:4] - - true - - - - IDLE - Idle - 0 - - - ADC - ADC Noise Reduction (If Available) - 1 - - - PDOWN - Power Down - 2 - - - PSAVE - Power Save - 3 - - - VAL_0x04 - Reserved - 4 - - - VAL_0x05 - Reserved - 5 - - - STDBY - Standby - 6 - - - VAL_0x07 - Reserved - 7 - - - - - SE - Sleep Enable - [7:7] - - - - - MCUCSR - MCU Control And Status Register - 0x4 - - - PORF - Power-on reset flag - [0:0] - - - EXTRF - External Reset Flag - [1:1] - - - BORF - Brown-out Reset Flag - [2:2] - - - WDRF - Watchdog Reset Flag - [3:3] - - - - - OSCCAL - Oscillator Calibration Value - 0x1 - - - OSCCAL - Oscillator Calibration - [7:0] - - - 0 - 255 - - - - - - - SFIOR - Special Function IO Register - 0x0 - - - PSR10 - Prescaler Reset Timer/Counter1 and Timer/Counter0 - [0:0] - - - PUD - Pull-up Disable - [2:2] - - - ADHSM - ADC High Speed Mode - [4:4] - - - - - SPMCR - Store Program Memory Control Register - 0x7 - - - SPMEN - Store Program Memory Enable - [0:0] - - - PGERS - Page Erase - [1:1] - - - PGWRT - Page Write - [2:2] - - - BLBSET - Boot Lock Bit Set - [3:3] - - - RWWSRE - Read-While-Write Section Read Enable - [4:4] - - - RWWSB - Read-While-Write Section Busy - [6:6] - - - SPMIE - SPM Interrupt Enable - [7:7] - - - - - - - EEPROM - EEPROM - 0x3C - - - EEAR - EEPROM Address Register Bytes - 0x2 - 16 - - - 0 - 65535 - - - - - EECR - EEPROM Control Register - 0x0 - - - EERE - EEPROM Read Enable - [0:0] - - - EEWE - EEPROM Write Enable - [1:1] - - - EEMWE - EEPROM Master Write Enable - [2:2] - - - EERIE - EEPROM Ready Interrupt Enable - [3:3] - - - - - EEDR - EEPROM Data Register - 0x1 - - - 0 - 255 - - - - - - - EXINT - External Interrupts - 0x55 - - - GICR - General Interrupt Control Register - 0x6 - - - IVCE - Interrupt Vector Change Enable - [0:0] - - - IVSEL - Interrupt Vector Select - [1:1] - - - INT - External Interrupt Request 1 Enable - [7:6] - - - 0 - 3 - - - - - - - GIFR - General Interrupt Flag Register - 0x5 - - - INTF - External Interrupt Flags - [7:6] - - - 0 - 3 - - - - - - - MCUCR - MCU Control Register - 0x0 - - - ISC0 - Interrupt Sense Control 0 Bits - [1:0] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - ISC1 - Interrupt Sense Control 1 Bits - [3:2] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - - - - - FUSE - Fuses - 0x0 - - - HIGH - <TBD> - 0x1 - - - BOOTRST - Boot Reset vector Enabled - [0:0] - - - BOOTSZ - Select Boot Size - [2:1] - - true - - - - 1024W_0C00 - Boot Flash size=1024 words Boot address=$0C00 - 0 - - - 512W_0E00 - Boot Flash size=512 words Boot address=$0E00 - 1 - - - 256W_0F00 - Boot Flash size=256 words Boot address=$0F00 - 2 - - - 128W_0F80 - Boot Flash size=128 words Boot address=$0F80 - 3 - - - - - EESAVE - Preserve EEPROM through the Chip Erase cycle - [3:3] - - - CKOPT - CKOPT fuse (operation dependent of CKSEL fuses) - [4:4] - - - SPIEN - Serial program downloading (SPI) enabled - [5:5] - - - WDTON - Watch-dog Timer always on - [6:6] - - - RSTDISBL - Reset Disabled (Enable PC6 as i/o pin) - [7:7] - - - - - LOW - <TBD> - 0x0 - - - SUT_CKSEL - Select Clock Source - [5:0] - - true - - - - EXTCLK_6CK_0MS - Ext. Clock; Start-up time: 6 CK + 0 ms - 0 - - - INTRCOSC_1MHZ_6CK_0MS - Int. RC Osc. 1 MHz; Start-up time: 6 CK + 0 ms - 1 - - - INTRCOSC_2MHZ_6CK_0MS - Int. RC Osc. 2 MHz; Start-up time: 6 CK + 0 ms - 2 - - - INTRCOSC_4MHZ_6CK_0MS - Int. RC Osc. 4 MHz; Start-up time: 6 CK + 0 ms - 3 - - - INTRCOSC_8MHZ_6CK_0MS - Int. RC Osc. 8 MHz; Start-up time: 6 CK + 0 ms - 4 - - - EXTRCOSC_XX_0MHZ9_18CK_0MS - Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 0 ms - 5 - - - EXTRCOSC_0MHZ9_3MHZ_18CK_0MS - Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 0 ms - 6 - - - EXTRCOSC_3MHZ_8MHZ_18CK_0MS - Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 0 ms - 7 - - - EXTRCOSC_8MHZ_12MHZ_18CK_0MS - Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 0 ms - 8 - - - EXTLOFXTAL_1KCK_4MS - Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4 ms - 9 - - - EXTLOFXTALRES_258CK_4MS - Ext. Crystal/Resonator Low Freq.; Start-up time: 258 CK + 4 ms - 10 - - - EXTLOFXTALRES_1KCK_64MS - Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 64 ms - 11 - - - EXTMEDFXTALRES_258CK_4MS - Ext. Crystal/Resonator Medium Freq.; Start-up time: 258 CK + 4 ms - 12 - - - EXTMEDFXTALRES_1KCK_64MS - Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 64 ms - 13 - - - EXTHIFXTALRES_258CK_4MS - Ext. Crystal/Resonator High Freq.; Start-up time: 258 CK + 4 ms - 14 - - - EXTHIFXTALRES_1KCK_64MS - Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 64 ms - 15 - - - EXTCLK_6CK_4MS - Ext. Clock; Start-up time: 6 CK + 4 ms - 16 - - - INTRCOSC_1MHZ_6CK_4MS - Int. RC Osc. 1 MHz; Start-up time: 6 CK + 4 ms - 17 - - - INTRCOSC_2MHZ_6CK_4MS - Int. RC Osc. 2 MHz; Start-up time: 6 CK + 4 ms - 18 - - - INTRCOSC_4MHZ_6CK_4MS - Int. RC Osc. 4 MHz; Start-up time: 6 CK + 4 ms - 19 - - - INTRCOSC_8MHZ_6CK_4MS - Int. RC Osc. 8 MHz; Start-up time: 6 CK + 4 ms - 20 - - - EXTRCOSC_XX_0MHZ9_18CK_4MS - Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 4 ms - 21 - - - EXTRCOSC_0MHZ9_3MHZ_18CK_4MS - Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 4 ms - 22 - - - EXTRCOSC_3MHZ_8MHZ_18CK_4MS - Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 4 ms - 23 - - - EXTRCOSC_8MHZ_12MHZ_18CK_4MS - Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 4 ms - 24 - - - EXTLOFXTAL_1KCK_64MS - Ext. Low-Freq. Crystal; Start-up time: 1K CK + 64 ms - 25 - - - EXTLOFXTALRES_258CK_64MS - Ext. Crystal/Resonator Low Freq.; Start-up time: 258 CK + 64 ms - 26 - - - EXTLOFXTALRES_16KCK_0MS - Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 0 ms - 27 - - - EXTMEDFXTALRES_258CK_64MS - Ext. Crystal/Resonator Medium Freq.; Start-up time: 258 CK + 64 ms - 28 - - - EXTMEDFXTALRES_16KCK_0MS - Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 0 ms - 29 - - - EXTHIFXTALRES_258CK_64MS - Ext. Crystal/Resonator High Freq.; Start-up time: 258 CK + 64 ms - 30 - - - EXTHIFXTALRES_16KCK_0MS - Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 0 ms - 31 - - - EXTCLK_6CK_64MS - Ext. Clock; Start-up time: 6 CK + 64 ms - 32 - - - INTRCOSC_1MHZ_6CK_64MS_DEFAULT - Int. RC Osc. 1 MHz; Start-up time: 6 CK + 64 ms; default value - 33 - - - INTRCOSC_2MHZ_6CK_64MS - Int. RC Osc. 2 MHz; Start-up time: 6 CK + 64 ms - 34 - - - INTRCOSC_4MHZ_6CK_64MS - Int. RC Osc. 4 MHz; Start-up time: 6 CK + 64 ms - 35 - - - INTRCOSC_8MHZ_6CK_64MS - Int. RC Osc. 8 MHz; Start-up time: 6 CK + 64 ms - 36 - - - EXTRCOSC_XX_0MHZ9_18CK_64MS - Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 64 ms - 37 - - - EXTRCOSC_0MHZ9_3MHZ_18CK_64MS - Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 64 ms - 38 - - - EXTRCOSC_3MHZ_8MHZ_18CK_64MS - Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 64 ms - 39 - - - EXTRCOSC_8MHZ_12MHZ_18CK_64MS - Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 64 ms - 40 - - - EXTLOFXTAL_32KCK_64MS - Ext. Low-Freq. Crystal; Start-up time: 32K CK + 64 ms - 41 - - - EXTLOFXTALRES_1KCK_0MS - Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 0 ms - 42 - - - EXTLOFXTALRES_16KCK_4MS - Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 4 ms - 43 - - - EXTMEDFXTALRES_1KCK_0MS - Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 0 ms - 44 - - - EXTMEDFXTALRES_16KCK_4MS - Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 4 ms - 45 - - - EXTHIFXTALRES_1KCK_0MS - Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 0 ms - 46 - - - EXTHIFXTALRES_16KCK_4MS - Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 4 ms - 47 - - - EXTRCOSC_XX_0MHZ9_6CK_4MS - Ext. RC Osc. - 0.9 MHz; Start-up time: 6 CK + 4 ms - 53 - - - EXTRCOSC_0MHZ9_3MHZ_6CK_4MS - Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 6 CK + 4 ms - 54 - - - EXTRCOSC_3MHZ_8MHZ_6CK_4MS - Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 6 CK + 4 ms - 55 - - - EXTRCOSC_8MHZ_12MHZ_6CK_4MS - Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 6 CK + 4 ms - 56 - - - EXTLOFXTALRES_1KCK_4MS - Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 4 ms - 58 - - - EXTLOFXTALRES_16KCK_64MS - Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 64 ms - 59 - - - EXTMEDFXTALRES_1KCK_4MS - Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 4 ms - 60 - - - EXTMEDFXTALRES_16KCK_64MS - Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 64 ms - 61 - - - EXTHIFXTALRES_1KCK_4MS - Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 4 ms - 62 - - - EXTHIFXTALRES_16KCK_64MS - Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 64 ms - 63 - - - - - BODEN - Brown-out detection enabled - [6:6] - - - BODLEVEL - Brownout detector trigger level - [7:7] - - true - - - - 4V0 - Brown-out detection at VCC=4.0 V - 0 - - - 2V7 - Brown-out detection at VCC=2.7 V - 1 - - - - - - - - - LOCKBIT - Lockbits - 0x0 - - - LOCKBIT - <TBD> - 0x0 - - - LB - Memory Lock - [1:0] - - true - - - - PROG_VER_DISABLED - Further programming and verification disabled - 0 - - - PROG_DISABLED - Further programming disabled - 2 - - - NO_LOCK - No memory lock features enabled - 3 - - - - - BLB0 - Boot Loader Protection Mode - [3:2] - - true - - - - LPM_SPM_DISABLE - LPM and SPM prohibited in Application Section - 0 - - - LPM_DISABLE - LPM prohibited in Application Section - 1 - - - SPM_DISABLE - SPM prohibited in Application Section - 2 - - - NO_LOCK - No lock on SPM and LPM in Application Section - 3 - - - - - BLB1 - Boot Loader Protection Mode - [5:4] - - true - - - - LPM_SPM_DISABLE - LPM and SPM prohibited in Boot Section - 0 - - - LPM_DISABLE - LPM prohibited in Boot Section - 1 - - - SPM_DISABLE - SPM prohibited in Boot Section - 2 - - - NO_LOCK - No lock on SPM and LPM in Boot Section - 3 - - - - - - - - - PORTB - I/O Port - 0x36 - - - DDRB - Port B Data Direction Register - 0x1 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PINB - Port B Input Pins - 0x0 - read-write - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PORTB - Port B Data Register - 0x2 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - - - PORTC - I/O Port - 0x33 - - - DDRC - Port C Data Direction Register - 0x1 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - - - PINC - Port C Input Pins - 0x0 - read-write - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - - - PORTC - Port C Data Register - 0x2 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - - - - - PORTD - I/O Port - 0x30 - - - DDRD - Port D Data Direction Register - 0x1 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PIND - Port D Input Pins - 0x0 - read-write - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PORTD - Port D Data Register - 0x2 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - - - SPI - Serial Peripheral Interface - 0x2D - - - SPCR - SPI Control Register - 0x0 - - - SPR - SPI Clock Rate Selects - [1:0] - - true - - - - VAL_0x00 - fosc/4 - 0 - - - VAL_0x01 - fosc/16 - 1 - - - VAL_0x02 - fosc/64 - 2 - - - VAL_0x03 - fosc/128 - 3 - - - - - CPHA - Clock Phase - [2:2] - - - CPOL - Clock polarity - [3:3] - - - MSTR - Master/Slave Select - [4:4] - - - DORD - Data Order - [5:5] - - - SPE - SPI Enable - [6:6] - - - SPIE - SPI Interrupt Enable - [7:7] - - - - - SPDR - SPI Data Register - 0x2 - - - 0 - 255 - - - - - SPSR - SPI Status Register - 0x1 - read-only - - - SPI2X - Double SPI Speed Bit - [0:0] - - - WCOL - Write Collision Flag - [6:6] - - - SPIF - SPI Interrupt Flag - [7:7] - - - - - - - TC0 - Timer/Counter, 8-bit - 0x52 - - - TCCR0 - Timer/Counter0 Control Register - 0x1 - - - CS00 - Clock Select0 bit 0 - [0:0] - - true - - - - VAL_0x00 - No Clock Source (Stopped) - 0 - - - VAL_0x01 - Running, No Prescaling - 1 - - - - - CS01 - Clock Select0 bit 1 - [1:1] - - - CS02 - Clock Select0 bit 2 - [2:2] - - - - - TCNT0 - Timer Counter 0 - 0x0 - - - 0 - 255 - - - - - TIFR - Timer/Counter Interrupt Flag register - 0x6 - - - TOV0 - Timer/Counter0 Overflow Flag - [0:0] - - - - - TIMSK - Timer/Counter Interrupt Mask Register - 0x7 - - - TOIE0 - Timer/Counter0 Overflow Interrupt Enable - [0:0] - - - - - - - TC1 - Timer/Counter, 16-bit - 0x46 - - - ICR1 - Timer/Counter1 Input Capture Register Bytes - 0x0 - 16 - - - 0 - 65535 - - - - - OCR1A - Timer/Counter1 Output Compare Register Bytes - 0x4 - 16 - - - 0 - 65535 - - - - - OCR1B - Timer/Counter1 Output Compare Register Bytes - 0x2 - 16 - - - 0 - 65535 - - - - - TCCR1A - Timer/Counter1 Control Register A - 0x9 - - - WGM1 - Waveform Generation Mode - [1:0] - - - 0 - 3 - - - - - FOC1B - Force Output Compare 1B - [2:2] - - - FOC1A - Force Output Compare 1A - [3:3] - - - COM1B - Compare Output Mode 1B, bits - [5:4] - - - 0 - 3 - - - - - COM1A - Compare Output Mode 1A, bits - [7:6] - - - 0 - 3 - - - - - - - TCCR1B - Timer/Counter1 Control Register B - 0x8 - - - CS1 - Prescaler source of Timer/Counter 1 - [2:0] - - true - - - - VAL_0x00 - No Clock Source (Stopped) - 0 - - - VAL_0x01 - Running, No Prescaling - 1 - - - VAL_0x02 - Running, CLK/8 - 2 - - - VAL_0x03 - Running, CLK/64 - 3 - - - VAL_0x04 - Running, CLK/256 - 4 - - - VAL_0x05 - Running, CLK/1024 - 5 - - - VAL_0x06 - Running, ExtClk Tx Falling Edge - 6 - - - VAL_0x07 - Running, ExtClk Tx Rising Edge - 7 - - - - - WGM1 - Waveform Generation Mode - [4:3] - - - 0 - 3 - - - - - ICES1 - Input Capture 1 Edge Select - [6:6] - - - ICNC1 - Input Capture 1 Noise Canceler - [7:7] - - - - - TCNT1 - Timer/Counter1 Bytes - 0x6 - 16 - - - 0 - 65535 - - - - - TIFR - Timer/Counter Interrupt Flag register - 0x12 - read-only - - - TOV1 - Timer/Counter1 Overflow Flag - [2:2] - - - OCF1B - Output Compare Flag 1B - [3:3] - - - OCF1A - Output Compare Flag 1A - [4:4] - - - ICF1 - Input Capture Flag 1 - [5:5] - - - - - TIMSK - Timer/Counter Interrupt Mask Register - 0x13 - - - TOIE1 - Timer/Counter1 Overflow Interrupt Enable - [2:2] - - - OCIE1B - Timer/Counter1 Output CompareB Match Interrupt Enable - [3:3] - - - OCIE1A - Timer/Counter1 Output CompareA Match Interrupt Enable - [4:4] - - - TICIE1 - Timer/Counter1 Input Capture Interrupt Enable - [5:5] - - - - - - - TC2 - Timer/Counter, 8-bit Async - 0x42 - - - ASSR - Asynchronous Status Register - 0x0 - - - TCR2UB - Timer/counter Control Register2 Update Busy - [0:0] - - - OCR2UB - Output Compare Register2 Update Busy - [1:1] - - - TCN2UB - Timer/Counter2 Update Busy - [2:2] - - - AS2 - Asynchronous Timer/counter2 - [3:3] - - - - - OCR2 - Timer/Counter2 Output Compare Register - 0x1 - - - 0 - 255 - - - - - SFIOR - Special Function IO Register - 0xE - - - PSR2 - Prescaler Reset Timer/Counter2 - [1:1] - - - - - TCCR2 - Timer/Counter2 Control Register - 0x3 - - - CS2 - Clock Select bits - [2:0] - - true - - - - VAL_0x00 - No Clock Source (Stopped) - 0 - - - VAL_0x01 - Running, No Prescaling - 1 - - - VAL_0x02 - Running, CLK/8 - 2 - - - VAL_0x03 - Running, CLK/32 - 3 - - - VAL_0x04 - Running, CLK/64 - 4 - - - VAL_0x05 - Running, CLK/128 - 5 - - - VAL_0x06 - Running, CLK/256 - 6 - - - VAL_0x07 - Running, CLK/1024 - 7 - - - - - WGM21 - Waveform Generation Mode - [3:3] - - - COM2 - Compare Output Mode bits - [5:4] - - - 0 - 3 - - - - - WGM20 - Waveform Genration Mode - [6:6] - - true - - - - VAL_0x00 - Normal - 0 - - - VAL_0x01 - CTC - 1 - - - - - FOC2 - Force Output Compare - [7:7] - - - - - TCNT2 - Timer/Counter2 - 0x2 - - - 0 - 255 - - - - - TIFR - Timer/Counter Interrupt Flag Register - 0x16 - read-only - - - TOV2 - Timer/Counter2 Overflow Flag - [6:6] - - - OCF2 - Output Compare Flag 2 - [7:7] - - - - - TIMSK - Timer/Counter Interrupt Mask register - 0x17 - - - TOIE2 - Timer/Counter2 Overflow Interrupt Enable - [6:6] - - - OCIE2 - Timer/Counter2 Output Compare Match Interrupt Enable - [7:7] - - - - - - - TWI - Two Wire Serial Interface - 0x20 - - - TWAR - TWI (Slave) Address register - 0x2 - - - TWGCE - TWI General Call Recognition Enable Bit - [0:0] - - - TWA - TWI (Slave) Address register Bits - [7:1] - - - 0 - 127 - - - - - - - TWBR - TWI Bit Rate register - 0x0 - - - 0 - 255 - - - - - TWCR - TWI Control Register - 0x36 - read-only - - - TWIE - TWI Interrupt Enable - [0:0] - - - TWEN - TWI Enable Bit - [2:2] - - - TWWC - TWI Write Collition Flag - [3:3] - - - TWSTO - TWI Stop Condition Bit - [4:4] - - - TWSTA - TWI Start Condition Bit - [5:5] - - - TWEA - TWI Enable Acknowledge Bit - [6:6] - - - TWINT - TWI Interrupt Flag - [7:7] - - - - - TWDR - TWI Data register - 0x3 - - - 0 - 255 - - - - - TWSR - TWI Status Register - 0x1 - - - TWPS - TWI Prescaler - [1:0] - - true - - - - VAL_0x00 - 1 - 0 - - - VAL_0x01 - 4 - 1 - - - VAL_0x02 - 16 - 2 - - - VAL_0x03 - 64 - 3 - - - - - TWS - TWI Status - [7:3] - - - 0 - 31 - - - - - - - - - USART - USART - 0x29 - - - UBRRH - USART Baud Rate Register Hight Byte - 0x17 - - - 0 - 255 - - - - - UBRRL - USART Baud Rate Register Low Byte - 0x0 - - - 0 - 255 - - - - - UCSRA - USART Control and Status Register A - 0x2 - read-only - - - MPCM - Multi-processor Communication Mode - [0:0] - - - U2X - Double the USART transmission speed - [1:1] - - - UPE - Parity Error - [2:2] - - - DOR - Data overRun - [3:3] - - - FE - Framing Error - [4:4] - - - UDRE - USART Data Register Empty - [5:5] - - - TXC - USART Transmitt Complete - [6:6] - - - RXC - USART Receive Complete - [7:7] - - - - - UCSRB - USART Control and Status Register B - 0x1 - - - TXB8 - Transmit Data Bit 8 - [0:0] - - - RXB8 - Receive Data Bit 8 - [1:1] - - - UCSZ2 - Character Size - [2:2] - - - TXEN - Transmitter Enable - [3:3] - - - RXEN - Receiver Enable - [4:4] - - - UDRIE - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE - TX Complete Interrupt Enable - [6:6] - - - RXCIE - RX Complete Interrupt Enable - [7:7] - - - - - UCSRC - USART Control and Status Register C - 0x17 - - - UCPOL - Clock Polarity - [0:0] - - - UCSZ - Character Size - [2:1] - - - 0 - 3 - - - - - USBS - Stop Bit Select - [3:3] - - true - - - - VAL_0x00 - 1-bit - 0 - - - VAL_0x01 - 2-bit - 1 - - - - - UPM - Parity Mode Bits - [5:4] - - true - - - - VAL_0x00 - Disabled - 0 - - - VAL_0x01 - Reserved - 1 - - - VAL_0x02 - Enabled, Even Parity - 2 - - - VAL_0x03 - Enabled, Odd Parity - 3 - - - - - UMSEL - USART Mode Select - [6:6] - - true - - - - VAL_0x00 - Asynchronous Operation - 0 - - - VAL_0x01 - Synchronous Operation - 1 - - - - - URSEL - Register Select - [7:7] - - - - - UDR - USART I/O Data Register - 0x3 - - - 0 - 255 - - - - - - - WDT - Watchdog Timer - 0x41 - - - WDTCR - Watchdog Timer Control Register - 0x0 - - - WDP - Watch Dog Timer Prescaler bits - [2:0] - - true - - - - VAL_0x00 - Oscillator Cycles 16K - 0 - - - VAL_0x01 - Oscillator Cycles 32K - 1 - - - VAL_0x02 - Oscillator Cycles 64K - 2 - - - VAL_0x03 - Oscillator Cycles 128K - 3 - - - VAL_0x04 - Oscillator Cycles 256K - 4 - - - VAL_0x05 - Oscillator Cycles 512K - 5 - - - VAL_0x06 - Oscillator Cycles 1024K - 6 - - - VAL_0x07 - Oscillator Cycles 2048K - 7 - - - - - WDE - Watch Dog Enable - [3:3] - - - WDCE - Watchdog Change Enable - [4:4] - - - - - - - \ No newline at end of file diff --git a/misc/svd/attiny84.svd b/misc/svd/attiny84.svd deleted file mode 100644 index 2f65316..0000000 --- a/misc/svd/attiny84.svd +++ /dev/null @@ -1,1627 +0,0 @@ - - Atmel - ATtiny84 - 8 - 8 - read-write - 0 - 0xff - - - AC - Analog Comparator - 0x21 - - - ACSR - Analog Comparator Control And Status Register - 0x7 - read-write - - - ACIS - Analog Comparator Interrupt Mode Select - [1:0] - - true - - ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 - - - ACIC - Analog Comparator Input Capture Enable - [2:2] - - - ACIE - Analog Comparator Interrupt Enable - [3:3] - - - ACI - Analog Comparator Interrupt Flag - [4:4] - - - ACO - Analog Compare Output - [5:5] - read-only - - ACBG - Analog Comparator Bandgap Select - [6:6] - - - ACD - Analog Comparator Disable - [7:7] - - - - - ADCSRB - ADC Control and Status Register B - 0x2 - - - ACME - Analog Comparator Multiplexer Enable - [6:6] - - - - - DIDR0 - Digital Input Disable Register 0 - 0x0 - - - ADC1D - ADC1 (AIN0) Digital input buffer disable - [1:1] - - ADC2DADC2 (AIN1) Digital input buffer disable21read-write - - - - - - ADC - Analog-to-Digital Converter - 0x21 - - - ADC - ADC Data Register Bytes - 0x3 - 16 - - - 0 - 65535 - - - - - ADCSRA - ADC Control and Status Register A - 0x5 - read-write - - - ADPS - ADC Prescaler Select Bits - [2:0] - - true - - ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 - - - ADIE - ADC Interrupt Enable - [3:3] - - - ADIF - ADC Interrupt Flag - [4:4] - - - ADATE - ADC Auto Trigger Enable - [5:5] - - - ADSC - ADC Start Conversion - [6:6] - - - ADEN - ADC Enable - [7:7] - - - - - ADCSRB - ADC Control and Status Register B - 0x2 - - - ADTS - ADC Auto Trigger Source bits - [2:0] - - true - - ADTSread-writeFREEFree Running mode0ACAnalog Comparator1INT0External Interrupt Request 02TC0_CMATimer/Counter0 Compare Match A3TC0_OVFTimer/Counter0 Overflow4TC0_CMBTimer/Counter0 Compare Match B5PCIRPin Change Interrupt Request6 - - - ADLAR - ADC Left Adjust Result - [4:4] - - - BIN - Bipolar Input Mode - [7:7] - - - - - ADMUX - ADC Multiplexer Selection Register - 0x6 - - - 0 - 255 - - - MUXAnalog Channel and Gain Selection Bits06read-writeMUXread-writeADC0Single-ended Input ADC00ADC1Single-ended Input ADC11ADC2Single-ended Input ADC22ADC3Single-ended Input ADC33ADC4Single-ended Input ADC44ADC5Single-ended Input ADC55ADC6Single-ended Input ADC66ADC7Single-ended Input ADC77ADC_GND0V (GND)32ADC_VBGInternal Reference (VBG)33TEMPSENSTemperature sensor34ADC0_ADC0_20XDifferential Inputs Positive ADC0 Negative ADC0 20x Gain35ADC0_ADC1_1XDifferential Inputs Positive ADC0 Negative ADC1 1x Gain8ADC0_ADC1_20XDifferential Inputs Postive ADC0 Negative ADC1 20x Gain9ADC0_ADC3_1XDifferential Inputs Positive ADC0 Negative ADC3 1x Gain10ADC0_ADC3_20XDifferential Inputs Positive ADC0 Negative ADC3 20x Gain11ADC1_ADC0_1XDifferential Inputs Positive ADC1 Negative ADC0 1x Gain40ADC1_ADC0_20XDifferential Inputs Positive ADC1 Negative ADC0 20x Gain41ADC1_ADC2_1XDifferential Inputs Positive ADC1 Negative ADC2 1x Gain12ADC1_ADC2_20XDifferential Inputs Positive ADC1 Negative ADC2 20x Gain13ADC1_ADC3_1XDifferential Inputs Positive ADC1 Negative ADC3 1x Gain14ADC1_ADC3_20XDifferential Inputs Positive ADC1 Negative ADC3 20x Gain15ADC2_ADC1_1XDifferential Inputs Positive ADC2 Negative ADC2 1x Gain44ADC2_ADC1_20XDifferential Inputs Positive ADC2 Negative ADC2 20x Gain45ADC2_ADC3_1XDifferential Inputs Positive ADC2 Negative ADC3 1x Gain16ADC2_ADC3_20XDifferential Inputs Positive ADC2 Negative ADC3 20x Gain17ADC3_ADC0_1XDifferential Inputs Positive ADC3 Negative ADC0 1x Gain42ADC3_ADC0_20XDifferential Inputs Positive ADC3 Negative ADC0 20x Gain43ADC3_ADC1_1XDifferential Inputs Positive ADC3 Negative ADC1 1x Gain46ADC3_ADC1_20XDifferential Inputs Positive ADC3 Negative ADC1 20x Gain47ADC3_ADC2_1XDifferential Inputs Positive ADC3 Negative ADC2 1x Gain48ADC3_ADC2_20XDifferential Inputs Positive ADC3 Negative ADC2 20x Gain49ADC3_ADC3_1XDifferential Inputs Positive ADC3 Negative ADC3 1x Gain36ADC3_ADC3_20XDifferential Inputs Positive ADC3 Negative ADC3 20x Gain37ADC3_ADC4_1XDifferential Inputs Positive ADC4 Negative ADC0 1x Gain18ADC3_ADC4_20XDifferential Inputs Positive ADC4 Negative ADC0 20x Gain19ADC3_ADC5_1XDifferential Inputs Positive ADC5 Negative ADC1 1x Gain20ADC3_ADC5_20XDifferential Inputs Positive ADC5 Negative ADC1 20x Gain21ADC3_ADC6_1XDifferential Inputs Positive ADC6 Negative ADC2 1x Gain22ADC3_ADC6_20XDifferential Inputs Positive ADC6 Negative ADC2 20x Gain23ADC3_ADC7_1XDifferential Inputs Positive ADC7 Negative ADC3 1x Gain24ADC3_ADC7_20XDifferential Inputs Positive ADC7 Negative ADC3 20x Gain25ADC4_ADC3_1XDifferential Inputs Positive ADC4 Negative ADC3 1x Gain50ADC4_ADC3_20XDifferential Inputs Positive ADC4 Negative ADC3 20x Gain51ADC4_ADC5_1XDifferential Inputs Positive ADC4 Negative ADC5 1x Gain26ADC4_ADC5_20XDifferential Inputs Positive ADC4 Negative ADC5 20x Gain27ADC5_ADC3_1XDifferential Inputs Positive ADC5 Negative ADC3 1x Gain52ADC5_ADC3_20XDifferential Inputs Positive ADC5 Negative ADC3 20x Gain53ADC5_ADC4_1XDifferential Inputs Positive ADC5 Negative ADC4 1x Gain58ADC5_ADC4_20XDifferential Inputs Positive ADC5 Negative ADC4 20x Gain59ADC5_ADC6_1XDifferential Inputs Positive ADC5 Negative ADC6 1x Gain28ADC5_ADC6_20XDifferential Inputs Positive ADC5 Negative ADC6 20x Gain29ADC6_ADC3_1XDifferential Inputs Positive ADC6 Negative ADC3 1x Gain54ADC6_ADC3_20XDifferential Inputs Positive ADC6 Negative ADC3 20x Gain55ADC6_ADC5_1XDifferential Inputs Positive ADC6 Negative ADC5 1x Gain60ADC6_ADC5_20XDifferential Inputs Positive ADC6 Negative ADC5 20x Gain61ADC6_ADC7_1XDifferential Inputs Positive ADC6 Negative ADC7 1x Gain30ADC6_ADC7_20XDifferential Inputs Positive ADC6 Negative ADC7 20x Gain31ADC7_ADC3_1XDifferential Inputs Positive ADC7 Negative ADC3 1x Gain56ADC7_ADC3_20XDifferential Inputs Positive ADC7 Negative ADC3 20x Gain57ADC7_ADC6_1XDifferential Inputs Positive ADC7 Negative ADC6 1x Gain62ADC7_ADC6_20XDifferential Inputs Positive ADC7 Negative ADC6 20x Gain63ADC7_ADC7_1XDifferential Inputs Positive ADC7 Negative ADC7 1x Gain38ADC7_ADC7_20XDifferential Inputs Positive ADC7 Negative ADC7 20x Gain39 - - REFSReference Selection Bits62read-writeREFSread-writeVCCVcc used as Voltage Reference, disconnected from Aref0AREFExternal Voltage Reference at AREF pin, Internal Voltage Reference turned off1INTERNALInternal 1.1V Voltage Reference2 - - - - DIDR0 - Digital Input Disable Register 0 - 0x0 - - - 0 - 255 - - - - - - - BOOT_LOAD - Bootloader - 0x57 - - - SPMCSR - Store Program Memory Control Register - 0x0 - read-only - - - SPMEN - Store Program Memory Enable - [0:0] - - - PGERS - Page Erase - [1:1] - - - PGWRT - Page Write - [2:2] - - - RFLB - Read fuse and lock bits - [3:3] - - - CTPB - Clear temporary page buffer - [4:4] - - - - - - - CPU - CPU Registers - 0x20 - - RESET - External Pin, Power-on Reset, Brown-out Reset,Watchdog Reset - 0 - - - EXT_INT0 - External Interrupt Request 0 - 1 - - - PCINT0 - Pin Change Interrupt Request 0 - 2 - - - PCINT1 - Pin Change Interrupt Request 1 - 3 - - - WDT - Watchdog Time-out - 4 - - - TIM1_CAPT - Timer/Counter1 Capture Event - 5 - - - TIM1_COMPA - Timer/Counter1 Compare Match A - 6 - - - TIM1_COMPB - Timer/Counter1 Compare Match B - 7 - - - TIM1_OVF - Timer/Counter1 Overflow - 8 - - - TIM0_COMPA - Timer/Counter0 Compare Match A - 9 - - - TIM0_COMPB - Timer/Counter0 Compare Match B - 10 - - - TIM0_OVF - Timer/Counter0 Overflow - 11 - - - ANA_COMP - Analog Comparator - 12 - - - ADC - ADC Conversion Complete - 13 - - - EE_RDY - EEPROM Ready - 14 - - - USI_STR - USI START - 15 - - - USI_OVF - USI Overflow - 16 - - - - CLKPR - Clock Prescale Register - 0x26 - - - CLKPS - Clock Prescaler Select Bits - [3:0] - - true - - CLKPSread-writePRESCALER_1Prescaler Value 10PRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287PRESCALER_256Prescaler Value 2568 - - - CLKPCE - Clock Prescaler Change Enable - [7:7] - - - - - GPIOR0 - General Purpose I/O Register 0 - 0x13 - - - 0 - 255 - - - - - GPIOR1 - General Purpose I/O Register 1 - 0x14 - - - 0 - 255 - - - - - GPIOR2 - General Purpose I/O Register 2 - 0x15 - - - 0 - 255 - - - - - MCUCR - MCU Control Register - 0x35 - - - SM - Sleep Mode Select Bits - [4:3] - - true - - - - IDLE - Idle - 0 - - - ADC - ADC Noise Reduction (If Available) - 1 - - - PDOWN - Power Down - 2 - - - STDBY - Standby - 3 - - - - - SE - Sleep Enable - [5:5] - - - PUD - Pull-up Disable - [6:6] - - BODSBOD Sleep (available on some devices)71read-write - BODSEBOD Sleep Enable (available on some devices)21read-write - - - - MCUSR - MCU Status Register - 0x34 - - - PORF - Power-on reset flag - [0:0] - - - EXTRF - External Reset Flag - [1:1] - - - BORF - Brown-out Reset Flag - [2:2] - - - WDRF - Watchdog Reset Flag - [3:3] - - - - - OSCCAL - Oscillator Calibration Value - 0x31 - read-write - - - OSCCAL - Oscillator Calibration - [7:0] - - - 0 - 255 - - - - - - - PRR - Power Reduction Register - 0x0 - - - PRADC - Power Reduction ADC - [0:0] - - - PRUSI - Power Reduction USI - [1:1] - - - PRTIM0 - Power Reduction Timer/Counter0 - [2:2] - - - PRTIM1 - Power Reduction Timer/Counter1 - [3:3] - - - - - - - EEPROM - EEPROM - 0x3C - - - EEAR - EEPROM Address Register Bytes - 0x2 - 16 - - - 0 - 65535 - - - - - EECR - EEPROM Control Register - 0x0 - - - EERE - EEPROM Read Enable - [0:0] - - - EEPE - EEPROM Write Enable - [1:1] - - - EEMPE - EEPROM Master Write Enable - [2:2] - - - EERIE - EEPROM Ready Interrupt Enable - [3:3] - - - EEPM - EEPROM Programming Mode Bits - [5:4] - - true - - EEPMread-writeATOMICAtomic (erase and write in one operation)0ERASEErase only1WRITEWrite only2 - - - - - EEDR - EEPROM Data Register - 0x1 - - - 0 - 255 - - - - - - - EXINT - External Interrupts - 0x32 - - - GIFR - General Interrupt Flag register - 0x28 - read-write - - - PCIF - Pin Change Interrupt Flags - [5:4] - - - 0 - 3 - - - - - INTF0 - External Interrupt Flag 0 - [6:6] - - - - - GIMSK - General Interrupt Mask Register - 0x29 - - - PCIE - Pin Change Interrupt Enables - [5:4] - - - 0 - 3 - - - - - INT0 - External Interrupt Request 0 Enable - [6:6] - - - - - MCUCR - MCU Control Register - 0x23 - - ISC0Interrupt Sense Control 0 bits02read-writeISC0read-writeLOWThe low level of INTx generates an interrupt request0TOGGLEAny logical change on INTx generates an interrupt request1FALLINGThe falling edge of INTx generates an interrupt request2RISINGThe rising edge of INTx generates an interrupt request3 - - - - - PCMSK0 - Pin Change Enable Mask 0 - 0x0 - - - 0 - 255 - - - - - PCMSK1 - Pin Change Enable Mask 1 - 0xE - - - 0 - 255 - - - - - - - FUSE - Fuses - 0x0 - - - EXTENDED - <TBD> - 0x2 - - - SELFPRGEN - Self Programming enable - [0:0] - - - - - HIGH - <TBD> - 0x1 - - - BODLEVEL - Brown-out Detector trigger level - [2:0] - - true - - - - 4V3 - Brown-out detection at VCC=4.3 V - 4 - - - 2V7 - Brown-out detection at VCC=2.7 V - 5 - - - 1V8 - Brown-out detection at VCC=1.8 V - 6 - - - DISABLED - Brown-out detection disabled - 7 - - - - - EESAVE - Preserve EEPROM through the Chip Erase cycle - [3:3] - - - WDTON - Watch-dog Timer always on - [4:4] - - - SPIEN - Serial program downloading (SPI) enabled - [5:5] - - - DWEN - Debug Wire enable - [6:6] - - - RSTDISBL - Reset Disabled (Enable PB3 as i/o pin) - [7:7] - - - - - LOW - <TBD> - 0x0 - - - SUT_CKSEL - Select Clock source - [5:0] - - true - - - - EXTCLK_6CK_14CK_0MS - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 0 - - - INTRCOSC_8MHZ_6CK_14CK_0MS - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 2 - - - WDOSC_128KHZ_6CK_14CK_0MS - WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 4 - - - EXTLOFXTAL_1KCK_14CK_0MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms - 6 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 8 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 9 - - - EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 10 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 11 - - - EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 12 - - - EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 13 - - - EXTXOSC_8MHZ_XX_258CK_14CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 14 - - - EXTXOSC_8MHZ_XX_1KCK_14CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 15 - - - EXTCLK_6CK_14CK_4MS1 - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - 16 - - - INTRCOSC_8MHZ_6CK_14CK_4MS - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms - 18 - - - WDOSC_128KHZ_6CK_14CK_4MS - WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms - 20 - - - EXTLOFXTAL_1KCK_14CK_4MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms - 22 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 24 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 25 - - - EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 26 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 27 - - - EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 28 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 29 - - - EXTXOSC_8MHZ_XX_258CK_14CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 30 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 31 - - - EXTCLK_6CK_14CK_65MS - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms - 32 - - - INTRCOSC_8MHZ_6CK_14CK_64MS_DEFAULT - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms; default value - 34 - - - WDOSC_128KHZ_6CK_14CK_64MS - WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms - 36 - - - EXTLOFXTAL_32KCK_14CK_64MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 64 ms - 38 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 40 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 41 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 42 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 43 - - - EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 44 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 45 - - - EXTXOSC_8MHZ_XX_1KCK_14CK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 46 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 47 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 56 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 57 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 58 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 59 - - - EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 60 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 61 - - - EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 62 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 63 - - - - - CKOUT - Clock output on PORTB2 - [6:6] - - - CKDIV8 - Divide clock by 8 internally - [7:7] - - - - - - - LOCKBIT - Lockbits - 0x0 - - - LOCKBIT - <TBD> - 0x0 - - - LB - Memory Lock - [1:0] - - true - - - - PROG_VER_DISABLED - Further programming and verification disabled - 0 - - - PROG_DISABLED - Further programming disabled - 2 - - - NO_LOCK - No memory lock features enabled - 3 - - - - - - - - - PORTA - I/O Port - 0x39 - - - DDRA - Port A Data Direction Register - 0x1 - - - 0 - 255 - - - - - PINA - Port A Input Pins - 0x0 - read-write - - - 0 - 255 - - - - - PORTA - Port A Data Register - 0x2 - - - 0 - 255 - - - - - - - PORTB - I/O Port - 0x36 - - - DDRB - Data Direction Register, Port B - 0x1 - - - 0 - 255 - - - - - PINB - Input Pins, Port B - 0x0 - read-write - - - 0 - 255 - - - - - PORTB - Data Register, Port B - 0x2 - - - 0 - 255 - - - - - - - TC0 - Timer/Counter0, 8-bit, PWM - 0x43 - - - GTCCR - General Timer/Counter Control Register - 0x0 - - - PSR10 - Prescaler Reset Timer/CounterN - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - OCR0A - Output Compare Register A - 0x13 - - - 0 - 255 - - - - - OCR0B - Output Compare Register B - 0x19 - - - 0 - 255 - - - - - TCCR0A - Timer/Counter Control Register A - 0xD - - - WGM0 - Waveform Generation Mode bits - [1:0] - - true - WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *BOTTOM*, Flag: *TOP*3 - - - COM0B - Compare Output B Mode - [5:4] - - true - COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM0A - Compare Output A Mode - [7:6] - - true - - - - - - TCCR0B - Timer/Counter Control Register B - 0x10 - - - CS0 - Clock Select bits - [2:0] - - true - - CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM02 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) - [3:3] - - - FOC0B - Force Output Compare B - [6:6] - write-only - - FOC0A - Force Output Compare A - [7:7] - write-only - - - - TCNT0 - Timer/Counter0 - 0xF - - - 0 - 255 - - - - - TIFR0 - Timer/Counter0 Interrupt Flag Register - 0x15 - read-only - - - TOV0 - Timer/Counter0 Overflow Flag - [0:0] - - - OCF0A - Timer/Counter0 Output Compare Flag A - [1:1] - - - OCF0B - Timer/Counter0 Output Compare Flag B - [2:2] - - - - - TIMSK0 - Timer/Counter Interrupt Mask Register - 0x16 - - - TOIE0 - Timer/Counter0 Overflow Interrupt Enable - [0:0] - - - OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable - [2:2] - - - - - - - TC1 - Timer/Counter, 16-bit - 0x2B - - - ICR1 - Timer/Counter1 Input Capture Register Bytes - 0x19 - 16 - - - 0 - 65535 - - - - - OCR1A - Timer/Counter1 Output Compare Register A Bytes - 0x1F - 16 - - - 0 - 65535 - - - - - OCR1B - Timer/Counter1 Output Compare Register B Bytes - 0x1D - 16 - - - 0 - 65535 - - - - - TCCR1A - Timer/Counter1 Control Register A - 0x24 - - - WGM1 - Pulse Width Modulator Select Bits - [1:0] - - - 0 - 3 - - - - - COM1B - Compare Output Mode 1B, bits - [5:4] - - true - COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM1A - Compare Output Mode 1A, bits - [7:6] - - true - - - - - - TCCR1B - Timer/Counter1 Control Register B - 0x23 - - - CS1 - Clock Select1 bits - [2:0] - - true - CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM1 - Waveform Generation Mode Bits - [4:3] - - - 0 - 3 - - - - - ICES1 - Input Capture 1 Edge Select - [6:6] - - - ICNC1 - Input Capture 1 Noise Canceler - [7:7] - - - - - TCCR1C - Timer/Counter1 Control Register C - 0x17 - - - FOC1B - Force Output Compare for Channel B - [6:6] - write-only - - FOC1A - Force Output Compare for Channel A - [7:7] - write-only - - - - TCNT1 - Timer/Counter1 Bytes - 0x21 - 16 - - - 0 - 65535 - - - - - TIFR1 - Timer/Counter Interrupt Flag register - 0x0 - read-write - - - TOV1 - Timer/Counter1 Overflow Flag - [0:0] - - - OCF1A - Timer/Counter1 Output Compare A Match Flag - [1:1] - - - OCF1B - Timer/Counter1 Output Compare B Match Flag - [2:2] - - - ICF1 - Timer/Counter1 Input Capture Flag - [5:5] - - - - - TIMSK1 - Timer/Counter1 Interrupt Mask Register - 0x1 - - - TOIE1 - Timer/Counter1 Overflow Interrupt Enable - [0:0] - - - OCIE1A - Timer/Counter1 Output Compare A Match Interrupt Enable - [1:1] - - - OCIE1B - Timer/Counter1 Output Compare B Match Interrupt Enable - [2:2] - - - ICIE1 - Timer/Counter1 Input Capture Interrupt Enable - [5:5] - - - - - - - USI - Universal Serial Interface - 0x2D - - - USIBR - USI Buffer Register - 0x3 - read-only - - - 0 - 255 - - - - - USICR - USI Control Register - 0x0 - - - USITC - Toggle Clock Port Pin - [0:0] - write-only - - USICLK - Clock Strobe - [1:1] - write-only - - USICS - USI Clock Source Select Bits - [3:2] - - - 0 - 3 - - - USICSread-writeNO_CLOCKNo Clock/Software clock strobe0TC0Timer/Counter0 Compare Match1EXT_POSExternal, positive edge2EXT_NEGExternal, negative edge3 - - - USIWM - USI Wire Mode Bits - [5:4] - - true - - USIWMread-writeDISABLEDAll detectors disabled. Port pins operates as normal.0THREE_WIREThree-wire mode. Uses DO, DI, and USCK pins.1TWO_WIRE_SLAVETwo-wire mode (Slave). Uses SDA (DI) and SCL (USCK) pins.2TWO_WIRE_MASTERTwo-wire mode (Master). Uses SDA and SCL pins.3 - - - USIOIE - Counter Overflow Interrupt Enable - [6:6] - - - USISIE - Start Condition Interrupt Enable - [7:7] - - - - - USIDR - USI Data Register - 0x2 - - - 0 - 255 - - - - - USISR - USI Status Register - 0x1 - read-write - - - USICNT - USI Counter Value Bits - [3:0] - - - 0 - 15 - - - - - USIDC - Data Output Collision - [4:4] - read-only - - USIPF - Stop Condition Flag - [5:5] - - - USIOIF - Counter Overflow Interrupt Flag - [6:6] - - - USISIF - Start Condition Interrupt Flag - [7:7] - - - - - - - WDT - Watchdog Timer - 0x41 - - - WDTCSR - Watchdog Timer Control Register - 0x0 - read-write - - - WDE - Watch Dog Enable - [3:3] - - - WDCE - Watchdog Change Enable - [4:4] - - - WDIE - Watchdog Timeout Interrupt Enable - [6:6] - - - WDIF - Watchdog Timeout Interrupt Flag - [7:7] - - WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 - - WDPHWatchdog Timer Prescaler - High Bit[5:5] - - - - - - \ No newline at end of file diff --git a/misc/svd/attiny841.svd b/misc/svd/attiny841.svd deleted file mode 100644 index ff35c22..0000000 --- a/misc/svd/attiny841.svd +++ /dev/null @@ -1,3309 +0,0 @@ - - Atmel - ATtiny841 - 8 - 8 - read-write - 0 - 0xff - - - AC - Analog Comparator - 0x2A - - - ACSR0A - Analog Comparator 0 Control And Status Register A - 0x0 - read-write - - ACIS0 - Analog Comparator Interrupt Mode Select - [1:0] - - true - - ACIS0read-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 - - - ACIC0 - Analog Comparator 0 Input Capture Enable - [2:2] - - - ACIE0 - Analog Comparator 0 Interrupt Enable - [3:3] - - - ACI0 - Analog Comparator 0 Interrupt Flag - [4:4] - - - ACO0 - Analog Comparator 0 Output - [5:5] - - - ACPMUX2 - Analog Comparator 0 Positive Input Multiplexer Bit 2 - [6:6] - - - ACD0 - Analog Comparator 0 Disable - [7:7] - - - - - ACSR0B - Analog Comparator 0 Control And Status Register B - 0x1 - - - ACPMUX - Analog Comparator 0 Positive Input Multiplexer Bits 1:0 - [1:0] - - - 0 - 3 - - - - - ACNMUX - Analog Comparator 0 Negative Input Multiplexer - [3:2] - - - 0 - 3 - - - - - ACOE0 - Analog Comparator 0 Output Pin Enable - [4:4] - - - HLEV0 - Analog Comparator 0 Hysteresis Level - [6:6] - - - HSEL0 - Analog Comparator 0 Hysteresis Select - [7:7] - - - - - ACSR1A - Analog Comparator 1 Control And Status Register A - 0x2 - read-write - - ACIS1 - Analog Comparator Interrupt Mode Select - [1:0] - - true - - ACIS1read-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 - - - ACIC1 - Analog Comparator 1 Input Capture Enable - [2:2] - - - ACIE1 - Analog Comparator 1 Interrupt Enable - [3:3] - - - ACI1 - Analog Comparator 1 Interrupt Flag - [4:4] - - - ACO1 - Analog Comparator 1 Output - [5:5] - - - ACBG1 - Analog Comparator 1 Bandgap Select - [6:6] - - - ACD1 - Analog Comparator 1 Disable - [7:7] - - - - - ACSR1B - Analog Comparator 1 Control And Status Register B - 0x3 - - - ACME1 - Analog Comparator 1 Multiplexer Enable - [2:2] - - - ACOE1 - Analog Comparator 1 Output Pin Enable - [4:4] - - - HLEV1 - Analog Comparator 1 Hysteresis Level - [6:6] - - - HSEL1 - Analog Comparator 1 Hysteresis Select - [7:7] - - - - - - - ADC - Analog-to-Digital Converter - 0x24 - - - ADC - ADC Data Register Bytes - 0x2 - 16 - - - 0 - 65535 - - - - - ADCSRA - The ADC Control and Status register - 0x1 - read-write - - - ADPS - ADC Prescaler Select Bits - [2:0] - - true - - ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 - - - ADIE - ADC Interrupt Enable - [3:3] - - - ADIF - ADC Interrupt Flag - [4:4] - - - ADATE - ADC Auto Trigger Enable - [5:5] - - - ADSC - ADC Start Conversion - [6:6] - - - ADEN - ADC Enable - [7:7] - - - - - ADCSRB - ADC Control and Status Register B - 0x0 - - - ADTS - ADC Auto Trigger Sources - [2:0] - - true - - - - VAL_0x00 - Free Running mode - 0 - - - VAL_0x01 - Analog Comparator 0 - 1 - - - VAL_0x02 - External Interrupt Request 0 - 2 - - - VAL_0x03 - Timer/Counter0 Compare Match A - 3 - - - VAL_0x04 - Timer/Counter0 Overflow - 4 - - - VAL_0x05 - Timer/Counter1 Compare Match A - 5 - - - VAL_0x06 - Timer/Counter1 Overflow - 6 - - - VAL_0x07 - Timer/Counter1 Capture Event - 7 - - - - - ADLAR - <TBD> - [3:3] - - - - - ADMUXA - The ADC multiplexer Selection Register A - 0x5 - - - MUX - Analog Channel and Gain Selection Bits - [5:0] - - - 0 - 63 - - - - - - - ADMUXB - The ADC multiplexer Selection Register B - 0x4 - - - GSEL - Gain Selection Bits - [1:0] - - - 0 - 3 - - - - - REFS - Reference Selection Bits - [7:5] - - - 0 - 7 - - - REFSread-writeVCCVcc0INTERNAL_1Internal 1.1V Voltage Reference with AREF disconnected1INTERNAL_2Internal 2.2V Voltage Reference with AREF disconnected2INTERNAL_4Internal 4.096V Voltage Reference with AREF disconnected3AREFAREF with internal reference off4AREF_INTERNAL_1Internal 1.1V Voltage Reference with external capacitor at AREF pin5AREF_INTERNAL_2Internal 2.2V Voltage Reference with external capacitor at AREF pin6AREF_INTERNAL_4Internal 4.096V Voltage Reference with external capacitor at AREF pin7 - - - - - DIDR0 - Digital Input Disable Register 0 - 0x3C - - - ADC0D - ADC0/AREF Digital input Disable - [0:0] - - - ADC1D - ADC1/AIN00 Digital input Disable - [1:1] - - - ADC2D - ADC2/AIN01 Digital input Disable - [2:2] - - - ADC3D - ADC3/AIN10 Digital Input Disable - [3:3] - - - ADC4D - ADC4/AIN11 Digital input Disable - [4:4] - - - ADC5D - ADC5 Digital input Disable - [5:5] - - - ADC6D - ADC6 Digital input Disable - [6:6] - - - ADC7D - ADC7 Digital input Disable - [7:7] - - - - - DIDR1 - Digital Input Disable Register 1 - 0x3D - - - ADC11D - ADC11 Digital input Disable - [0:0] - - - ADC10D - ADC10 Digital input Disable - [1:1] - - - ADC8D - ADC8 Digital input Disable - [2:2] - - - ADC9D - ADC9 Digital Input Disable - [3:3] - - - - - - - CPU - CPU Registers - 0x33 - - RESET - External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset - 0 - - - INT0 - External Interrupt Request 0 - 1 - - - PCINT0 - Pin Change Interrupt Request 0 - 2 - - - PCINT1 - Pin Change Interrupt Request 1 - 3 - - - WDT - Watchdog Time-out Interrupt - 4 - - - TIMER1_CAPT - Timer/Counter1 Capture Event - 5 - - - TIMER1_COMPA - Timer/Counter1 Compare Match A - 6 - - - TIMER1_COMPB - Timer/Counter1 Compare Match B - 7 - - - TIMER1_OVF - Timer/Counter1 Overflow - 8 - - - TIMER0_COMPA - TimerCounter0 Compare Match A - 9 - - - TIMER0_COMPB - TimerCounter0 Compare Match B - 10 - - - TIMER0_OVF - Timer/Couner0 Overflow - 11 - - - ANA_COMP0 - Analog Comparator 0 - 12 - - - ADC - ADC Conversion Complete - 13 - - - EE_RDY - EEPROM Ready - 14 - - - ANA_COMP1 - Analog Comparator 1 - 15 - - - TIMER2_CAPT - Timer/Counter2 Capture Event - 16 - - - TIMER2_COMPA - Timer/Counter2 Compare Match A - 17 - - - TIMER2_COMPB - Timer/Counter2 Compare Match B - 18 - - - TIMER2_OVF - Timer/Counter2 Overflow - 19 - - - SPI - Serial Peripheral Interface - 20 - - - USART0_START - USART0, Start - 21 - - - USART0_RX - USART0, Rx Complete - 22 - - - USART0_UDRE - USART0 Data Register Empty - 23 - - - USART0_TX - USART0, Tx Complete - 24 - - - USART1_START - USART1, Start - 25 - - - USART1_RX - USART1, Rx Complete - 26 - - - USART1_UDRE - USART1 Data Register Empty - 27 - - - USART1_TX - USART1, Tx Complete - 28 - - - TWI_SLAVE - Two-wire Serial Interface - 29 - - - - CCP - Configuration Change Protection - 0x3E - - - 0 - 255 - - - - - CLKCR - Clock Control Register - 0x3F - - - CKSEL - Clock Select Bits - [3:0] - - - 0 - 15 - - - - - SUT - Start-up Time - [4:4] - - - CKOUTC - Clock Output (Copy). Active low. - [5:5] - - - CSTR - Clock Switch Trigger - [6:6] - - - OSCRDY - Oscillator Ready - [7:7] - - - - - CLKPR - Clock Prescale Register - 0x40 - - - CLKPS - Clock Prescaler Select Bits - [3:0] - - true - - - - VAL_0x00 - 1 - 0 - - - VAL_0x01 - 2 - 1 - - - VAL_0x02 - 4 - 2 - - - VAL_0x03 - 8 - 3 - - - VAL_0x04 - 16 - 4 - - - VAL_0x05 - 32 - 5 - - - VAL_0x06 - 64 - 6 - - - VAL_0x07 - 128 - 7 - - - VAL_0x08 - 256 - 8 - - - - - - - GPIOR0 - General Purpose I/O Register 0 - 0x0 - - - 0 - 255 - - - - - GPIOR1 - General Purpose I/O Register 1 - 0x1 - - - 0 - 255 - - - - - GPIOR2 - General Purpose I/O Register 2 - 0x2 - - - 0 - 255 - - - - - MCUCR - MCU Control Register - 0x22 - - - ISC0 - Interrupt Sense Control 0 bits - [1:0] - - - 0 - 3 - - - - - SM - Sleep Mode Select Bits - [4:3] - - true - - - - IDLE - Idle - 0 - - - ADC - ADC Noise Reduction (If Available) - 1 - - - PDOWN - Power Down - 2 - - - STDBY - Standby - 3 - - - - - SE - Sleep Enable - [5:5] - - - - - MCUSR - MCU Status Register - 0x21 - - - PORF - Power-on reset flag - [0:0] - - - EXTRF - External Reset Flag - [1:1] - - - BORF - Brown-out Reset Flag - [2:2] - - - WDRF - Watchdog Reset Flag - [3:3] - - - - - OSCCAL0 - Oscillator Calibration Register 8MHz - 0x41 - - - 0 - 255 - - - - - OSCCAL1 - Oscillator Calibration Register 32kHz - 0x44 - - - 0 - 255 - - - - - OSCTCAL0A - Oscillator Temperature Calibration Register A - 0x42 - - - 0 - 255 - - - - - OSCTCAL0B - Oscillator Temperature Calibration Register B - 0x43 - - - 0 - 255 - - - - - PRR - Power Reduction Register - 0x3D - - - PRADC - Power Reduction ADC - [0:0] - - - PRTIM0 - Power Reduction Timer/Counter0 - [1:1] - - - PRTIM1 - Power Reduction Timer/Counter1 - [2:2] - - - PRTIM2 - Power Reduction Timer/Counter2 - [3:3] - - - PRSPI - Power Reduction SPI - [4:4] - - - PRUSART0 - Power Reduction USART0 - [5:5] - - - PRUSART1 - Power Reduction USART1 - [6:6] - - - PRTWI - Power Reduction TWI - [7:7] - - - - - SPMCSR - Store Program Memory Control and Status Register - 0x24 - read-only - - - SPMEN - Store program Memory Enable - [0:0] - - - PGERS - Page Erase - [1:1] - - - PGWRT - Page Write - [2:2] - - - RFLB - Read Fuse and Lock Bits - [3:3] - - - CTPB - Clear Temporary Page Buffer - [4:4] - - - RSIG - Read Device Signature Imprint Table - [5:5] - - - - - - - EEPROM - EEPROM - 0x3C - - - EEAR - EEPROM Address Register Bytes - 0x2 - 16 - - - 0 - 65535 - - - - - EECR - EEPROM Control Register - 0x0 - - - EERE - EEPROM Read Enable - [0:0] - - - EEPE - EEPROM Write Enable - [1:1] - - - EEMPE - EEPROM Master Write Enable - [2:2] - - - EERIE - EEPROM Ready Interrupt Enable - [3:3] - - - EEPM - EEPROM Programming Mode Bits - [5:4] - - true - - - - VAL_0x00 - Erase and Write in one operation - 0 - - - VAL_0x01 - Erase Only - 1 - - - VAL_0x02 - Write Only - 2 - - - - - - - EEDR - EEPROM Data Register - 0x1 - - - 0 - 255 - - - - - - - EXINT - External Interrupts - 0x32 - - - GIFR - General Interrupt Flag register - 0x28 - read-only - - - PCIF - Pin Change Interrupt Flags - [5:4] - - - 0 - 3 - - - - - INTF0 - External Interrupt Flag 0 - [6:6] - - - - - GIMSK - General Interrupt Mask Register - 0x29 - - - PCIE - Pin Change Interrupt Enables - [5:4] - - - 0 - 3 - - - - - INT0 - External Interrupt Request 0 Enable - [6:6] - - - - - MCUCR - MCU Control Register - 0x23 - - - ISC00 - Interrupt Sense Control 0 Bit 0 - [0:0] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Reserved - 1 - - - - - ISC01 - Interrupt Sense Control 0 Bit 1 - [1:1] - - - - - PCMSK0 - Pin Change Enable Mask 0 - 0x0 - - - PCINT0 - Pin Change Enable Mask 0 Bit 0 - [0:0] - - - PCINT1 - Pin Change Enable Mask 0 Bit 1 - [1:1] - - - PCINT2 - Pin Change Enable Mask 0 Bit 2 - [2:2] - - - PCINT3 - Pin Change Enable Mask 0 Bit 3 - [3:3] - - - PCINT4 - Pin Change Enable Mask 0 Bit 4 - [4:4] - - - PCINT5 - Pin Change Enable Mask 0 Bit 5 - [5:5] - - - PCINT6 - Pin Change Enable Mask 0 Bit 6 - [6:6] - - - PCINT7 - Pin Change Enable Mask 0 Bit 7 - [7:7] - - - - - PCMSK1 - Pin Change Enable Mask 1 - 0xE - - - PCINT8 - Pin Change Enable Mask 1 Bit 0 - [0:0] - - - PCINT9 - Pin Change Enable Mask 1 Bit 1 - [1:1] - - - PCINT10 - Pin Change Enable Mask 1 Bit 2 - [2:2] - - - PCINT11 - Pin Change Enable Mask 1 Bit 3 - [3:3] - - - - - - - FUSE - Fuses - 0x0 - - - EXTENDED - <TBD> - 0x2 - - - SELFPRGEN - Self Programming enable - [0:0] - - - BODACT - BOD mode of operation when the device is active or idle - [2:1] - - true - - - - BOD_SAMPLED - Sampled - 1 - - - BOD_ENABLED - Enabled - 2 - - - BOD_DISABLED - Disabled - 3 - - - - - BODPD - BOD mode of operation when the device is in sleep mode - [4:3] - - true - - - - BOD_SAMPLED - Sampled - 1 - - - BOD_ENABLED - Enabled - 2 - - - BOD_DISABLED - Disabled - 3 - - - - - ULPOSCSEL - Frequency selection for internal ULP oscillator. The selection only affects system clock, watchdog and reset timeout always use 32 kHz clock. - [7:5] - - true - - - - ULPOSC_512KHZ - 512 kHz - 3 - - - ULPOSC_256KHZ - 256 kHz - 4 - - - ULPOSC_128KHZ - 128 kHz - 5 - - - ULPOSC_64KHZ - 64 kHz - 6 - - - ULPOSC_32KHZ - 32 kHz - 7 - - - - - - - HIGH - <TBD> - 0x1 - - - BODLEVEL - Brown-out Detector trigger level - [2:0] - - true - - - - 4V3 - Brown-out detection at VCC=4.3 V - 4 - - - 2V7 - Brown-out detection at VCC=2.7 V - 5 - - - 1V8 - Brown-out detection at VCC=1.8 V - 6 - - - - - EESAVE - Preserve EEPROM through the Chip Erase cycle - [3:3] - - - WDTON - Watch-dog Timer always on - [4:4] - - - SPIEN - Serial program downloading (SPI) enabled - [5:5] - - - DWEN - Debug Wire enable - [6:6] - - - RSTDISBL - Reset Disabled (Enable PC2 as i/o pin) - [7:7] - - - - - LOW - <TBD> - 0x0 - - - SUT_CKSEL - Select Clock Source - [4:0] - - true - - - - EXTCLK_6CK_16CK_16MS - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/16 CK + 16 ms - 0 - - - INTRCOSC_8MHZ_6CK_16CK_16MS - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/16 CK + 16 ms - 2 - - - INTULPOSC_32KHZ_6CK_16CK_16MS - Int. ULP Osc.; Start-up time PWRDWN/RESET: 6 CK/16 CK + 16 ms - 4 - - - EXTLOFXTAL_1KCK_16CK_16MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/16 CK + 16 ms - 6 - - - EXTCRES_0MHZ4_0MHZ9_258CK_16CK_16MS - Ext. Ceramic Res. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/16 CK + 16 ms - 8 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_16CK_16MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16 K CK/16 CK + 16 ms - 9 - - - EXTCRES_0MHZ9_3MHZ_258CK_16CK_16MS - Ext. Ceramic Res. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/16 CK + 16 ms - 10 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_16CK_16MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16 K CK/16 CK + 16 ms - 11 - - - EXTCRES_3MHZ_8MHZ_258CK_16CK_16MS - Ext. Ceramic Res. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/16 CK + 16 ms - 12 - - - EXTXOSC_3MHZ_8MHZ_16KCK_16CK_16MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16 K CK/16 CK + 16 ms - 13 - - - EXTCRES_8MHZ_XX_258CK_16CK_16MS - Ext. Ceramic Res. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/16 CK + 16 ms - 14 - - - EXTXOSC_8MHZ_XX_16KCK_16CK_16MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16 K CK/16 CK + 16 ms - 15 - - - EXTLOFXTAL_32KCK_14CK_16MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/16 CK + 16 ms - 22 - - - EXTCRES_0MHZ4_0MHZ9_1KCK_16CK_16MS - Ext. Ceramic Res. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK/16 CK + 16 ms - 24 - - - EXTCRES_0MHZ9_3MHZ_1KCK_16CK_16MS - Ext. Ceramic Res. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK/16 CK + 16 ms - 26 - - - EXTCRES_3MHZ_8MHZ_1KCK_16CK_16MS - Ext. Ceramic Res. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK/16 CK + 16 ms - 28 - - - EXTCRES_8MHZ_XX_1KCK_16CK_16MS - Ext. Ceramic Res. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK/16 CK + 16 ms - 30 - - - - - CKOUT - Clock output on PORTC2 - [6:6] - - - CKDIV8 - Divide clock by 8 internally - [7:7] - - - - - - - LOCKBIT - Lockbits - 0x0 - - - LOCKBIT - <TBD> - 0x0 - - - LB - Memory Lock - [1:0] - - true - - - - PROG_VER_DISABLED - Further programming and verification disabled - 0 - - - PROG_DISABLED - Further programming disabled - 2 - - - NO_LOCK - No memory lock features enabled - 3 - - - - - - - - - PORTA - I/O Port - 0x39 - - - DDRA - Data Direction Register, Port A - 0x1 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - PHDE - Port High Drive Enable Register - 0x31 - - - PHDEA - PortA High Drive Enable - [1:0] - - - 0 - 3 - - - - - - - PINA - Port A Input Pins - 0x0 - read-write - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - PORTA - Port A Data Register - 0x2 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - PORTCR - Port Control Register - 0x2B - - - BBMA - Break-Before-Make Mode Enable - [0:0] - - - - - PUEA - Pull-up Enable Control Register - 0x2A - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - - - PORTB - I/O Port - 0x36 - - - DDRB - Data Direction Register, Port B - 0x1 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - - - PINB - Port B Data register - 0x0 - read-write - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - - - PORTB - Input Pins, Port B - 0x2 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - - - PORTCR - Port Control Register - 0x2E - - - BBMB - Break-Before-Make Mode Enable - [1:1] - - - - - PUEB - Pull-up Enable Control Register - 0x2C - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - - - - - SPI - Serial Peripheral Interface - 0x65 - - - REMAP - Remap Port Pins - 0x0 - - - SPIMAP - SPI Pin Mapping - [1:1] - - - - - SPCR - SPI Control Register - 0x4D - - - SPR - SPI Clock Rate Selects - [1:0] - - true - - SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 - - - CPHA - Clock Phase - [2:2] - - - CPOL - Clock polarity - [3:3] - - - MSTR - Master/Slave Select - [4:4] - - - DORD - Data Order - [5:5] - - - SPE - SPI Enable - [6:6] - - - SPIE - SPI Interrupt Enable - [7:7] - - - - - SPDR - SPI Data Register - 0x4B - - - 0 - 255 - - - - - SPSR - SPI Status Register - 0x4C - read-write - - SPI2X - Double SPI Speed Bit - [0:0] - read-write - - WCOL - Write Collision Flag - [6:6] - read-only - - SPIF - SPI Interrupt Flag - [7:7] - read-only - - - - - - TC0 - Timer/Counter0, 8-bit, PWM - 0x43 - - - GTCCR - General Timer/Counter Control Register - 0x0 - - - PSR - Prescaler Reset Timer/CounterN - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - OCR0A - Output Compare Register A - 0x13 - - - 0 - 255 - - - - - OCR0B - Output Compare Register B - 0x19 - - - 0 - 255 - - - - - TCCR0A - Timer/Counter Control Register A - 0xD - - - WGM0 - Waveform Generation Mode bits - [1:0] - - true - WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *BOTTOM*, Flag: *TOP*3 - - - COM0B - Compare Output B Mode - [5:4] - - true - COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM0A - Compare Output A Mode - [7:6] - - true - - - - - - TCCR0B - Timer/Counter Control Register B - 0x10 - - - CS0 - Clock Select bits - [2:0] - - true - - CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM02 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) - [3:3] - - - FOC0B - Force Output Compare B - [6:6] - write-only - - FOC0A - Force Output Compare A - [7:7] - write-only - - - - TCNT0 - Timer/Counter0 - 0xF - - - 0 - 255 - - - - - TIFR0 - Timer/Counter0 Interrupt Flag Register - 0x15 - read-only - - - TOV0 - Timer/Counter0 Overflow Flag - [0:0] - - - OCF0A - Timer/Counter0 Output Compare Flag A - [1:1] - - - OCF0B - Timer/Counter0 Output Compare Flag B - [2:2] - - - - - TIMSK0 - Timer/Counter Interrupt Mask Register - 0x16 - - - TOIE0 - Timer/Counter0 Overflow Interrupt Enable - [0:0] - - - OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable - [2:2] - - - - - - - TC1 - Timer/Counter1, 16-bit - 0x2E - - - GTCCR - General Timer/Counter Control Register - 0x15 - - - PSR - Prescaler Reset Timer/CounterN - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - ICR1 - Timer/Counter1 Input Capture Register Bytes - 0x16 - 16 - - - 0 - 65535 - - - - - OCR1A - Timer/Counter1 Output Compare Register A Bytes - 0x1C - 16 - - - 0 - 65535 - - - - - OCR1B - Timer/Counter1 Output Compare Register B Bytes - 0x1A - 16 - - - 0 - 65535 - - - - - TCCR1A - Timer/Counter1 Control Register A - 0x21 - - - WGM1 - Pulse Width Modulator Select Bits - [1:0] - - - 0 - 3 - - - - - COM1B - Compare Output Mode 1B, bits - [5:4] - - true - COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM1A - Compare Output Mode 1A, bits - [7:6] - - true - - - - - - TCCR1B - Timer/Counter1 Control Register B - 0x20 - - - CS1 - Clock Select bits - [2:0] - - true - CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM1 - Waveform Generation Mode Bits - [4:3] - - - 0 - 3 - - - - - ICES1 - Input Capture 1 Edge Select - [6:6] - - - ICNC1 - Input Capture 1 Noise Canceler - [7:7] - - - - - TCCR1C - Timer/Counter1 Control Register C - 0x14 - - - FOC1B - Force Output Compare for Channel B - [6:6] - write-only - - FOC1A - Force Output Compare for Channel A - [7:7] - write-only - - - - TCNT1 - Timer/Counter1 Bytes - 0x1E - 16 - - - 0 - 65535 - - - - - TIFR1 - Timer/Counter Interrupt Flag register - 0x0 - read-write - - - TOV1 - Timer/Counter1 Overflow Flag - [0:0] - - - OCF1A - Timer/Counter1 Output Compare A Match Flag - [1:1] - - - OCF1B - Timer/Counter1 Output Compare B Match Flag - [2:2] - - - ICF1 - Timer/Counter1 Input Capture Flag - [5:5] - - - - - TIMSK1 - Timer/Counter1 Interrupt Mask Register - 0x1 - - - TOIE1 - Timer/Counter1 Overflow Interrupt Enable - [0:0] - - - OCIE1A - Timer/Counter1 Output Compare A Match Interrupt Enable - [1:1] - - - OCIE1B - Timer/Counter1 Output Compare B Match Interrupt Enable - [2:2] - - - ICIE1 - Timer/Counter1 Input Capture Interrupt Enable - [5:5] - - - - - - - TC2 - Timer/Counter2, 16-bit - 0x30 - - - GTCCR - General Timer/Counter Control Register - 0x13 - - - PSR - Prescaler Reset Timer/CounterN - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - ICR2 - Timer/Counter2 Input Capture Register Bytes - 0x90 - 16 - - - 0 - 65535 - - - - - OCR2A - Timer/Counter2 Output Compare Register A Bytes - 0x94 - 16 - - - 0 - 65535 - - - - - OCR2B - Timer/Counter2 Output Compare Register B Bytes - 0x92 - 16 - - - 0 - 65535 - - - - - TCCR2A - Timer/Counter2 Control Register A - 0x9A - - - WGM2 - Pulse Width Modulator Select Bits - [1:0] - - - 0 - 3 - - - - - COM2B - Compare Output Mode 2B, bits - [5:4] - - true - COM2Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM2A - Compare Output Mode 2A, bits - [7:6] - - true - - - - - - TCCR2B - Timer/Counter2 Control Register B - 0x99 - - - CS2 - Clock Select bits - [2:0] - - true - CS2read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM2 - Waveform Generation Mode Bits - [4:3] - - - 0 - 3 - - - - - ICES2 - Input Capture 2 Edge Select - [6:6] - - - ICNC2 - Input Capture 2 Noise Canceler - [7:7] - - - - - TCCR2C - Timer/Counter2 Control Register C - 0x98 - - - FOC2B - Force Output Compare for Channel B - [6:6] - write-only - - FOC2A - Force Output Compare for Channel A - [7:7] - write-only - - - - TCNT2 - Timer/Counter2 Bytes - 0x96 - 16 - - - 0 - 65535 - - - - - TIFR2 - Timer/Counter Interrupt Flag register - 0x0 - read-write - - - TOV2 - Timer/Counter2 Overflow Flag - [0:0] - - - OCF2A - Timer/Counter2 Output Compare A Match Flag - [1:1] - - - OCF2B - Timer/Counter2 Output Compare B Match Flag - [2:2] - - - ICF2 - Timer/Counter2 Input Capture Flag - [5:5] - - - - - TIMSK2 - Timer/Counter2 Interrupt Mask Register - 0x1 - - - TOIE2 - Timer/Counter2 Overflow Interrupt Enable - [0:0] - - - OCIE2A - Timer/Counter2 Output Compare A Match Interrupt Enable - [1:1] - - - OCIE2B - Timer/Counter2 Output Compare B Match Interrupt Enable - [2:2] - - - ICIE2 - Timer/Counter2 Input Capture Interrupt Enable - [5:5] - - - - - - - TOCPM - Timer/Counter Output Compare Pin - 0x66 - - - TOCPMCOE - Timer Output Compare Pin Mux Channel Output Enable - 0x0 - - - TOCC0OE - Timer Output Compare Channel 0 Output Enable - [0:0] - - - TOCC1OE - Timer Output Compare Channel 1 Output Enable - [1:1] - - - TOCC2OE - Timer Output Compare Channel 2 Output Enable - [2:2] - - - TOCC3OE - Timer Output Compare Channel 3 Output Enable - [3:3] - - - TOCC4OE - Timer Output Compare Channel 4 Output Enable - [4:4] - - - TOCC5OE - Timer Output Compare Channel 5 Output Enable - [5:5] - - - TOCC6OE - Timer Output Compare Channel 6 Output Enable - [6:6] - - - TOCC7OE - Timer Output Compare Channel 7 Output Enable - [7:7] - - - - - TOCPMSA0 - Timer Output Compare Pin Mux Selection 0 - 0x1 - - - TOCC0S - Timer Output Compare Channel 0 Selection Bits - [1:0] - - - 0 - 3 - - - - - TOCC1S - Timer Output Compare Channel 1 Selection Bits - [3:2] - - - 0 - 3 - - - - - TOCC2S - Timer Output Compare Channel 2 Selection Bits - [5:4] - - - 0 - 3 - - - - - TOCC3S - Timer Output Compare Channel 3 Selection Bits - [7:6] - - - 0 - 3 - - - - - - - TOCPMSA1 - Timer Output Compare Pin Mux Selection 1 - 0x2 - - - TOCC4S - Timer Output Compare Channel 4 Selection Bits - [1:0] - - - 0 - 3 - - - - - TOCC5S - Timer Output Compare Channel 5 Selection Bits - [3:2] - - - 0 - 3 - - - - - TOCC6S - Timer Output Compare Channel 6 Selection Bits - [5:4] - - - 0 - 3 - - - - - TOCC7S - Timer Output Compare Channel 7 Selection Bits - [7:6] - - - 0 - 3 - - - - - - - - - TWI - Two Wire Serial Interface - 0xA0 - - - TWSA - TWI Slave Address Register - 0x2 - read-only - - - 0 - 255 - - - - - TWSAM - TWI Slave Address Mask Register - 0x1 - - - TWAE - TWI Address Enable - [0:0] - - - TWSAM - TWI Address Mask Bits - [7:1] - - - 0 - 127 - - - - - - - TWSCRA - TWI Slave Control Register A - 0x5 - - - TWSME - TWI Smart Mode Enable - [0:0] - - - TWPME - TWI Promiscuous Mode Enable - [1:1] - - - TWSIE - TWI Stop Interrupt Enable - [2:2] - - - TWEN - Two-Wire Interface Enable - [3:3] - - - TWASIE - TWI Address/Stop Interrupt Enable - [4:4] - - - TWDIE - TWI Data Interrupt Enable - [5:5] - - - TWSHE - TWI SDA Hold Time Enable - [7:7] - - - - - TWSCRB - TWI Slave Control Register B - 0x4 - - - TWCMD - <TBD> - [1:0] - - - 0 - 3 - - - - - TWAA - TWI Acknowledge Action - [2:2] - TWAAread-writeACK_WRITESend ACK when TWCMD is written as 10 or 110ACK_READSend ACK when TWSD is read1NACK_WRITESend NACK when TWCMD is written as 10 or 112NACK_READSend NACK when TWSD is read3 - - - TWHNM - TWI High Noise Mode - [3:3] - - - - - TWSD - TWI Slave Data Register - 0x0 - read-only - - - TWSD - TWI slave data bit - [7:0] - - - 0 - 255 - - - - - - - TWSSRA - TWI Slave Status Register A - 0x3 - - - TWAS - TWI Address or Stop - [0:0] - - - TWDIR - TWI Read/Write Direction - [1:1] - - - TWBE - TWI Bus Error - [2:2] - - - TWC - TWI Collision - [3:3] - - - TWRA - TWI Receive Acknowledge - [4:4] - - - TWCH - TWI Clock Hold - [5:5] - - - TWASIF - TWI Address/Stop Interrupt Flag - [6:6] - - - TWDIF - TWI Data Interrupt Flag. - [7:7] - - - - - - - USART0 - USART - 0x65 - - - REMAP - Remap Port Pins - 0x0 - - - U0MAP - USART0 Pin Mapping - [0:0] - - - - - UBRR0 - USART Baud Rate Register Bytes - 0x1C - 16 - - - 0 - 65535 - - - - - UCSR0A - USART Control and Status Register A - 0x21 - read-write - - - MPCM0 - Multi-processor Communication Mode - [0:0] - - - U2X0 - Double the USART transmission speed - [1:1] - - - UPE0 - Parity Error - [2:2] - read-only - - DOR0 - Data overRun - [3:3] - read-only - - FE0 - Framing Error - [4:4] - read-only - - UDRE0 - USART Data Register Empty - [5:5] - read-only - - TXC0 - USART Transmit Complete - [6:6] - - - RXC0 - USART Receive Complete - [7:7] - read-only - - - - UCSR0B - USART Control and Status Register B - 0x20 - - - TXB80 - Transmit Data Bit 8 - [0:0] - - - RXB80 - Receive Data Bit 8 - [1:1] - read-only - - UCSZ02 - Character Size - [2:2] - - - TXEN0 - Transmitter Enable - [3:3] - - - RXEN0 - Receiver Enable - [4:4] - - - UDRIE0 - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE0 - TX Complete Interrupt Enable - [6:6] - - - RXCIE0 - RX Complete Interrupt Enable - [7:7] - - - - - UCSR0C - USART Control and Status Register C - 0x1F - - - UCPOL0 - Clock Polarity - [0:0] - UCPOL0read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 - - - UCSZ0 - Character Size - [2:1] - - - 0 - 3 - - - UCSZ0read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 - - - USBS0 - Stop Bit Select - [3:3] - - true - - USBS0read-writeSTOP11-bit0STOP22-bit1 - - - UPM0 - Parity Mode Bits - [5:4] - - true - - UPM0read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 - - - UMSEL0 - USART Mode Select - [7:6] - - true - - UMSEL0read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 - - - - - UCSR0D - USART Control and Status Register D - 0x1E - - - SFDE0 - USART RX Start Frame Detection Enable - [5:5] - - - RXS0 - USART RX Start Flag - [6:6] - - - RXSIE0 - USART RX Start Interrupt Enable - [7:7] - - - - - UDR0 - USART I/O Data Register - 0x1B - - - 0 - 255 - - - - - - - USART1 - USART - 0x90 - - - UBRR1 - USART Baud Rate Register Bytes - 0x1 - 16 - - - 0 - 65535 - - - - - UCSR1A - USART Control and Status Register A - 0x6 - read-write - - - MPCM1 - Multi-processor Communication Mode - [0:0] - - - U2X1 - Double the USART transmission speed - [1:1] - - - UPE1 - Parity Error - [2:2] - read-only - - DOR1 - Data overRun - [3:3] - read-only - - FE1 - Framing Error - [4:4] - read-only - - UDRE1 - USART Data Register Empty - [5:5] - read-only - - TXC1 - USART Transmit Complete - [6:6] - - - RXC1 - USART Receive Complete - [7:7] - read-only - - - - UCSR1B - USART Control and Status Register B - 0x5 - - - TXB81 - Transmit Data Bit 8 - [0:0] - - - RXB81 - Receive Data Bit 8 - [1:1] - read-only - - UCSZ12 - Character Size - [2:2] - - - TXEN1 - Transmitter Enable - [3:3] - - - RXEN1 - Receiver Enable - [4:4] - - - UDRIE1 - USART Data register Empty Interrupt Enable - [5:5] - - - TXCIE1 - TX Complete Interrupt Enable - [6:6] - - - RXCIE1 - RX Complete Interrupt Enable - [7:7] - - - - - UCSR1C - USART Control and Status Register C - 0x4 - - - UCPOL1 - Clock Polarity - [0:0] - UCPOL1read-writeRISING_EDGETransmit on Rising XCKn Edge, Receive on Falling XCKn Edge0FALLING_EDGETransmit on Falling XCKn Edge, Receive on Rising XCKn Edge1 - - - UCSZ1 - Character Size - [2:1] - - - 0 - 3 - - - UCSZ1read-writeCHR5Character Size: 5 bit0CHR6Character Size: 6 bit1CHR7Character Size: 7 bit2CHR8Character Size: 8 bit3 - - - USBS1 - Stop Bit Select - [3:3] - - true - - USBS1read-writeSTOP11-bit0STOP22-bit1 - - - UPM1 - Parity Mode Bits - [5:4] - - true - - UPM1read-writeDISABLEDDisabled0PARITY_EVENEnabled, Even Parity2PARITY_ODDEnabled, Odd Parity3 - - - UMSEL1 - USART Mode Select - [7:6] - - true - - UMSEL1read-writeUSART_ASYNCAsynchronous USART0USART_SYNCSynchronous USART1SPI_MASTERMaster SPI (MSPIM)3 - - - - - UCSR1D - USART Control and Status Register D - 0x3 - - - SFDE1 - USART RX Start Frame Detection Enable - [5:5] - - - RXS1 - USART RX Start Flag - [6:6] - - - RXSIE1 - USART RX Start Interrupt Enable - [7:7] - - - - - UDR1 - USART I/O Data Register - 0x0 - - - 0 - 255 - - - - - - - WDT - Watchdog Timer - 0x41 - - - WDTCSR - Watchdog Timer Control and Status Register - 0x0 - read-write - - WDE - Watch Dog Enable - [3:3] - - - WDIE - Watchdog Timer Interrupt Enable - [6:6] - - - WDIF - Watchdog Timer Interrupt Flag - [7:7] - - WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 - - WDPHWatchdog Timer Prescaler - High Bit[5:5] - - - - - - \ No newline at end of file diff --git a/misc/svd/attiny85.svd b/misc/svd/attiny85.svd deleted file mode 100644 index 5dadaaf..0000000 --- a/misc/svd/attiny85.svd +++ /dev/null @@ -1,1792 +0,0 @@ - - Atmel - ATtiny85 - 8 - 8 - read-write - 0 - 0xff - - - AC - Analog Comparator - 0x23 - - - ACSR - Analog Comparator Control And Status Register - 0x5 - read-write - - - ACIS - Analog Comparator Interrupt Mode Select - [1:0] - - true - - ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 - - - ACIE - Analog Comparator Interrupt Enable - [3:3] - - - ACI - Analog Comparator Interrupt Flag - [4:4] - - - ACO - Analog Compare Output - [5:5] - read-only - - ACBG - Analog Comparator Bandgap Select - [6:6] - - - ACD - Analog Comparator Disable - [7:7] - - - - - ADCSRB - ADC Control and Status Register B - 0x0 - - - ACME - Analog Comparator Multiplexer Enable - [6:6] - - - - - DIDR0 - Digital Input Disable Register 0 - 0x11 - - - AIN0D - AIN0 Digital Input Disable - [0:0] - - - AIN1D - AIN1 Digital Input Disable - [1:1] - - - - - - - ADC - Analog-to-Digital Converter - 0x23 - - - ADC - ADC Data Register Bytes - 0x1 - 16 - - - 0 - 65535 - - - - - ADCSRA - ADC Control and Status Register A - 0x3 - - - ADPS - ADC Prescaler Select Bits - [2:0] - - true - - ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 - - - ADIE - ADC Interrupt Enable - [3:3] - - - ADIF - ADC Interrupt Flag - [4:4] - - - ADATE - ADC Auto Trigger Enable - [5:5] - - - ADSC - ADC Start Conversion - [6:6] - - - ADEN - ADC Enable - [7:7] - - - - - ADCSRB - ADC Control and Status Register B - 0x0 - - - ADTS - ADC Auto Trigger Sources - [2:0] - - true - - ADTSread-writeFREEFree Running mode0ACAnalog Comparator1INT0External Interrupt Request 02TC0_CMATimer/Counter0 Compare Match A3TC0_OVFTimer/Counter0 Overflow4TC0_CMBTimer/Counter0 Compare Match B5PCIRPin Change Interrupt Request6 - - - IPR - Input Polarity Mode - [5:5] - - - BIN - Bipolar Input Mode - [7:7] - - - - - ADMUX - The ADC multiplexer Selection Register - 0x4 - - - MUX - Analog Channel and Gain Selection Bits - [3:0] - - true - MUXread-writeADC0Single-ended Input ADC00ADC1Single-ended Input ADC11ADC2Single-ended Input ADC22ADC3Single-ended Input ADC33ADC2_ADC2_1XDifferential Inputs Positive ADC2 Negative ADC2 1x Gain4ADC2_ADC2_20XDifferential Inputs Positive ADC2 Negative ADC2 20x Gain5ADC2_ADC3_1XDifferential Inputs Positive ADC2 Negative ADC3 1x Gain6ADC2_ADC3_20XDifferential Inputs Positive ADC2 Negative ADC3 20x Gain7ADC0_ADC0_1XDifferential Inputs Positive ADC0 Negative ADC0 1x Gain8ADC0_ADC0_20XDifferential Inputs Positive ADC0 Negative ADC0 20x Gain9ADC0_ADC1_1XDifferential Inputs Positive ADC0 Negative ADC1 1x Gain10ADC0_ADC1_20XDifferential Inputs Positive ADC0 Negative ADC1 20x Gain11ADC_VBGInternal Reference (VBG)12ADC_GND0V (GND)13TEMPSENSTemperature sensor15 - - - REFS2 - Reference Selection Bit 2 - [4:4] - - - ADLAR - Left Adjust Result - [5:5] - - - REFS - Reference Selection Bits - [7:6] - - true - REFSread-writeVCCVcc used as Voltage Reference, disconnected from Aref0AREFExternal Voltage Reference at AREF pin, Internal Voltage Reference turned off1INTERNALInternal Voltage Reference (1.1V when REFS2 is cleared, 2.56V when REFS2 is set) without external bypass2INTERNAL_BYPASSInternal 2.56V Voltage Reference with external bypass capacitor at AREF pin (REFS2 must be set)3 - - - - - DIDR0 - Digital Input Disable Register 0 - 0x11 - - - ADC1D - ADC1 Digital input Disable - [2:2] - - - ADC3D - ADC3 Digital input Disable - [3:3] - - - ADC2D - ADC2 Digital input Disable - [4:4] - - - ADC0D - ADC0 Digital input Disable - [5:5] - - - - - - - BOOT_LOAD - Bootloader - 0x57 - - - SPMCSR - Store Program Memory Control Register - 0x0 - read-only - - - SPMEN - Store Program Memory Enable - [0:0] - - - PGERS - Page Erase - [1:1] - - - PGWRT - Page Write - [2:2] - - - RFLB - Read fuse and lock bits - [3:3] - - - CTPB - Clear temporary page buffer - [4:4] - - - RSIG - Read Device Signature Imprint Table - [5:5] - - - - - - - CPU - CPU Registers - 0x31 - - RESET - External Pin, Power-on Reset, Brown-out Reset,Watchdog Reset - 0 - - - INT0 - External Interrupt 0 - 1 - - - PCINT0 - Pin change Interrupt Request 0 - 2 - - - TIMER1_COMPA - Timer/Counter1 Compare Match 1A - 3 - - - TIMER1_OVF - Timer/Counter1 Overflow - 4 - - - TIMER0_OVF - Timer/Counter0 Overflow - 5 - - - EE_RDY - EEPROM Ready - 6 - - - ANA_COMP - Analog comparator - 7 - - - ADC - ADC Conversion ready - 8 - - - TIMER1_COMPB - Timer/Counter1 Compare Match B - 9 - - - TIMER0_COMPA - Timer/Counter0 Compare Match A - 10 - - - TIMER0_COMPB - Timer/Counter0 Compare Match B - 11 - - - WDT - Watchdog Time-out - 12 - - - USI_START - USI START - 13 - - - USI_OVF - USI Overflow - 14 - - - - CLKPR - Clock Prescale Register - 0x15 - read-write - - - CLKPS - Clock Prescaler Select Bits - [3:0] - - true - - CLKPSread-writePRESCALER_1Prescaler Value 10PRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287PRESCALER_256Prescaler Value 2568 - - - CLKPCE - Clock Prescaler Change Enable - [7:7] - - - - - DWDR - debugWire data register - 0x11 - - - 0 - 255 - - - - - GPIOR0 - General purpose register 0 - 0x0 - - - 0 - 255 - - - - - GPIOR1 - General Purpose register 1 - 0x1 - - - 0 - 255 - - - - - GPIOR2 - General Purpose IO register 2 - 0x2 - - - 0 - 255 - - - - - MCUCR - MCU Control Register - 0x24 - - - SM - Sleep Mode Select Bits - [4:3] - - true - - - - IDLE - Idle - 0 - - - ADC - ADC Noise Reduction (If Available) - 1 - - - PDOWN - Power Down - 2 - - - VAL_0x03 - Reserved - 3 - - - - - SE - Sleep Enable - [5:5] - - - PUD - Pull-up Disable - [6:6] - - BODSBOD Sleep (available on some devices)71read-write - BODSEBOD Sleep Enable (available on some devices)21read-write - - - - MCUSR - MCU Status register - 0x23 - read-write - - - PORF - Power-On Reset Flag - [0:0] - - - EXTRF - External Reset Flag - [1:1] - - - BORF - Brown-out Reset Flag - [2:2] - - - WDRF - Watchdog Reset Flag - [3:3] - - - - - OSCCAL - Oscillator Calibration Register - 0x20 - read-write - - - OSCCAL - Oscillator Calibration - [7:0] - - - 0 - 255 - - - - - - - PLLCSR - PLL Control and status register - 0x16 - - - PLOCK - PLL Lock detector - [0:0] - read-only - - PLLE - PLL Enable - [1:1] - - - PCKE - PCK Enable - [2:2] - - - LSM - Low speed mode - [7:7] - - - - - PRR - Power Reduction Register - 0xF - - - PRADC - Power Reduction ADC - [0:0] - - - PRUSI - Power Reduction USI - [1:1] - - - PRTIM0 - Power Reduction Timer/Counter0 - [2:2] - - - PRTIM1 - Power Reduction Timer/Counter1 - [3:3] - - - - - - - EEPROM - EEPROM - 0x3C - - - EEAR - EEPROM Address Register Bytes - 0x2 - 16 - - - 0 - 65535 - - - - - EECR - EEPROM Control Register - 0x0 - - - EERE - EEPROM Read Enable - [0:0] - - - EEPE - EEPROM Write Enable - [1:1] - - - EEMPE - EEPROM Master Write Enable - [2:2] - - - EERIE - EEPROM Ready Interrupt Enable - [3:3] - - - EEPM - EEPROM Programming Mode Bits - [5:4] - - true - - EEPMread-writeATOMICAtomic (erase and write in one operation)0ERASEErase only1WRITEWrite only2 - - - - - EEDR - EEPROM Data Register - 0x1 - - - 0 - 255 - - - - - - - EXINT - External Interrupts - 0x35 - - - GIFR - General Interrupt Flag register - 0x25 - read-write - - - PCIF - Pin Change Interrupt Flag - [5:5] - - - INTF0 - External Interrupt Flag 0 - [6:6] - - - - - GIMSK - General Interrupt Mask Register - 0x26 - - - PCIE - Pin Change Interrupt Enable - [5:5] - - - INT0 - External Interrupt Request 0 Enable - [6:6] - - - - - MCUCR - MCU Control Register - 0x20 - - ISC0Interrupt Sense Control 0 bits02read-writeISC0read-writeLOWThe low level of INTx generates an interrupt request0TOGGLEAny logical change on INTx generates an interrupt request1FALLINGThe falling edge of INTx generates an interrupt request2RISINGThe rising edge of INTx generates an interrupt request3 - - - - - PCMSK - Pin Change Enable Mask - 0x0 - - - 0 - 255 - - - - - - - FUSE - Fuses - 0x0 - - - EXTENDED - <TBD> - 0x2 - - - SELFPRGEN - Self Programming enable - [0:0] - - - - - HIGH - <TBD> - 0x1 - - - BODLEVEL - Brown-out Detector trigger level - [2:0] - - true - - - - 4V3 - Brown-out detection at VCC=4.3 V - 4 - - - 2V7 - Brown-out detection at VCC=2.7 V - 5 - - - 1V8 - Brown-out detection at VCC=1.8 V - 6 - - - DISABLED - Brown-out detection disabled - 7 - - - - - EESAVE - Preserve EEPROM through the Chip Erase cycle - [3:3] - - - WDTON - Watch-dog Timer always on - [4:4] - - - SPIEN - Serial program downloading (SPI) enabled - [5:5] - - - DWEN - Debug Wire enable - [6:6] - - - RSTDISBL - Reset Disabled (Enable PB5 as i/o pin) - [7:7] - - - - - LOW - <TBD> - 0x0 - - - SUT_CKSEL - Select Clock source - [5:0] - - true - - - - EXTCLK_6CK_14CK_0MS - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 0 - - - PLLCLK_1KCK_14CK_4MS - PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms - 1 - - - INTRCOSC_8MHZ_6CK_14CK_0MS - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 2 - - - INTRCOSC_6MHZ4_6CK_14CK_64MS - ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms - 3 - - - WDOSC_128KHZ_6CK_14CK_0MS - WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 4 - - - EXTLOFXTAL_1KCK_14CK_0MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms - 6 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 8 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 9 - - - EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 10 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 11 - - - EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 12 - - - EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 13 - - - EXTXOSC_8MHZ_XX_258CK_14CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 14 - - - EXTXOSC_8MHZ_XX_1KCK_14CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 15 - - - EXTCLK_6CK_14CK_4MS1 - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - 16 - - - PLLCLK_16KCK_14CK_4MS - PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4 ms - 17 - - - INTRCOSC_8MHZ_6CK_14CK_4MS - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms - 18 - - - WDOSC_128KHZ_6CK_14CK_4MS - WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms - 20 - - - EXTLOFXTAL_1KCK_14CK_4MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms - 22 - - - EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 24 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 25 - - - EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 26 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 27 - - - EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 28 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 29 - - - EXTXOSC_8MHZ_XX_258CK_14CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 30 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 31 - - - EXTCLK_6CK_14CK_65MS - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms - 32 - - - PLLCLK_1KCK_14CK_64MS - PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 64 ms - 33 - - - INTRCOSC_8MHZ_6CK_14CK_64MS - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms - 34 - - - INTRCOSC_6MHZ4_6CK_14CK_4MS - ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms - 35 - - - WDOSC_128KHZ_6CK_14CK_64MS - WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms - 36 - - - EXTLOFXTAL_32KCK_14CK_64MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 64 ms - 38 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 40 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 41 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 42 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 43 - - - EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 44 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 45 - - - EXTXOSC_8MHZ_XX_1KCK_14CK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 46 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 47 - - - PLLCLK_16KCK_14CK_64MS - PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 64 ms - 49 - - - INTRCOSC_6MHZ4_1CK_14CK_0MS - ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 1 CK/14 CK + 0 ms - 51 - - - EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 56 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 57 - - - EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 58 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 59 - - - EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 60 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 61 - - - EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 62 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 63 - - - - - CKOUT - Clock output on PORTB4 - [6:6] - - - CKDIV8 - Divide clock by 8 internally - [7:7] - - - - - - - LOCKBIT - Lockbits - 0x0 - - - LOCKBIT - <TBD> - 0x0 - - - LB - Memory Lock - [1:0] - - true - - - - PROG_VER_DISABLED - Further programming and verification disabled - 0 - - - PROG_DISABLED - Further programming disabled - 2 - - - NO_LOCK - No memory lock features enabled - 3 - - - - - - - - - PORTB - I/O Port - 0x36 - - - DDRB - Data Direction Register, Port B - 0x1 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - - - PINB - Input Pins, Port B - 0x0 - read-write - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - - - PORTB - Data Register, Port B - 0x2 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - - - - - TC0 - Timer/Counter0, 8-bit, PWM - 0x48 - - - GTCCR - General Timer/Counter Control Register - 0x4 - - - PSR0 - Prescaler Reset Timer/Counter1 and Timer/Counter0 - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - OCR0A - Output Compare Register A - 0x1 - - - 0 - 255 - - - - - OCR0B - Output Compare Register B - 0x0 - - - 0 - 255 - - - - - TCCR0A - Timer/Counter Control Register A - 0x2 - - - WGM0 - Waveform Generation Mode - [1:0] - - true - WGM0read-writeNORMAL_TOPNormal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*0PWM_PHASEPhase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*1CTCCTC, Top: *OCRA*, Update: *Immediate*, Flag: *MAX*2PWM_FASTFast PWM, Top: `0xff`, Update: *BOTTOM*, Flag: *TOP*3 - - - COM0B - Compare Output B Mode - [5:4] - - true - COM0Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM0A - Compare Output A Mode - [7:6] - - true - - - - - - TCCR0B - Timer/Counter Control Register B - 0xB - - - CS0 - Clock Select - [2:0] - - true - - CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM02 - Waveform Generation Mode High Bit (Enable Top: *OCRA* for `PWM` modes) - [3:3] - - - FOC0B - Force Output Compare B - [6:6] - write-only - - FOC0A - Force Output Compare A - [7:7] - write-only - - - - TCNT0 - Timer/Counter0 - 0xA - - - 0 - 255 - - - - - TIFR - Timer/Counter0 Interrupt Flag register - 0x10 - - - TOV0 - Timer/Counter0 Overflow Flag - [1:1] - - - OCF0B - Timer/Counter0 Output Compare Flag 0B - [3:3] - - - OCF0A - Timer/Counter0 Output Compare Flag 0A - [4:4] - - - - - TIMSK - Timer/Counter Interrupt Mask Register - 0x11 - - - TOIE0 - Timer/Counter0 Overflow Interrupt Enable - [1:1] - - - OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable - [3:3] - - - OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable - [4:4] - - - - - - - TC1 - Timer/Counter1, 8-bit - 0x43 - - - DT1A - Dead Time Value Register A - 0x2 - - - DTVL - <TBD> - [3:0] - - - 0 - 15 - - - - - DTVH - <TBD> - [7:4] - - - 0 - 15 - - - - - - - DT1B - Dead Time Value Register B - 0x1 - - - DTVL - <TBD> - [3:0] - - - 0 - 15 - - - - - DTVH - <TBD> - [7:4] - - - 0 - 15 - - - - - - - DTPS - Dead time prescaler register - 0x0 - - - DTPS - <TBD> - [1:0] - - - 0 - 3 - - - DTPSread-writeDIRECTNo Prescaling0PRESCALE_2Division factor 21PRESCALE_4Division factor 42PRESCALE_8Division factor 83 - - - - - GTCCR - Timer counter control register - 0x9 - - - PSR1 - Prescaler Reset Timer/Counter1 - [1:1] - - - FOC1A - Force Output Compare 1A - [2:2] - write-only - - FOC1B - Force Output Compare Match 1B - [3:3] - write-only - - COM1B - Comparator B Output Mode - [5:4] - - - 0 - 3 - - - COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match1MATCH_CLEARClear OCix on Compare Match2MATCH_SETSet OCix on Compare Match3 - - - PWM1B - Pulse Width Modulator B Enable - [6:6] - - - - - OCR1A - Output Compare Register A - 0xB - - - 0 - 255 - - - - - OCR1B - Output Compare Register B - 0x8 - - - 0 - 255 - - - - - OCR1C - Output Compare Register C - 0xA - - - 0 - 255 - - - - - TCCR1 - Timer/Counter Control Register - 0xD - - - CS1 - Clock Select Bits - [3:0] - - true - - CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_2Running, CLK/22PRESCALE_4Running, CLK/43PRESCALE_8Running, CLK/84PRESCALE_16Running, CLK/165PRESCALE_32Running, CLK/326PRESCALE_64Running, CLK/647PRESCALE_128Running, CLK/1288PRESCALE_256Running, CLK/2569PRESCALE_512Running, CLK/51210PRESCALE_1024Running, CLK/102411PRESCALE_2048Running, CLK/204812PRESCALE_4096Running, CLK/409613PRESCALE_8192Running, CLK/819214PRESCALE_16384Running, CLK/1638415 - - - COM1A - Compare Output Mode, Bits - [5:4] - - true - - COM1Aread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match1MATCH_CLEARClear OCix on Compare Match2MATCH_SETSet OCix on Compare Match3 - - - PWM1A - Pulse Width Modulator Enable - [6:6] - - - CTC1 - Clear Timer/Counter on Compare Match - [7:7] - - - - - TCNT1 - Timer/Counter Register - 0xC - read-write - - - 0 - 255 - - - - - TIFR - Timer/Counter Interrupt Flag Register - 0x15 - - - TOV1 - Timer/Counter1 Overflow Flag - [2:2] - - - OCF1B - Timer/Counter1 Output Compare Flag 1B - [5:5] - - - OCF1A - Timer/Counter1 Output Compare Flag 1A - [6:6] - - - - - TIMSK - Timer/Counter Interrupt Mask Register - 0x16 - - - TOIE1 - Timer/Counter1 Overflow Interrupt Enable - [2:2] - - - OCIE1B - OCIE1A: Timer/Counter1 Output Compare B Interrupt Enable - [5:5] - - - OCIE1A - OCIE1A: Timer/Counter1 Output Compare Interrupt Enable - [6:6] - - - - - - - USI - Universal Serial Interface - 0x2D - - - USIBR - USI Buffer Register - 0x3 - read-only - - - 0 - 255 - - - - - USICR - USI Control Register - 0x0 - - - USITC - Toggle Clock Port Pin - [0:0] - write-only - - USICLK - Clock Strobe - [1:1] - write-only - - USICS - USI Clock Source Select Bits - [3:2] - - - 0 - 3 - - - USICSread-writeNO_CLOCKNo Clock/Software clock strobe0TC0Timer/Counter0 Compare Match1EXT_POSExternal, positive edge2EXT_NEGExternal, negative edge3 - - - USIWM - USI Wire Mode Bits - [5:4] - - true - - USIWMread-writeDISABLEDAll detectors disabled. Port pins operates as normal.0THREE_WIREThree-wire mode. Uses DO, DI, and USCK pins.1TWO_WIRE_SLAVETwo-wire mode (Slave). Uses SDA (DI) and SCL (USCK) pins.2TWO_WIRE_MASTERTwo-wire mode (Master). Uses SDA and SCL pins.3 - - - USIOIE - Counter Overflow Interrupt Enable - [6:6] - - - USISIE - Start Condition Interrupt Enable - [7:7] - - - - - USIDR - USI Data Register - 0x2 - - - 0 - 255 - - - - - USISR - USI Status Register - 0x1 - read-write - - - USICNT - USI Counter Value Bits - [3:0] - - - 0 - 15 - - - - - USIDC - Data Output Collision - [4:4] - read-only - - USIPF - Stop Condition Flag - [5:5] - - - USIOIF - Counter Overflow Interrupt Flag - [6:6] - - - USISIF - Start Condition Interrupt Flag - [7:7] - - - - - - - WDT - Watchdog Timer - 0x41 - - - WDTCR - Watchdog Timer Control Register - 0x0 - read-write - - - WDE - Watch Dog Enable - [3:3] - - - WDCE - Watchdog Change Enable - [4:4] - - - WDIE - Watchdog Timeout Interrupt Enable - [6:6] - - - WDIF - Watchdog Timeout Interrupt Flag - [7:7] - - WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 - - WDPHWatchdog Timer Prescaler - High Bit[5:5] - - - - - - \ No newline at end of file diff --git a/misc/svd/attiny861.svd b/misc/svd/attiny861.svd deleted file mode 100644 index caa9add..0000000 --- a/misc/svd/attiny861.svd +++ /dev/null @@ -1,2354 +0,0 @@ - - Atmel - ATtiny861 - 8 - 8 - read-write - 0 - 0xff - - - AC - Analog Comparator - 0x28 - - - ACSRA - Analog Comparator Control And Status Register A - 0x0 - read-write - - ACIS - Analog Comparator Interrupt Mode Select - [1:0] - - true - - ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 - - - ACME - Analog Comparator Multiplexer Enable - [2:2] - - - ACIE - Analog Comparator Interrupt Enable - [3:3] - - - ACI - Analog Comparator Interrupt Flag - [4:4] - - - ACO - Analog Compare Output - [5:5] - read-only - - ACBG - Analog Comparator Bandgap Select - [6:6] - - - ACD - Analog Comparator Disable - [7:7] - - - - - ACSRB - Analog Comparator Control And Status Register B - 0x1 - - - ACM - Analog Comparator Multiplexer - [2:0] - - - 0 - 7 - - - - - HLEV - Hysteresis Level - [6:6] - - - HSEL - Hysteresis Select - [7:7] - - - - - - - ADC - Analog-to-Digital Converter - 0x21 - - - ADC - ADC Data Register Bytes - 0x3 - 16 - - - 0 - 65535 - - - - - ADCSRA - The ADC Control and Status register - 0x5 - read-write - - - ADPS - ADC Prescaler Select Bits - [2:0] - - true - - ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 - - - ADIE - ADC Interrupt Enable - [3:3] - - - ADIF - ADC Interrupt Flag - [4:4] - - - ADATE - ADC Auto Trigger Enable - [5:5] - - - ADSC - ADC Start Conversion - [6:6] - - - ADEN - ADC Enable - [7:7] - - - - - ADCSRB - ADC Control and Status Register B - 0x2 - - - ADTS - ADC Auto Trigger Sources - [2:0] - - true - - - - VAL_0x00 - Free Running mode - 0 - - - VAL_0x01 - Analog Comparator - 1 - - - VAL_0x02 - External Interrupt Request 0 - 2 - - - VAL_0x03 - Timer/Counter0 Compare Match A - 3 - - - VAL_0x04 - Timer/Counter0 Overflow - 4 - - - VAL_0x05 - Timer/Counter1 Compare Match B - 5 - - - VAL_0x06 - Timer/Counter1 Overflow - 6 - - - VAL_0x07 - Watchdog Interrupt Request - 7 - - - - - MUX5 - Analog Channel and Gain Selection Bit 5 - [3:3] - - - REFS2 - Reference Selection Bit - [4:4] - - - IPR - Input Polarity Mode - [5:5] - - - GSEL - Gain Select - [6:6] - - - BIN - Bipolar Input Mode - [7:7] - - - - - ADMUX - The ADC multiplexer Selection Register - 0x6 - - - MUX - Analog Channel and Gain Selection Bits - [4:0] - - - 0 - 31 - - - - - ADLAR - Left Adjust Result - [5:5] - - - REFS - Reference Selection Bits - [7:6] - - - 0 - 3 - - - REFSread-writeAREFAref Internal Vref turned off0AVCCAVcc with external capacitor at AREF pin1INTERNALInternal 1.1V Voltage Reference with external capacitor at AREF pin3 - - - - - DIDR0 - Digital Input Disable Register 0 - 0x0 - - - ADC0D - ADC0 Digital input Disable - [0:0] - - - ADC1D - ADC1 Digital input Disable - [1:1] - - - ADC2D - ADC2 Digital input Disable - [2:2] - - - AREFD - AREF Digital Input Disable - [3:3] - - - ADC3D - ADC3 Digital input Disable - [4:4] - - - ADC4D - ADC4 Digital input Disable - [5:5] - - - ADC5D - ADC5 Digital input Disable - [6:6] - - - ADC6D - ADC6 Digital input Disable - [7:7] - - - - - DIDR1 - Digital Input Disable Register 1 - 0x1 - - - ADC7D - ADC7 Digital input Disable - [4:4] - - - ADC8D - ADC8 Digital input Disable - [5:5] - - - ADC9D - ADC9 Digital input Disable - [6:6] - - - ADC10D - ADC10 Digital input Disable - [7:7] - - - - - - - BOOT_LOAD - Bootloader - 0x57 - - - SPMCSR - Store Program Memory Control Register - 0x0 - read-only - - - SPMEN - Store Program Memory Enable - [0:0] - - - PGERS - Page Erase - [1:1] - - - PGWRT - Page Write - [2:2] - - - RFLB - Read fuse and lock bits - [3:3] - - - CTPB - Clear temporary page buffer - [4:4] - - - - - - - CPU - CPU Registers - 0x2A - - RESET - External Reset, Power-on Reset and Watchdog Reset - 0 - - - INT0 - External Interrupt 0 - 1 - - - PCINT - Pin Change Interrupt - 2 - - - TIMER1_COMPA - Timer/Counter1 Compare Match 1A - 3 - - - TIMER1_COMPB - Timer/Counter1 Compare Match 1B - 4 - - - TIMER1_OVF - Timer/Counter1 Overflow - 5 - - - TIMER0_OVF - Timer/Counter0 Overflow - 6 - - - USI_START - USI Start - 7 - - - USI_OVF - USI Overflow - 8 - - - EE_RDY - EEPROM Ready - 9 - - - ANA_COMP - Analog Comparator - 10 - - - ADC - ADC Conversion Complete - 11 - - - WDT - Watchdog Time-Out - 12 - - - INT1 - External Interrupt 1 - 13 - - - TIMER0_COMPA - Timer/Counter0 Compare Match A - 14 - - - TIMER0_COMPB - Timer/Counter0 Compare Match B - 15 - - - TIMER0_CAPT - ADC Conversion Complete - 16 - - - TIMER1_COMPD - Timer/Counter1 Compare Match D - 17 - - - FAULT_PROTECTION - Timer/Counter1 Fault Protection - 18 - - - - CLKPR - Clock Prescale Register - 0x1E - read-only - - - CLKPS - Clock Prescaler Select Bits - [3:0] - - true - - - - VAL_0x00 - 1 - 0 - - - VAL_0x01 - 2 - 1 - - - VAL_0x02 - 4 - 2 - - - VAL_0x03 - 8 - 3 - - - VAL_0x04 - 16 - 4 - - - VAL_0x05 - 32 - 5 - - - VAL_0x06 - 64 - 6 - - - VAL_0x07 - 128 - 7 - - - VAL_0x08 - 256 - 8 - - - - - CLKPCE - Clock Prescaler Change Enable - [7:7] - - - - - DWDR - debugWire data register - 0x16 - - - 0 - 255 - - - - - GPIOR0 - General purpose register 0 - 0x0 - - - 0 - 255 - - - - - GPIOR1 - General Purpose register 1 - 0x1 - - - 0 - 255 - - - - - GPIOR2 - General Purpose IO register 2 - 0x2 - - - 0 - 255 - - - - - MCUCR - MCU Control Register - 0x2B - - - ISC0 - Interrupt Sense Control 0 bits - [1:0] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change in INTX - 1 - - - VAL_0x02 - Falling Edge of INTX - 2 - - - VAL_0x03 - Rising Edge of INTX - 3 - - - - - SM - Sleep Mode Select Bits - [4:3] - - true - - - - IDLE - Idle - 0 - - - ADC - ADC Noise Reduction (If Available) - 1 - - - PDOWN - Power Down - 2 - - - STDBY - Standby - 3 - - - - - SE - Sleep Enable - [5:5] - - - PUD - Pull-up Disable - [6:6] - - - - - MCUSR - MCU Status register - 0x2A - - - PORF - Power-On Reset Flag - [0:0] - - - EXTRF - External Reset Flag - [1:1] - - - BORF - Brown-out Reset Flag - [2:2] - - - WDRF - Watchdog Reset Flag - [3:3] - - - - - OSCCAL - Oscillator Calibration Register - 0x27 - read-only - - - OSCCAL - Oscillator Calibration - [7:0] - - - 0 - 255 - - - - - - - PLLCSR - PLL Control and status register - 0x1F - - - PLOCK - PLL Lock detector - [0:0] - - - PLLE - PLL Enable - [1:1] - - - PCKE - PCK Enable - [2:2] - - - LSM - Low speed mode - [7:7] - - - - - PRR - Power Reduction Register - 0x2C - - - PRADC - Power Reduction ADC - [0:0] - - - PRUSI - Power Reduction USI - [1:1] - - - PRTIM0 - Power Reduction Timer/Counter0 - [2:2] - - - PRTIM1 - Power Reduction Timer/Counter1 - [3:3] - - - - - - - EEPROM - EEPROM - 0x3C - - - EEAR - EEPROM Address Register Bytes - 0x2 - 16 - - - 0 - 65535 - - - - - EECR - EEPROM Control Register - 0x0 - - - EERE - EEPROM Read Enable - [0:0] - - - EEPE - EEPROM Write Enable - [1:1] - - - EEMPE - EEPROM Master Write Enable - [2:2] - - - EERIE - EEPROM Ready Interrupt Enable - [3:3] - - - EEPM - EEPROM Programming Mode Bits - [5:4] - - true - - - - VAL_0x00 - Erase and Write in one operation - 0 - - - VAL_0x01 - Erase Only - 1 - - - VAL_0x02 - Write Only - 2 - - - - - - - EEDR - EEPROM Data Register - 0x1 - - - 0 - 255 - - - - - - - EXINT - External Interrupts - 0x42 - - - GIFR - General Interrupt Flag register - 0x18 - read-only - - - PCIF - Pin Change Interrupt Flag - [5:5] - - - INTF - External Interrupt Flags - [7:6] - - - 0 - 3 - - - - - - - GIMSK - General Interrupt Mask Register - 0x19 - - - PCIE - Pin Change Interrupt Enables - [5:4] - - - 0 - 3 - - - - - INT - External Interrupt Request 1 Enable - [7:6] - - - 0 - 3 - - - - - - - MCUCR - MCU Control Register - 0x13 - - - ISC00 - Interrupt Sense Control 0 Bit 0 - [0:0] - - true - - - - VAL_0x00 - Low Level of INTX - 0 - - - VAL_0x01 - Any Logical Change of INTX - 1 - - - - - ISC01 - Interrupt Sense Control 0 Bit 1 - [1:1] - - - - - PCMSK0 - Pin Change Enable Mask 0 - 0x1 - - - 0 - 255 - - - - - PCMSK1 - Pin Change Enable Mask 1 - 0x0 - - - 0 - 255 - - - - - - - FUSE - Fuses - 0x0 - - - EXTENDED - <TBD> - 0x2 - - - SELFPRGEN - Self Programming enable - [0:0] - - - - - HIGH - <TBD> - 0x1 - - - BODLEVEL - Brown-out Detector trigger level - [2:0] - - true - - - - 2V0 - Brown-out detection at VCC=2.0 V - 0 - - - 1V9 - Brown-out detection at VCC=1.9 V - 1 - - - 2V2 - Brown-out detection at VCC=2.2 V - 2 - - - 2V3 - Brown-out detection at VCC=2.3 V - 3 - - - 4V3 - Brown-out detection at VCC=4.3 V - 4 - - - 2V7 - Brown-out detection at VCC=2.7 V - 5 - - - 1V8 - Brown-out detection at VCC=1.8 V - 6 - - - DISABLED - Brown-out detection disabled - 7 - - - - - EESAVE - Preserve EEPROM through the Chip Erase cycle - [3:3] - - - WDTON - Watch-dog Timer always on - [4:4] - - - SPIEN - Serial program downloading (SPI) enabled - [5:5] - - - DWEN - Debug Wire enable - [6:6] - - - RSTDISBL - Reset Disabled (Enable PB7 as i/o pin) - [7:7] - - - - - LOW - <TBD> - 0x0 - - - SUT_CKSEL - Select Clock source - [5:0] - - true - - - - EXTCLK_6CK_14CK_0MS - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 0 - - - PLLCLK_1KCK_14CK_8MS - PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 8 ms - 1 - - - INTRCOSC_8MHZ_6CK_14CK_0MS - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 2 - - - WDOSC_128KHZ_6CK_14CK_0MS - WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 3 - - - EXTLOFXTAL_1CK_4MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1 CK 4 ms - 4 - - - EXTCRES_0MHZ4_0MHZ9_258CK_14CK_4MS1 - Ext. Ceramic Res. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 8 - - - EXTCRES_0MHZ4_0MHZ9_1KCK_14CK_65MS - Ext. Ceramic Res. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 9 - - - EXTCRES_0MHZ9_3MHZ_258CK_14CK_4MS1 - Ext. Ceramic Res. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 10 - - - EXTCRES_0MHZ9_3MHZ_1KCK_14CK_65MS - Ext. Ceramic Res. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 11 - - - EXTCRES_3MHZ_8MHZ_258CK_14CK_4MS1 - Ext. Ceramic Res. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 12 - - - EXTCRES_3MHZ_8MHZ_1KCK_14CK_65MS - Ext. Ceramic Res. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 13 - - - EXTCRES_8MHZ_XX_258CK_14CK_4MS1 - Ext. Ceramic Res. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms - 14 - - - EXTCRES_8MHZ_XX_1KCK_14CK_65MS - Ext. Ceramic Res. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms - 15 - - - EXTCLK_6CK_14CK_4MS - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms - 16 - - - PLLCLK_16KCK_14CK_8MS - PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 8 ms - 17 - - - INTRCOSC_8MHZ_6CK_14CK_4MS - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms - 18 - - - WDOSC_128KHZ_6CK_14CK_4MS - WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms - 19 - - - EXTLOFXTAL_1CK_64MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1 CK + 64 ms - 20 - - - EXTCRES_0MHZ4_0MHZ9_258CK_14CK_65MS - Ext. Ceramic Res. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 24 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 25 - - - EXTCRES_0MHZ9_3MHZ_258CK_14CK_65MS - Ext. Ceramic Res. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 26 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 27 - - - EXTCRES_3MHZ_8MHZ_258CK_14CK_65MS - Ext. Ceramic Res. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 28 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 29 - - - EXTCRES_8MHZ_XX_258CK_14CK_65MS - Ext. Ceramic Res. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms - 30 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_0MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms - 31 - - - EXTCLK_6CK_14CK_64MS - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms - 32 - - - PLLCLK_1KCK_14CK_68MS - PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 68 ms - 33 - - - INTRCOSC_8MHZ_6CK_14CK_64MS - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms - 34 - - - WDOSC_128KHZ_6CK_14CK_64MS - WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms - 35 - - - EXTLOFXTAL_32CK_64MS - Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32 CK + 64 ms - 36 - - - EXTCRES_0MHZ4_0MHZ9_1KCK_14CK_0MS - Ext. Ceramic Res. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 40 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 41 - - - EXTCRES_0MHZ9_3MHZ_1KCK_14CK_0MS - Ext. Ceramic Res. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 42 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 43 - - - EXTCRES_3MHZ_8MHZ_1KCK_14CK_0MS - Ext. Ceramic Res. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 44 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 45 - - - EXTCRES_8MHZ_XX_1KCK_14CK_0MS - Ext. Ceramic Res. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms - 46 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms - 47 - - - PLLCLK_16KCK_14CK_68MS - PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 68 ms - 49 - - - EXTCRES_0MHZ4_0MHZ9_1KCK_14CK_4MS1 - Ext. Ceramic Res. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 56 - - - EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS - Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 57 - - - EXTCRES_0MHZ9_3MHZ_1KCK_14CK_4MS1 - Ext. Ceramic Res. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 58 - - - EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS - Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 59 - - - EXTCRES_3MHZ_8MHZ_1KCK_14CK_4MS1 - Ext. Ceramic Res. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 60 - - - EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS - Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 61 - - - EXTCRES_8MHZ_XX_1KCK_14CK_4MS1 - Ext. Ceramic Res. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms - 62 - - - EXTXOSC_8MHZ_XX_16KCK_14CK_65MS - Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms - 63 - - - - - CKOUT - Clock output on PORTB5 - [6:6] - - - CKDIV8 - Divide clock by 8 internally - [7:7] - - - - - - - LOCKBIT - Lockbits - 0x0 - - - LOCKBIT - <TBD> - 0x0 - - - LB - Memory Lock - [1:0] - - true - - - - PROG_VER_DISABLED - Further programming and verification disabled - 0 - - - PROG_DISABLED - Further programming disabled - 2 - - - NO_LOCK - No memory lock features enabled - 3 - - - - - - - - - PORTA - I/O Port - 0x39 - - - DDRA - Port A Data Direction Register - 0x1 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - PINA - Port A Input Pins - 0x0 - read-write - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - PORTA - Port A Data Register - 0x2 - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - PA4 - Pin A4 - [4:4] - - - PA5 - Pin A5 - [5:5] - - - PA6 - Pin A6 - [6:6] - - - PA7 - Pin A7 - [7:7] - - - - - - - PORTB - I/O Port - 0x36 - - - DDRB - Port B Data Direction Register - 0x1 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PINB - Port B Input Pins - 0x0 - read-write - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PORTB - Port B Data Register - 0x2 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - - - TC0 - Timer/Counter0 - 0x32 - - - OCR0A - Timer/Counter0 Output Compare Register - 0x1 - - - 0 - 255 - - - - - OCR0B - Timer/Counter0 Output Compare Register - 0x0 - - - 0 - 255 - - - - - TCCR0A - Timer/Counter Control Register A - 0x3 - - - WGM00 - Waveform Generation Mode - [0:0] - - - ACIC0 - Analog Comparator Input Capture Enable - [3:3] - - - ICES0 - Input Capture Edge Select - [4:4] - - - ICNC0 - Input Capture Noice Canceler - [5:5] - - - ICEN0 - Input Capture Mode Enable - [6:6] - - - TCW0 - Timer/Counter 0 Width - [7:7] - - - - - TCCR0B - Timer/Counter Control Register B - 0x21 - - - CS0 - Clock Select - [2:0] - - true - CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - PSR0 - Timer/Counter 0 Prescaler Reset - [3:3] - - - TSM - Timer/Counter Synchronization Mode - [4:4] - - - - - TCNT0H - Timer/Counter0 High - 0x2 - - - 0 - 255 - - - - - TCNT0L - Timer/Counter0 Low - 0x20 - - - 0 - 255 - - - - - TIFR - Timer/Counter0 Interrupt Flag register - 0x26 - read-only - - - ICF0 - Timer/Counter0 Input Capture Flag - [0:0] - - - TOV0 - Timer/Counter0 Overflow Flag - [1:1] - - - OCF0B - Timer/Counter0 Output Compare Flag 0B - [3:3] - - - OCF0A - Timer/Counter0 Output Compare Flag 0A - [4:4] - - - - - TIMSK - Timer/Counter Interrupt Mask Register - 0x27 - - - TICIE0 - Timer/Counter0 Input Capture Interrupt Enable - [0:0] - - - TOIE0 - Timer/Counter0 Overflow Interrupt Enable - [1:1] - - - OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable - [3:3] - - - OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable - [4:4] - - - - - - - TC1 - Timer/Counter1, 10-bit - 0x20 - - - DT1 - Timer/Counter 1 Dead Time Value - 0x24 - - - DT1L - <TBD> - [3:0] - - - 0 - 15 - - - - - DT1H - <TBD> - [7:4] - - - 0 - 15 - - - - - - - OCR1A - Output Compare Register - 0x2D - - - 0 - 255 - - - - - OCR1B - Output Compare Register - 0x2C - - - 0 - 255 - - - - - OCR1C - Output compare register - 0x2B - - - 0 - 255 - - - - - OCR1D - Output compare register - 0x2A - read-only - - - 0 - 255 - - - - - TC1H - Timer/Counter High Bits - 0x25 - - - 0 - 255 - - - - - TCCR1A - Timer/Counter Control Register A - 0x30 - - - PWM1B - Pulse Width Modulator Enable - [0:0] - - - PWM1A - Pulse Width Modulator Enable - [1:1] - - - FOC1B - Force Output Compare Match 1B - [2:2] - write-only - - FOC1A - Force Output Compare Match 1A - [3:3] - write-only - - COM1B - Compare Output Mode, Bits - [5:4] - - true - COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 - - - COM1A - Compare Output Mode, Bits - [7:6] - - true - - - - - - TCCR1B - Timer/Counter Control Register B - 0x2F - - - CS1 - Clock Select Bits - [3:0] - - true - CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_2Running, CLK/22PRESCALE_4Running, CLK/43PRESCALE_8Running, CLK/84PRESCALE_16Running, CLK/165PRESCALE_32Running, CLK/326PRESCALE_64Running, CLK/647PRESCALE_128Running, CLK/1288PRESCALE_256Running, CLK/2569PRESCALE_512Running, CLK/51210PRESCALE_1024Running, CLK/102411PRESCALE_2048Running, CLK/204812PRESCALE_4096Running, CLK/409613PRESCALE_8192Running, CLK/819214PRESCALE_16384Running, CLK/1638415 - - - DTPS1 - Dead Time Prescaler - [5:4] - - true - - DTPS1read-writeX11x (no division)0X22x1X44x2X88x3 - - - PSR1 - Timer/Counter 1 Prescaler reset - [6:6] - - - PWM1X - PWM Inversion Mode - [7:7] - - - - - TCCR1C - Timer/Counter Control Register C - 0x27 - - - PWM1D - Pulse Width Modulator D Enable - [0:0] - - - FOC1D - Force Output Compare Match 1D - [1:1] - write-only - - COM1D - Comparator D output mode - [3:2] - - true - COM1Dread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at TOP)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at TOP)3 - - - COM1B0S - COM1B0 Shadow Bit - [4:4] - - - COM1B1S - COM1B1 Shadow Bit - [5:5] - - - COM1A0S - COM1A0 Shadow Bit - [6:6] - - - COM1A1S - COM1A1 Shadow Bit - [7:7] - - - - - TCCR1D - Timer/Counter Control Register D - 0x26 - - - WGM1 - Waveform Generation Mode Bit - [1:0] - - true - WGM1read-writePWM_FASTFast PWM, Update: *TOP*, Flag: *TOP*0PWM_CORRECTPhase and Frequency Correct PWM, Update: *BOTTOM*, Flag: *BOTTOM*1PWM_SINGLE_SLOPEPWM6 / Single-slope, Update: *TOP*, Flag: *TOP*2PWM_DUAL_SLOPEPWM6 / Dual-slope, Update: *BOTTOM*, Flag: *BOTTOM*3 - - - FPF1 - Fault Protection Interrupt Flag - [2:2] - - - FPAC1 - Fault Protection Analog Comparator Enable - [3:3] - - - FPES1 - Fault Protection Edge Select - [4:4] - - - FPNC1 - Fault Protection Noise Canceler - [5:5] - - - FPEN1 - Fault Protection Mode Enable - [6:6] - - - FPIE1 - Fault Protection Interrupt Enable - [7:7] - - - - - TCCR1E - Timer/Counter1 Control Register E - 0x0 - - - OC1OE - Ouput Compare Override Enable Bits - [5:0] - - - 0 - 63 - - - - - - - TCNT1 - Timer/Counter Register - 0x2E - read-only - - - 0 - 255 - - - - - TIFR - Timer/Counter Interrupt Flag Register - 0x38 - read-only - - - TOV1 - Timer/Counter1 Overflow Flag - [2:2] - - - OCF1B - Timer/Counter1 Output Compare Flag 1B - [5:5] - - - OCF1A - Timer/Counter1 Output Compare Flag 1A - [6:6] - - - OCF1D - Timer/Counter1 Output Compare Flag 1D - [7:7] - - - - - TIMSK - Timer/Counter Interrupt Mask Register - 0x39 - - - TOIE1 - Timer/Counter1 Overflow Interrupt Enable - [2:2] - - - OCIE1B - OCIE1A: Timer/Counter1 Output Compare B Interrupt Enable - [5:5] - - - OCIE1A - OCIE1A: Timer/Counter1 Output Compare Interrupt Enable - [6:6] - - - OCIE1D - OCIE1D: Timer/Counter1 Output Compare Interrupt Enable - [7:7] - - - - - - - USI - Universal Serial Interface - 0x2D - - - USIBR - USI Buffer Register - 0x3 - read-only - - - 0 - 255 - - - - - USICR - USI Control Register - 0x0 - - - USITC - Toggle Clock Port Pin - [0:0] - write-only - - USICLK - Clock Strobe - [1:1] - write-only - - USICS - USI Clock Source Select Bits - [3:2] - - - 0 - 3 - - - USICSread-writeNO_CLOCKNo Clock/Software clock strobe0TC0Timer/Counter0 Compare Match1EXT_POSExternal, positive edge2EXT_NEGExternal, negative edge3 - - - USIWM - USI Wire Mode Bits - [5:4] - - true - - USIWMread-writeDISABLEDAll detectors disabled. Port pins operates as normal.0THREE_WIREThree-wire mode. Uses DO, DI, and USCK pins.1TWO_WIRE_SLAVETwo-wire mode (Slave). Uses SDA (DI) and SCL (USCK) pins.2TWO_WIRE_MASTERTwo-wire mode (Master). Uses SDA and SCL pins.3 - - - USIOIE - Counter Overflow Interrupt Enable - [6:6] - - - USISIE - Start Condition Interrupt Enable - [7:7] - - - - - USIDR - USI Data Register - 0x2 - - - 0 - 255 - - - - - USIPP - USI Pin Position - 0x4 - - - 0 - 255 - - - - - USISR - USI Status Register - 0x1 - read-write - - - USICNT - USI Counter Value Bits - [3:0] - - - 0 - 15 - - - - - USIDC - Data Output Collision - [4:4] - read-only - - USIPF - Stop Condition Flag - [5:5] - - - USIOIF - Counter Overflow Interrupt Flag - [6:6] - - - USISIF - Start Condition Interrupt Flag - [7:7] - - - - - - - WDT - Watchdog Timer - 0x41 - - - WDTCR - Watchdog Timer Control Register - 0x0 - read-write - - - WDE - Watch Dog Enable - [3:3] - - - WDCE - Watchdog Change Enable - [4:4] - - - WDIE - Watchdog Timeout Interrupt Enable - [6:6] - - - WDIF - Watchdog Timeout Interrupt Flag - [7:7] - - WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 - - WDPHWatchdog Timer Prescaler - High Bit[5:5] - - - - - - \ No newline at end of file diff --git a/misc/svd/attiny88.svd b/misc/svd/attiny88.svd deleted file mode 100644 index 85078aa..0000000 --- a/misc/svd/attiny88.svd +++ /dev/null @@ -1,2237 +0,0 @@ - - Atmel - ATtiny88 - 8 - 8 - read-write - 0 - 0xff - - - AC - Analog Comparator - 0x50 - - - ACSR - Analog Comparator Control And Status Register - 0x0 - read-write - - - ACIS - Analog Comparator Interrupt Mode Select - [1:0] - - true - - ACISread-writeON_TOGGLEInterrupt on Toggle0ON_FALLING_EDGEInterrupt on Falling Edge2ON_RISING_EDGEInterrupt on Rising Edge3 - - - ACIC - Analog Comparator Input Capture Enable - [2:2] - - - ACIE - Analog Comparator Interrupt Enable - [3:3] - - - ACI - Analog Comparator Interrupt Flag - [4:4] - - - ACO - Analog Compare Output - [5:5] - read-only - - ACBG - Analog Comparator Bandgap Select - [6:6] - - - ACD - Analog Comparator Disable - [7:7] - - - - - DIDR1 - Digital Input Disable Register 1 - 0x2F - - - AIN0D - AIN0 Digital Input Disable - [0:0] - - - AIN1D - AIN1 Digital Input Disable - [1:1] - - - - - - - ADC - Analog-to-Digital Converter - 0x78 - - - ADC - ADC Data Register Bytes - 0x0 - 16 - - - 0 - 65535 - - - - - ADCSRA - The ADC Control and Status register A - 0x2 - - - ADPS - ADC Prescaler Select Bits - [2:0] - - true - - ADPSread-writePRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287 - - - ADIE - ADC Interrupt Enable - [3:3] - - - ADIF - ADC Interrupt Flag - [4:4] - - - ADATE - ADC Auto Trigger Enable - [5:5] - - - ADSC - ADC Start Conversion - [6:6] - - - ADEN - ADC Enable - [7:7] - - - - - ADCSRB - The ADC Control and Status register B - 0x3 - - - ADTS - ADC Auto Trigger Source bits - [2:0] - - true - - ADTSread-writeFREEFree Running mode0ACAnalog Comparator1INT0External Interrupt Request 02TC0_CMATimer/Counter0 Compare Match A3TC0_OVFTimer/Counter0 Overflow4TC1_CMBTimer/Counter1 Compare Match B5TC1_OVFTimer/Counter1 Overflow6TC1_CETimer/Counter1 Capture Event7 - - - ACME - <TBD> - [6:6] - - - - - ADMUX - The ADC multiplexer Selection Register - 0x4 - - - MUX - Analog Channel Selection Bits - [3:0] - - - 0 - 15 - - - MUXread-writeADC0ADC Single Ended Input pin 00ADC1ADC Single Ended Input pin 11ADC2ADC Single Ended Input pin 22ADC3ADC Single Ended Input pin 33ADC4ADC Single Ended Input pin 44ADC5ADC Single Ended Input pin 55ADC6ADC Single Ended Input pin 66ADC7ADC Single Ended Input pin 77TEMPSENSTemperature sensor8ADC_VBGInternal Reference (VBG)14ADC_GND0V (GND)15 - - - ADLAR - Left Adjust Result - [5:5] - - - REFS0 - Reference Selection Bit 0 - [6:6] - - true - - REFS0read-writeINTERNALInternal 1.1V Voltage Reference0AVCCAVcc Reference1 - - - - - DIDR0 - Digital Input Disable Register 0 - 0x6 - - - ADC0D - <TBD> - [0:0] - - - ADC1D - <TBD> - [1:1] - - - ADC2D - <TBD> - [2:2] - - - ADC3D - <TBD> - [3:3] - - - ADC4D - <TBD> - [4:4] - - - ADC5D - <TBD> - [5:5] - - - ADC6D - <TBD> - [6:6] - - - ADC7D - <TBD> - [7:7] - - - - - DIDR1 - Digital Input Disable Register 1 - 0x7 - - - AIN0D - <TBD> - [0:0] - - - AIN1D - <TBD> - [1:1] - - - - - - - CPU - CPU Registers - 0x32 - - RESET - External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset - 0 - - - INT0 - External Interrupt Request 0 - 1 - - - INT1 - External Interrupt Request 1 - 2 - - - PCINT0 - Pin Change Interrupt Request 0 - 3 - - - PCINT1 - Pin Change Interrupt Request 1 - 4 - - - PCINT2 - Pin Change Interrupt Request 2 - 5 - - - PCINT3 - Pin Change Interrupt Request 3 - 6 - - - WDT - Watchdog Time-out Interrupt - 7 - - - TIMER1_CAPT - Timer/Counter1 Capture Event - 8 - - - TIMER1_COMPA - Timer/Counter1 Compare Match A - 9 - - - TIMER1_COMPB - Timer/Counter1 Compare Match B - 10 - - - TIMER1_OVF - Timer/Counter1 Overflow - 11 - - - TIMER0_COMPA - TimerCounter0 Compare Match A - 12 - - - TIMER0_COMPB - TimerCounter0 Compare Match B - 13 - - - TIMER0_OVF - Timer/Couner0 Overflow - 14 - - - SPI_STC - SPI Serial Transfer Complete - 15 - - - ADC - ADC Conversion Complete - 16 - - - EE_RDY - EEPROM Ready - 17 - - - ANALOG_COMP - Analog Comparator - 18 - - - TWI - Two-wire Serial Interface - 19 - - - - CLKPR - Clock Prescale Register - 0x2F - read-write - - - CLKPS - Clock Prescaler Select Bits - [3:0] - - true - - CLKPSread-writePRESCALER_1Prescaler Value 10PRESCALER_2Prescaler Value 21PRESCALER_4Prescaler Value 42PRESCALER_8Prescaler Value 83PRESCALER_16Prescaler Value 164PRESCALER_32Prescaler Value 325PRESCALER_64Prescaler Value 646PRESCALER_128Prescaler Value 1287PRESCALER_256Prescaler Value 2568 - - - CLKPCE - Clock Prescaler Change Enable - [7:7] - - - - - GPIOR0 - General Purpose I/O Register 0 - 0xC - - - 0 - 255 - - - - - GPIOR1 - General Purpose I/O Register 1 - 0x18 - - - 0 - 255 - - - - - GPIOR2 - General Purpose I/O Register 2 - 0x19 - - - 0 - 255 - - - - - MCUCR - MCU Control Register - 0x23 - - - PUD - Pull-up Disable - [4:4] - - - BODSE - BOD Sleep Enable - [5:5] - - - BODS - BOD Sleep - [6:6] - - - - - MCUSR - MCU Status Register - 0x22 - - - PORF - Power-on reset flag - [0:0] - - - EXTRF - External Reset Flag - [1:1] - - - BORF - Brown-out Reset Flag - [2:2] - - - WDRF - Watchdog Reset Flag - [3:3] - - - - - OSCCAL - Oscillator Calibration Value - 0x34 - read-write - - - OSCCAL - Oscillator Calibration - [7:0] - - - 0 - 255 - - - - - - - PORTCR - Port Configuration Register - 0x0 - read-write - - - PUDA - <TBD> - [0:0] - - - PUDB - <TBD> - [1:1] - - - PUDC - <TBD> - [2:2] - - - PUDD - <TBD> - [3:3] - - - BBMA - <TBD> - [4:4] - - - BBMB - <TBD> - [5:5] - - - BBMC - <TBD> - [6:6] - - - BBMD - <TBD> - [7:7] - - - - - PRR - Power Reduction Register - 0x32 - read-write - - - PRADC - Power Reduction ADC - [0:0] - - - PRSPI - Power Reduction Serial Peripheral Interface - [2:2] - - - PRTIM1 - Power Reduction Timer/Counter1 - [3:3] - - - PRTIM0 - Power Reduction Timer/Counter0 - [5:5] - - - PRTWI - Power Reduction TWI - [7:7] - - - - - SMCR - Sleep Mode Control Register - 0x21 - - - SE - Sleep Enable - [0:0] - - - SM - Sleep Mode - [2:1] - - true - - SMread-writeIDLEIdle0ADCADC Noise Reduction1PDOWNPower-down2 - - - - - SPH - Stack Pointer High - 0x2C - - - 0 - 255 - - - - - SPL - Stack Pointer Low - 0x2B - - - 0 - 255 - - - - - SPMCSR - Store Program Memory Control Register - 0x25 - - - SELFPRGEN - Self Programming Enable - [0:0] - - - PGERS - Page Erase - [1:1] - - - PGWRT - Page Write - [2:2] - - - RFLB - Read Fuse and Lock Bits - [3:3] - - - CTPB - Clear Temporary Page Buffer - [4:4] - - - RWWSB - Read-While-Write Section Busy - [6:6] - - - - - - - EEPROM - EEPROM - 0x3F - - - EEARL - EEPROM Address Register Low Byte - 0x2 - - - 0 - 255 - - - - - EECR - EEPROM Control Register - 0x0 - - - EERE - EEPROM Read Enable - [0:0] - - - EEPE - EEPROM Write Enable - [1:1] - - - EEMPE - EEPROM Master Write Enable - [2:2] - - - EERIE - EEPROM Ready Interrupt Enable - [3:3] - - - EEPM - EEPROM Programming Mode Bits - [5:4] - - true - - EEPMread-writeATOMICAtomic (erase and write in one operation)0ERASEErase only1WRITEWrite only2 - - - - - EEDR - EEPROM Data Register - 0x1 - - - 0 - 255 - - - - - - - EXINT - External Interrupts - 0x3B - - - EICRA - External Interrupt Control Register - 0x2E - - - ISC0 - External Interrupt Sense Control 0 Bits - [1:0] - - true - - ISC0read-writeLOWThe low level of INTx generates an interrupt request0TOGGLEAny logical change on INTx generates an interrupt request1FALLINGThe falling edge of INTx generates an interrupt request2RISINGThe rising edge of INTx generates an interrupt request3 - - - ISC1 - External Interrupt Sense Control 1 Bits - [3:2] - - true - - - - - - - EIFR - External Interrupt Flag Register - 0x1 - read-only - - - INTF - External Interrupt Flags - [1:0] - - - 0 - 3 - - - - - - - EIMSK - External Interrupt Mask Register - 0x2 - - - INT - External Interrupt Request 1 Enable - [1:0] - - - 0 - 3 - - - - - - - PCICR - Pin Change Interrupt Control Register - 0x2D - - - PCIE - <TBD> - [3:0] - - - 0 - 15 - - - - - - - PCIFR - Pin Change Interrupt Flag Register - 0x0 - read-only - - - PCIF - Pin Change Interrupt Flags - [3:0] - - - 0 - 15 - - - - - - - PCMSK0 - Pin Change Mask Register 0 - 0x30 - - - PCINT - Pin Change Enable Masks - [7:0] - - - 0 - 255 - - - - - - - PCMSK1 - Pin Change Mask Register 1 - 0x31 - - - PCINT - Pin Change Enable Masks - [7:0] - - - 0 - 255 - - - - - - - PCMSK2 - Pin Change Mask Register 2 - 0x32 - - - PCINT - Pin Change Enable Masks - [7:0] - - - 0 - 255 - - - - - - - PCMSK3 - Pin Change Mask Register 3 - 0x2F - - - PCINT - Pin Change Enable Masks - [3:0] - - - 0 - 15 - - - - - - - - - FUSE - Fuses - 0x0 - - - EXTENDED - <TBD> - 0x2 - - - SELFPRGEN - Self Programming enable - [0:0] - - - - - HIGH - <TBD> - 0x1 - - - BODLEVEL - Brown-out Detector trigger level - [2:0] - - true - - - - 4V3 - Brown-out detection at VCC=4.3 V - 4 - - - 2V7 - Brown-out detection at VCC=2.7 V - 5 - - - 1V8 - Brown-out detection at VCC=1.8 V - 6 - - - DISABLED - Brown-out detection disabled - 7 - - - - - EESAVE - Preserve EEPROM through the Chip Erase cycle - [3:3] - - - WDTON - Watch-dog Timer always on - [4:4] - - - SPIEN - Serial program downloading (SPI) enabled - [5:5] - - - DWEN - Debug Wire enable - [6:6] - - - RSTDISBL - Reset Disabled (Enable PC6 as i/o pin) - [7:7] - - - - - LOW - <TBD> - 0x0 - - - SUT_CKSEL - Select Clock Source - [5:0] - - true - - - - EXTCLK_6CK_14CK_0MS - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 12 - - - INTRCOSC_8MHZ_6CK_14CK_0MS - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 14 - - - INTRCOSC_128KHZ_6CK_14CK_0MS - Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms - 15 - - - EXTCLK_6CK_14CK_4MS1 - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - 28 - - - INTRCOSC_8MHZ_6CK_14CK_4MS1 - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - 30 - - - INTRCOSC_128KHZ_6CK_14CK_4MS1 - Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms - 31 - - - EXTCLK_6CK_14CK_65MS - Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms - 44 - - - INTRCOSC_8MHZ_6CK_14CK_65MS_DEFAULT - Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; default value - 46 - - - INTRCOSC_128KHZ_6CK_14CK_65MS - Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms - 47 - - - - - CKOUT - Clock output on PORTB0 - [6:6] - - - CKDIV8 - Divide clock by 8 internally - [7:7] - - - - - - - LOCKBIT - Lockbits - 0x0 - - - LOCKBIT - <TBD> - 0x0 - - - LB - Memory Lock - [1:0] - - true - - - - PROG_VER_DISABLED - Further programming and verification disabled - 0 - - - PROG_DISABLED - Further programming disabled - 2 - - - NO_LOCK - No memory lock features enabled - 3 - - - - - - - - - PORTA - I/O Port - 0x2C - - - DDRA - Port A Data Direction Register - 0x1 - read-write - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - - - PINA - Port A Input Pins - 0x0 - read-write - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - - - PORTA - Port A Data Register - 0x2 - read-write - - - PA0 - Pin A0 - [0:0] - - - PA1 - Pin A1 - [1:1] - - - PA2 - Pin A2 - [2:2] - - - PA3 - Pin A3 - [3:3] - - - - - - - PORTB - I/O Port - 0x23 - - - DDRB - Port B Data Direction Register - 0x1 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PINB - Port B Input Pins - 0x0 - read-write - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - PORTB - Port B Data Register - 0x2 - - - PB0 - Pin B0 - [0:0] - - - PB1 - Pin B1 - [1:1] - - - PB2 - Pin B2 - [2:2] - - - PB3 - Pin B3 - [3:3] - - - PB4 - Pin B4 - [4:4] - - - PB5 - Pin B5 - [5:5] - - - PB6 - Pin B6 - [6:6] - - - PB7 - Pin B7 - [7:7] - - - - - - - PORTC - I/O Port - 0x26 - - - DDRC - Port C Data Direction Register - 0x1 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - PINC - Port C Input Pins - 0x0 - read-write - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - PORTC - Port C Data Register - 0x2 - - - PC0 - Pin C0 - [0:0] - - - PC1 - Pin C1 - [1:1] - - - PC2 - Pin C2 - [2:2] - - - PC3 - Pin C3 - [3:3] - - - PC4 - Pin C4 - [4:4] - - - PC5 - Pin C5 - [5:5] - - - PC6 - Pin C6 - [6:6] - - - PC7 - Pin C7 - [7:7] - - - - - - - PORTD - I/O Port - 0x29 - - - DDRD - Port D Data Direction Register - 0x1 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PIND - Port D Input Pins - 0x0 - read-write - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - PORTD - Port D Data Register - 0x2 - - - PD0 - Pin D0 - [0:0] - - - PD1 - Pin D1 - [1:1] - - - PD2 - Pin D2 - [2:2] - - - PD3 - Pin D3 - [3:3] - - - PD4 - Pin D4 - [4:4] - - - PD5 - Pin D5 - [5:5] - - - PD6 - Pin D6 - [6:6] - - - PD7 - Pin D7 - [7:7] - - - - - - - SPI - Serial Peripheral Interface - 0x4C - - - SPCR - SPI Control Register - 0x0 - - - SPR - SPI Clock Rate Selects - [1:0] - - true - - SPRread-writeFOSC_4_2Fosc/4 if SPI2X == 0 else Fosc/20FOSC_16_8Fosc/16 if SPI2X == 0 else Fosc/81FOSC_64_32Fosc/64 if SPI2X == 0 else Fosc/322FOSC_128_64Fosc/128 if SPI2X == 0 else Fosc/643 - - - CPHA - Clock Phase - [2:2] - - - CPOL - Clock polarity - [3:3] - - - MSTR - Master/Slave Select - [4:4] - - - DORD - Data Order - [5:5] - - - SPE - SPI Enable - [6:6] - - - SPIE - SPI Interrupt Enable - [7:7] - - - - - SPDR - SPI Data Register - 0x2 - - - 0 - 255 - - - - - SPSR - SPI Status Register - 0x1 - read-write - - - SPI2X - Double SPI Speed Bit - [0:0] - read-write - - WCOL - Write Collision Flag - [6:6] - read-only - - SPIF - SPI Interrupt Flag - [7:7] - read-only - - - - - - TC0 - Timer/Counter, 8-bit - 0x35 - - - GTCCR - General Timer/Counter Control Register - 0xE - - - PSRSYNC - Prescaler Reset Timer/Counter1 and Timer/Counter0 - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - OCR0A - Timer/Counter0 Output Compare Register - 0x12 - - - 0 - 255 - - - - - OCR0B - Timer/Counter0 Output Compare Register - 0x13 - - - 0 - 255 - - - - - TCCR0A - Timer/Counter Control Register A - 0x10 - - - CS0 - Clock Select - [2:0] - - true - - CS0read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - CTC0 - Clear Timer on Compare Match - [3:3] - - - - - TCNT0 - Timer/Counter0 - 0x11 - - - 0 - 255 - - - - - TIFR0 - Timer/Counter0 Interrupt Flag register - 0x0 - read-only - - - TOV0 - Timer/Counter0 Overflow Flag - [0:0] - - - OCF0A - Timer/Counter0 Output Compare Flag 0A - [1:1] - - - OCF0B - Timer/Counter0 Output Compare Flag 0B - [2:2] - - - - - TIMSK0 - Timer/Counter0 Interrupt Mask Register - 0x39 - - - TOIE0 - Timer/Counter0 Overflow Interrupt Enable - [0:0] - - - OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable - [1:1] - - - OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable - [2:2] - - - - - - - TC1 - Timer/Counter1, 16-bit, PWM - 0x36 - - - GTCCR - General Timer/Counter Control Register - 0xD - - - PSRSYNC - Prescaler Reset Timer/Counter1 and Timer/Counter0 - [0:0] - - - TSM - Timer/Counter Synchronization Mode - [7:7] - - - - - ICR1 - Timer/Counter1 Input Capture Register Bytes - 0x50 - 16 - - - 0 - 65535 - - - - - OCR1A - Timer/Counter1 Output Compare Register Bytes - 0x52 - 16 - - - 0 - 65535 - - - - - OCR1B - Timer/Counter1 Output Compare Register Bytes - 0x54 - 16 - - - 0 - 65535 - - - - - TCCR1A - Timer/Counter1 Control Register A - 0x4A - - - WGM1 - Waveform Generation Mode - [1:0] - - - 0 - 3 - - - - - COM1B - Compare Output Mode 1B, bits - [5:4] - - true - COM1Bread-writeDISCONNECTEDNormal port operation, OCix disconnected0MATCH_TOGGLEToggle OCix on Compare Match (Might depend on WGM)1MATCH_CLEARClear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)2MATCH_SETSet OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)3 - - - COM1A - Compare Output Mode 1A, bits - [7:6] - - true - - - - - - TCCR1B - Timer/Counter1 Control Register B - 0x4B - - - CS1 - Prescaler source of Timer/Counter 1 - [2:0] - - true - CS1read-writeNO_CLOCKNo clock source (Timer/Counter stopped)0DIRECTRunning, No Prescaling1PRESCALE_8Running, CLK/82PRESCALE_64Running, CLK/643PRESCALE_256Running, CLK/2564PRESCALE_1024Running, CLK/10245EXT_FALLINGRunning, ExtClk Tx Falling Edge6EXT_RISINGRunning, ExtClk Tx Rising Edge7 - - - WGM1 - Waveform Generation Mode - [4:3] - - - 0 - 3 - - - - - ICES1 - Input Capture 1 Edge Select - [6:6] - - - ICNC1 - Input Capture 1 Noise Canceler - [7:7] - - - - - TCCR1C - Timer/Counter1 Control Register C - 0x4C - - - FOC1B - <TBD> - [6:6] - write-only - - FOC1A - <TBD> - [7:7] - write-only - - - - TCNT1 - Timer/Counter1 Bytes - 0x4E - 16 - - - 0 - 65535 - - - - - TIFR1 - Timer/Counter Interrupt Flag register - 0x0 - read-write - - - TOV1 - Timer/Counter1 Overflow Flag - [0:0] - - - OCF1A - Output Compare Flag 1A - [1:1] - - - OCF1B - Output Compare Flag 1B - [2:2] - - - ICF1 - Input Capture Flag 1 - [5:5] - - - - - TIMSK1 - Timer/Counter Interrupt Mask Register - 0x39 - - - TOIE1 - Timer/Counter1 Overflow Interrupt Enable - [0:0] - - - OCIE1A - Timer/Counter1 Output CompareA Match Interrupt Enable - [1:1] - - - OCIE1B - Timer/Counter1 Output CompareB Match Interrupt Enable - [2:2] - - - ICIE1 - Timer/Counter1 Input Capture Interrupt Enable - [5:5] - - - - - - - TWI - Two Wire Serial Interface - 0xB8 - - - TWAMR - TWI (Slave) Address Mask Register - 0x5 - - - TWAM - TWI (Slave) Address Mask Bits - [7:1] - - - 0 - 127 - - - - - - - TWAR - TWI (Slave) Address register - 0x2 - - - TWGCE - TWI General Call Recognition Enable Bit - [0:0] - - - TWA - TWI (Slave) Address register Bits - [7:1] - - - 0 - 127 - - - - - - - TWBR - TWI Bit Rate register - 0x0 - - - 0 - 255 - - - - - TWCR - TWI Control Register - 0x4 - read-write - - TWIE - TWI Interrupt Enable - [0:0] - - - TWEN - TWI Enable Bit - [2:2] - - - TWWC - TWI Write Collition Flag - [3:3] - read-only - - TWSTO - TWI Stop Condition Bit - [4:4] - - - TWSTA - TWI Start Condition Bit - [5:5] - - - TWEA - TWI Enable Acknowledge Bit - [6:6] - - - TWINT - TWI Interrupt Flag - [7:7] - - - - - TWDR - TWI Data register - 0x3 - - - 0 - 255 - - - - - TWHSR - TWHSR - 0x6 - - - TWHS - <TBD> - [0:0] - - - - - TWSR - TWI Status Register - 0x1 - - - TWPS - TWI Prescaler - [1:0] - - true - - TWPSread-writePRESCALER_1Prescaler Value 10PRESCALER_4Prescaler Value 41PRESCALER_16Prescaler Value 162PRESCALER_64Prescaler Value 643 - - - TWS - TWI Status - [7:3] - read-only - - 0 - 31 - - - - - - - - - WDT - Watchdog Timer - 0x60 - - - WDTCSR - Watchdog Timer Control Register - 0x0 - read-write - - - WDE - Watch Dog Enable - [3:3] - - - WDCE - Watchdog Change Enable - [4:4] - - - WDIE - Watchdog Timeout Interrupt Enable - [6:6] - - - WDIF - Watchdog Timeout Interrupt Flag - [7:7] - - WDPLWatchdog Timer Prescaler - Low Bits[2:0]WDPLread-writeCYCLES_2K_512K- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set0CYCLES_4K_1024K- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set1CYCLES_8K- 8192 cycles, ~64ms2CYCLES_16K- 16K (16384) cycles, ~0.125s3CYCLES_32K- 32K (32768) cycles, ~0.25s4CYCLES_64K- 64K (65536) cycles, ~0.5s5CYCLES_128K- 128K (131072) cycles, ~1s6CYCLES_256K- 256K (262144) cycles, ~2s7 - - WDPHWatchdog Timer Prescaler - High Bit[5:5] - - - - - - \ No newline at end of file From bfc1433bf7961b4e7b30b9828c2ed64729c6462f Mon Sep 17 00:00:00 2001 From: unknown Date: Tue, 1 Nov 2022 12:47:34 +0100 Subject: [PATCH 11/11] Correct whitespace --- boards/move38_blink.json | 2 +- boards/move38_blink328.json | 2 +- boards/move38_blinkmax.json | 2 +- boards/move38_blinknfc.json | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/boards/move38_blink.json b/boards/move38_blink.json index af813bc..728cb9a 100644 --- a/boards/move38_blink.json +++ b/boards/move38_blink.json @@ -35,4 +35,4 @@ }, "url": "https://move38.com/", "vendor": "Move38" -} \ No newline at end of file +} diff --git a/boards/move38_blink328.json b/boards/move38_blink328.json index f6ee229..cd00476 100644 --- a/boards/move38_blink328.json +++ b/boards/move38_blink328.json @@ -35,4 +35,4 @@ }, "url": "https://move38.com/", "vendor": "Move38" -} \ No newline at end of file +} diff --git a/boards/move38_blinkmax.json b/boards/move38_blinkmax.json index 360042c..4c678a1 100644 --- a/boards/move38_blinkmax.json +++ b/boards/move38_blinkmax.json @@ -35,4 +35,4 @@ }, "url": "https://move38.com/", "vendor": "Move38" -} \ No newline at end of file +} diff --git a/boards/move38_blinknfc.json b/boards/move38_blinknfc.json index 8f26fc8..8893667 100644 --- a/boards/move38_blinknfc.json +++ b/boards/move38_blinknfc.json @@ -35,4 +35,4 @@ }, "url": "https://move38.com/", "vendor": "Move38" -} \ No newline at end of file +}