TileAndFuse padding enablement feature enhancements

[jerryyin]

1. Per @nirvedhmeshram 's TODO in

   iree/compiler/src/iree/compiler/Codegen/Dialect/GPU/TargetUtils/ConfigUtils.cpp

   Line 246 in 1586d53

   // TODO (nirvedhmeshram, jerryyin): Support all GEMM types.

   
   

   iree/compiler/src/iree/compiler/Codegen/Dialect/GPU/TargetUtils/ConfigUtils.cpp

   Line 252 in 1586d53

   if (!schedule && !contractionDims.batch.empty() && !hasFusedLeadingOp) {

There are two sub tasks in the feature:

• Aiming at Relax or remove the contractionDims.batch.empty() condition
• add one additional test case for linalg.matmul to compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse.mlir, and config_tile_and_fuse.mlir make sure they can be lowered correctly

2. Per @nirvedhmeshram 's TODO in

   iree/compiler/src/iree/compiler/Codegen/Dialect/GPU/TargetUtils/ConfigUtils.cpp

   Lines 333 to 335 in 1586d53

   	// TODO (nirvedhmeshram, jerryyin) : When using c promotion the heurestics
   	// used during finding a schedule need to be updated to account for the
   	// extra shared memory for the result.

In condition such as when doCPromotion = !mustBeAligned for now, make sure the MMA schedule take the additional allocation from gemmC into account and populate valid gemm schedules. Essentially formalize the condition of 932b39b into a PR. In the future, we can turn doCPromotion as a tuning variable to explore whether with C promotion can benefit gemm performance overall.