Rp2040 Systick Interrupt

[ncalbrecht]

Hi All,

first up thank you for the development of the amazing grblHAL Projekt and all the work involved!
I have a question regarding the Systick Timer interrupt on the RP2040.
In Line 1929 of driver.c a Systick Interrupt Handler is used to generate a 1ms timebase:

RP2040/driver.c

Line 1929 in 5cc6e78

void isr_systick (void)

The Systick is configured to a 1ms rate:

RP2040/driver.c

Line 1588 in 5cc6e78

systick_hw->rvr = 999;

So this makes sense, however, I can't see where the interrupt handler is registered. Additionally, if I understood the datasheet correctly, the RP2040 doesn't even have a Systick interrupt.
So how does this work? Is there a special SDK trick, or am I missing something?

[terjeio]

I can't see where the interrupt handler is registered.

Can't remember where it is found now but it is likely defined as a weak symbol in the vector table definition. By just adding it to driver.c the weak definition is overridden.

Additionally, if I understood the datasheet correctly, the RP2040 doesn't even have a Systick interrupt.

AFAIK all (or almost all?) ARM processors has a systick timer, usually reserved for OS use. I regard grblHAL as an OS (when not running under a RTOS) so I claim the systick timer and the corresponding interrupt. And the RP2040 definitely has one (or two - I believe one for each core), although somewhat hidden away.

[ncalbrecht]

Thanks, I've missed that, the handler is defined as a weak symbol in:
https://github.com/raspberrypi/pico-sdk/blob/2062372d203b372849d573f252cf7c6dc2800c0a/src/rp2_common/pico_standard_link/crt0.S#L101

And you are right, both cores have an individual Systick timer.
The SDK also provides a nice method for registering a Handler for each core.
https://github.com/raspberrypi/pico-sdk/blob/2062372d203b372849d573f252cf7c6dc2800c0a/src/rp2_common/hardware_exception/exception.c#L44
However, I think if you want to use both you probably need some modifications because the default core1 startup code uses the same vector table for both cores and therefore can't have individual handlers.