Skip to content
This repository has been archived by the owner on Jan 10, 2023. It is now read-only.

Check the verilog simulation files work #11

Open
5 tasks
mithro opened this issue May 5, 2021 · 0 comments
Open
5 tasks

Check the verilog simulation files work #11

mithro opened this issue May 5, 2021 · 0 comments
Labels
sky130_*_sc CI related to the standard cell libraries.

Comments

@mithro
Copy link
Contributor

mithro commented May 5, 2021

  • Check with USE_POWER_PINS enabled.
  • Check with USE_POWER_PINS disable.
  • Functional vs Behavioral models?
  • Run the XXX.tb.v files?
  • Check for syntax errors using iverilog (-Wall)
@mithro mithro added the sky130_*_sc CI related to the standard cell libraries. label May 5, 2021
Sign up for free to subscribe to this conversation on GitHub. Already have an account? Sign in.
Assignees
No one assigned
Labels
sky130_*_sc CI related to the standard cell libraries.
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@mithro