10 MHz (or any similar integer frequency) to 1PPS pulse divider

[SimonMerrett]

Implemented on ATtiny3227, sharing the code at the point I got it working. I wanted to get a 1PPS signal from a 10 MHz external clock reference. But I also wanted to be able to get 1PPS from 9,999,999 Hz etc. Seems to work although it needs proper testing. Please flag any concerns in comments below:

/* TC timer and CCL external clock divider
    Use TCA without prescaler to drive TCB1 as the MSB counter and TCB0 single-shot
    as LSB counter, to generate 1PPS from 10 MHz input clock
    Avoids issue of prescaled TCA0 clock input not resetting to 0
    Uses full length PER/CCMP values for 1 second timings (comment out #define TEST).
    Successful in making a long (6.5 ms) output pulse on a pin using CCL
    Input to output pulse propagation delay is in the order of 50 ns

              P P P P P P
              A A C C C C
              1 0 5 4 3 2
              | | | | | |
              o_o_o_o_o_o
       PA2 -o|           |o- PC1
       PA3 -o|  ATtiny   |o- PC0
       GND -o|           |o- PB0
       VDD -o|  x27      |o- PB1
       PA4 -o|           |o- PB2
       PA5 -o|___________|o- PB3
              o o o o o o
              | | | | | |
              P P P P P P
              A A B B B B
              6 7 7 6 5 4
*/
#include <Logic.h>

//#define TEST // macro implements shortened periods to see whole process on scope

#ifdef TEST
constexpr uint16_t tca0_per = 0x07;
constexpr uint16_t tcb0_ccmp = 0x01;
constexpr uint16_t tcb1_ccmp = 0x03;
#else
constexpr uint16_t tca0_per = 0xFFFF;
constexpr uint16_t tcb0_ccmp = 0x9679; // LSBs for 1/10 million are 0x967F but the TCA/TCBn events and LUT chain cause 6 cycles of delay
constexpr uint16_t tcb1_ccmp = 0x98;
#endif // TEST

void setup() {
  EventSys_init();
  // EventSys_init() needs to be called before CCL_init()
  CCL_init();
  TCB0_LSB_init();
  TCA0_prescale_init();
  TCB1_MSB_init();
  pins_init();
}

void loop() {
  // nothing needed in loop()
}

void EventSys_init(void)
{
  /* Set up generators */
  EVSYS.CHANNEL0 = EVSYS_CHANNEL0_TCA0_OVF_LUNF_gc; // set up channel 0 generator to be TCA0 overflow
  EVSYS.CHANNEL1 = EVSYS_CHANNEL1_CCL_LUT3_gc;      // set up channel 1 generator to be the level of LUT3
  EVSYS.CHANNEL2 = EVSYS_CHANNEL2_PORTA_PIN5_gc;    // set up channel 2 generator to be TCB0 waveform out
  EVSYS.CHANNEL3 = EVSYS_CHANNEL3_TCB1_CAPT_gc;     // set up channel 3 generator to be TCB1 compare match (capture)
  EVSYS.CHANNEL4 = EVSYS_CHANNEL4_TCB0_CAPT_gc;     // set up channel 4 generator to be TCB0 compare match (capture)

  /* Set up users */
  EVSYS.USERTCB0CAPT = EVSYS_USER_CHANNEL3_gc;      // TCB0 triggers start counting off TCB1 CCMP match
  EVSYS.USERTCB1COUNT = EVSYS_USER_CHANNEL0_gc;     // TCB1 triggers start counting off TCA0 PER overflows
  EVSYS.USERTCA0CNTB = EVSYS_USER_CHANNEL2_gc;      // TCA0 resets while TCB0 waveform out is high

  EVSYS.USERCCLLUT3A = EVSYS_USER_CHANNEL1_gc;      // LUT3 feedback is itself
  EVSYS.USERCCLLUT3B = EVSYS_USER_CHANNEL0_gc;      // LUT3 RESET is TCA0 PER overflow

#ifdef TEST
  EVSYS.USEREVSYSEVOUTA = EVSYS_USER_CHANNEL0_gc;   // route the TCA0 overflow event to PA7 for testing
#endif // TEST
  EVSYS.USEREVSYSEVOUTC = EVSYS_USER_CHANNEL4_gc;   // route the TCB0 match event to PC2 (LUT3 IN2) - no need for external wiring
}

void CCL_init(void)
{
  /*
                                              3-input     truth table:
    We use CCL LUT event as our "feedback",   |IN2|EvB|EvA| Y |
    routed to Event A.                        |---|---|---|---|
    Event B is RESET and IN2 is SET,          | 0 | 0 | 0 | 0 |
    via EVOUTC pin.                           | 0 | 0 | 1 | 1 |
    Both active HIGH.                         | 0 | 1 | 0 | 0 |
                                              | 0 | 1 | 1 | 0 |
                                              | 1 | 0 | 0 | 1 |
                                              | 1 | 0 | 1 | 1 |
                                              | 1 | 1 | 0 | 0 |
                                              | 1 | 1 | 1 | 1 |
  */
  Logic3.enable = true;               // Enable logic block 3
  Logic3.input0 = in::event_a;        // Use event 0 as input 0 feedback
  Logic3.input1 = in::event_b;        // Use event 1 as input 1 (RESET)
  Logic3.input2 = in::input;          // EVOUTC pin as input 2 (SET)
  Logic3.output = out::enable;        // Enable logic block 3 output pin
  Logic3.filter = filter::disable;    // No output filter enabled
  Logic3.truth = 0xB2;                // Set truth table - SET/RESET active HIGH with feedback

  // Initialize logic block 3
  Logic3.init();

  // Start the AVR logic hardware
  Logic::start();
}

void TCA0_prescale_init(void)
{
  takeOverTCA0();                                   // This replaces disabling and resettng the timer, required previously.
  TCA0.SINGLE.CTRLB = TCA_SINGLE_WGMODE_NORMAL_gc;  //Single slope PWM mode OVF interrupt at BOTTOM, PWM on WO0
  TCA0.SINGLE.PER = tca0_per;                       // Test small count to verify, will be 0xFFFF for 16 bit prescale function
  TCA0.SINGLE.EVCTRL = TCA_SINGLE_EVACTB_RESTART_HIGHLVL_gc | TCA_SINGLE_CNTBEI_bm; // results in a 2 clock cycle delay to the start of the counter after reset event level goes low
  TCA0.SINGLE.CTRLA = TCA_SINGLE_ENABLE_bm;         // No prescaler, as TCA0 is used as a resettable prescaler itself
}

void TCB0_LSB_init (void)
{
  TCB0.CCMP = tcb0_ccmp;                            /* Compare */
  TCB0.CNT = tcb0_ccmp;                             /* We don't want the single shot to fire straight away, so we set this equal to TCB0.CCMP */
  TCB0.CTRLB =  TCB_ASYNC_bm                        /* Asynchronous Enable: enabled. May not be necessary as pulse end time is the same*/
                | TCB_CCMPEN_bm                     /* Waveform Output: enabled */
                | TCB_CNTMODE_SINGLE_gc;            /* Single Shot */
  TCB0.EVCTRL = 1 << TCB_CAPTEI_bp                  /* Event Input Enable: enabled, to start counter running. */
                | 0 << TCB_EDGE_bp                  /* Event Edge: disabled. We only want one input edge to trigger a pulse */
                | 0 << TCB_FILTER_bp;               /* Input Capture Noise Cancellation Filter: disabled */
  TCB0.CTRLA = TCB_CLKSEL_CLKDIV1_gc                /* CLK_PER (no prescaler) */
               | 1 << TCB_ENABLE_bp ;               /* Enable: enabled. Turn the timer on! */
}

void TCB1_MSB_init(void)
{
  TCB1.CCMP = tcb1_ccmp;                            /* Compare */
  TCB1.EVCTRL = 1 << TCB_CAPTEI_bp                  /* Event Input Enable: enabled, as count input. */
                | 0 << TCB_EDGE_bp                  /* Event Edge: disabled. We only want one input edge to trigger a pulse */
                | 0 << TCB_FILTER_bp;               /* Input Capture Noise Cancellation Filter: disabled */
  TCB1.CTRLA = TCB_CLKSEL_EVENT_gc                  /* Use the assigned Event channel (0 in this case, from TCA0 PER overflow) as input */
               | 1 << TCB_ENABLE_bp;                /* Enable: enabled. Turn the timer on! */
}

void pins_init(void)
{
  PORTC.DIRSET |= PIN2_bm;                          // EVOUTC for LUT IN2 latch SET
  PORTA.DIRSET |= PIN5_bm                           // TCB0 WO for TCA0 reset scheme
                  | PIN7_bm;                        // EVOUTA Alt for test
  PORTA.PIN5CTRL = PORT_ISC_INTDISABLE_gc;          // set input register, to get level event for TCA0 reset scheme
  PORTMUX.EVSYSROUTEA = PORTMUX_EVOUTA_ALT1_gc;     // Output on PA7
}

[mosqu-ito]

That's really good, Simon. I confess, I barely had my toes in the pool last time I was trying to follow your 10MHz endeavour (felt like maybe I'd forgotten my reading glasses). So three's the charm, huh (three counters)? If I'm following better this time, your big count is broken into two factors and a remainder, with allowances for the known delays? And it's all neatly "wired" together with channels. I see an odd-lut implemented RS via channel 1. The only thing I still can't quite wrap my head around is how exactly the RS fits into the overall counter; I have no doubt it's a stuck cog in my old noggin. My stuck cog aside, I think it's great! It will be very instructive for me as I attempt to get my toes in a little deeper.

[mosqu-ito]

And TCB0match is the Set via channel 4.
So you kinda take what you get for a pulse width, or is there something more elegant happening that I'm not seeing? Maybe Lut2 with an edge detector (shorties?) or Lut0 with a sequencer (fifty/fifties)? Maybe I'm just making myself annoying now? :D

[SimonMerrett]

Yes, this example is a "good enough" take what you get. Because I'm recycling the TCA0 (prescaler task) period to be that of the output pulse. But that's because I didn't want to make things more complicated and I can live with the 6 ms or so pulse width I get. I also wanted to try for a hardware-only version, so that I didn't need to bother servicing interrupts etc (the height of laziness!). But you could absolutely use software counters, RTC PIT etc to extend your pulse duration to something more up your street.

[mosqu-ito]

Edge detector, sequencer, not hardware? Either one, just appended to what you have there already?
(gonna need to double up my tinfoil tonight) :D

[SimonMerrett]

I'm not sure what you are aiming for (is it still a more configurable pulse duty?) and how the edge detector/sequencer would achieve it. I'm a noob when it comes to combinatorial logic so would genuinely be enlightened if you could elaborate. Although I don't know the impact, I am aiming for minimal propagation delay between the input signal and output rising edge. I'm not sure if adding in further CCL stages would add to that propagation delay (I would guess it would). But that's just a preference of mine and doesn't mean your idea wouldn't add greater functionality. I have observed a pretty stable (low apparent jitter) offset between input and output pulse edges, so it is possible to account for the propagation delay. One may even be able to use further LUTs / events to act as delay line elements and bring the output edges into sync with a subsequent input pulse but that's all dependent on your input frequency.

[mosqu-ito]

Hi Simon. Sorry I was needling you there, you know your requirements better than I do. I just like pretty waveforms, either 50/50 or neat little blips. :D Rather than mess with your baby, I've made a demo for using a JK sequencer as a toggler (which always makes your output 50/50). I was just about to post it when I noticed you here, I shall do so now...