2 series 32 bit timer - will it "event" at a 32 bit compare value?

[SimonMerrett]

I have the ATtiny3227 in front of me and am looking at the datasheet about how to use both the TCBs chained together as a 32 bit counter. I am keen for fast responses, so I like the sound of this. However, from reading about the way it works, I'm not sure I can get an event to be generated at any arbitrary 32 bit number.

For example, it says to configure thus:

22.3.3.3 32-Bit Input Capture
Two 16-bit Timer/Counter Type B (TCBn) can be combined to work as a true 32-bit input capture:
One TCB is counting the two LSBs. Once this counter reaches MAX, an overflow (OVF) event is generated, and the
counter wraps around. The second TCB is configured to count these OVF events and thus provides the two MSBs.
The 32-bit counter value is concatenated from the two counter values.
To function as a 32-bit counter, the two TCBs and the system have to be set up as described in the following
paragraphs.
System Configuration
• Configure a source (TCA, events, CLK_PER) for the count input for the LSB TCB, according to the application
requirements
• Configure the event system to route the OVF events from the LSB TCB (event generator) to the MSB TCB
(event user)
• Configure the event system to route the same capture event (CAPT) generator to both TCBs
Configuration of the LSB Counter
• Select the configured count input by writing the Clock Select (CLKSEL) bit field in the Control A (CTRLA)
register
• Write the Timer Mode (CNTMODE) bit field in the Control B (CTRLB) register to select one of the Input Capture
modes
• The Cascade Two Timer/Counters (CASCADE) bit in CTRLA must be ‘0’
Configuration of the MSB Counter
• Enable the 32-bit mode by writing the Cascade Two Timer/Counters bit (CASCADE) in CTRLA to ‘1’
• Select events as clock input by writing to the Clock Select (CLKSEL) bit field in the Control A (CTRLA) register
• Write the Timer Mode (CNTMODE) bit field in the Control B (CTRLB) register to select the same Input Capture
mode as the LSB TCB

and the example is given:

Capturing a 32-Bit Counter Value
To acquire a 32-bit counter value, send a CAPT event to both TCBs. Both TCBs are running in the same capture
mode, so each will capture the current counter value (CNT) in the respective Capture/Compare (CCMP) register. The
32-bit capture value is formed by concatenating the two CCMP registers.

But although the event system appears to be the glue holding two 16 bit timers together, there is no apparent way to respond quickly to the 32 bit compare value that you want, right? In fact, they only allow you to use an external event to copy the CNT values into the CCMP registers for you to read at your leisure?

Is there any way to trigger an event at an arbitrary 32 bit count without CCL?

[mosqu-ito]

Does it have to be an all-hardware solution? Could the high order counter fire an "almost there" event which reconfigures the low order counter to fire "the event" a short time later?

[SimonMerrett]

It's a possibility. As well as counting every pulse (at around 10 MHz) I'm aiming for minimal propagation time from when the final pulse arrives to when the output pin rises.

Before, I was thinking there would need to be an event on both the low order timer CCMP and OVF, with the OVF event feeding the high order timer. The high order timer CCMP and the low order CCMP would be set for the desired value and fed into a LUT, although I haven't checked that's possible. When both events are high, the logic cell fires the pin.

Your question has made me think about using three timers, with one in single shot mode that begins when the high order timer reaches its final value.

But if they had made the effort to let it do 32 bit counting, it's a shame they didn't make it more usable.

Further thoughts and ideas most welcome!

[mosqu-ito]

Are you concerned that the last leg (handled solely by the low order counter) might be very small (zero even) thus causing the final event to be considerably delayed? How about a three event chain?
Decrement the high order target so that instead of having 0 to 65535 counts to go we instead have 65536 to 131071 counts to go. Split that into two counts no smaller than 32768. Now the final count can't occur anywhere near it's setup.
If there's a way to do a native 32 bit target the datasheet doesn't make it obvious.
CCL seems pretty well documented though, enough to set up some experiments. Are you dead set on avoiding it?

[mosqu-ito]

Upon reflection I can see why you might not want to re-use active counters if you're aiming to keep up with 10 MHz.

[SimonMerrett]

I tried my idea for the first part of the CCL approach but it didn't work. I was planning to generate an event at CCMP and OVF on the low order timer. However, in periodic interrupt mode, it will only generate one of those. But it gave me the idea that perhaps 8 bit pwm mode on the low order timer could enable a 24 bit counter, which should be suitable for my needs, although CCL will still be needed.