From be51c070c0aeabc7f03aa27a230da78c0e635e80 Mon Sep 17 00:00:00 2001 From: Tilen Majerle Date: Mon, 30 Nov 2020 15:46:56 +0100 Subject: [PATCH 01/17] Create FUNDING.yml --- .github/FUNDING.yml | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 .github/FUNDING.yml diff --git a/.github/FUNDING.yml b/.github/FUNDING.yml new file mode 100644 index 0000000..77b3607 --- /dev/null +++ b/.github/FUNDING.yml @@ -0,0 +1,3 @@ +# These are supported funding model platforms + +custom: ['paypal.me/tilz0R'] From 830f9a40e5ad702d9382b4b9e98da3a11ea0bb3c Mon Sep 17 00:00:00 2001 From: Tilen Majerle Date: Mon, 30 Nov 2020 16:00:51 +0100 Subject: [PATCH 02/17] Add option to ignore user apps with uncommented macro --- lwow/src/include/lwow/lwow_opt.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lwow/src/include/lwow/lwow_opt.h b/lwow/src/include/lwow/lwow_opt.h index ea2e7a7..548a20d 100644 --- a/lwow/src/include/lwow/lwow_opt.h +++ b/lwow/src/include/lwow/lwow_opt.h @@ -34,6 +34,9 @@ #ifndef LWOW_HDR_OPT_H #define LWOW_HDR_OPT_H +/* Uncomment to ignore user options (or set macro in compiler flags) */ +/* #define LWOW_IGNORE_USER_OPTS */ + /* Include application options */ #ifndef LWOW_IGNORE_USER_OPTS #include "lwow_opts.h" From b6c81fb045338e7e86943e654fccb80280d29a6f Mon Sep 17 00:00:00 2001 From: Tilen Majerle Date: Mon, 30 Nov 2020 21:21:05 +0100 Subject: [PATCH 03/17] Add donate button --- docs/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/index.rst b/docs/index.rst index 49dc386..a28bf69 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -12,7 +12,7 @@ Its primary focus is UART hardware for physical communication for sensors and ot .. rst-class:: center .. rst-class:: index_links - :ref:`download_library` :ref:`getting_started` `Open Github `_ + :ref:`download_library` :ref:`getting_started` `Open Github `_ `Donate `_ Features ^^^^^^^^ From 066626aa681c039dde85a00a989a76f75da0e795 Mon Sep 17 00:00:00 2001 From: Tilen Majerle Date: Sat, 5 Dec 2020 01:24:35 +0100 Subject: [PATCH 04/17] Add logo on all --- docs/index.rst | 3 +++ docs/static/images/logo | 1 - docs/static/images/logo.drawio | 1 + docs/static/images/logo.svg | 2 +- 4 files changed, 5 insertions(+), 2 deletions(-) delete mode 100644 docs/static/images/logo create mode 100644 docs/static/images/logo.drawio diff --git a/docs/index.rst b/docs/index.rst index a28bf69..8e06dee 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -6,6 +6,9 @@ Welcome to the documentation for version |version|. LwOW is lightweight, platform independent library for Onewire protocol for embedded systems. Its primary focus is UART hardware for physical communication for sensors and other slaves. +.. image:: static/images/logo.svg + :align: center + .. image:: static/images/logo.svg :align: center diff --git a/docs/static/images/logo b/docs/static/images/logo deleted file mode 100644 index f3aa1be..0000000 --- a/docs/static/images/logo +++ /dev/null @@ -1 +0,0 @@ -7Zhdb5swFIZ/DZedAANhl2uSdTeVKqXS1qvJwSdg1eDIMU2yXz8TbMD5aJIJ0UzqVTiv7WP8vCdHFg4a55sHgZfZIyfAHN8lGwdNHN/3XD9QP5WyrZUwRrWQCkr0pFaY0T9gVmq1pARW1kTJOZN0aYsJLwpIpKVhIfjanrbgzN51iVM4EGYJZofqT0pkVqtx6Lb6D6BpZnb2XD2SYzNZC6sME77uSGjqoLHgXNZP+WYMrIJnuNTrvp8YbV5MQCEvWeC+FM+T5ygry0fvdUoffpMxuTNp3jAr9Yn128qtQSB4WRCosngOul9nVMJsiZNqdK1MV1omc6aHV1Lw1waVOuT9gjI25oyLXTZEMMSLpJnZGYmSGOYLNaJfCYSEzcnDeg1CVXvAc5Biq6boBcjUjy47L9LxujXRSFnHP+Mr1mWTNplbsupBw70GtD846BBiEhwDHftzFEX9gPZHNujRR3N2h+a8iBNIjhb0PA4DddB+OKMbK+jwPGcoyLeqBauo4AW8x7WqRtuWOhuQg/Z8lliHSPgOEQEMS/pmpz+GSe/wxKna+LQhwR7pFS9FAnpVty/vJUKjM4kkFinIg0Q715pj/7uRUe9GKoPE9pcK3C+hCV/07F0wqY7uNtFWR7duOXL7snw/kT+s5aNPyy+1PDjRdq+2fD/RwP/yr5+WX9rYo54sP0g0sOXeBX/zq65C3YuPrhC7LFBPd504tMCZsOM/OuL/fhPt7arjxf8ryMAG6Y0+muQFbegmSSJ/MJIqbD8K1L2g/bSCpn8B \ No newline at end of file diff --git a/docs/static/images/logo.drawio b/docs/static/images/logo.drawio new file mode 100644 index 0000000..984051f --- /dev/null +++ b/docs/static/images/logo.drawio @@ -0,0 +1 @@ +jZLLboMwEEW/xstIgANNl02aPtRWXWSRqDsHT7AVg5HjFOjX19RjCIoiVfLCc2bGj3uH0FXZPhtWiw/NQZEk4i2hjyRJsiQh/Yp450GaUg8KI7lH8Qg28gcQRkjPksNpUmi1VlbWU5jrqoLcThgzRjfTsoNW01trVsAV2ORMXdOt5FZ4ukijkb+ALES4OY4wU7JQjOAkGNfNBaJrQldGa+t3ZbsC1WsXdPF9Tzeyw8MMVPY/DXz/8PU2n5ldd3e/Wyxnx/3ydYanfDN1xg+/N59bfLDtggpGnysO/UExoctGSAubmuV9tnG2OyZsqTB9skYfB7UyRw66smgt7eNBisgF+AIwFtqbX4sHwdyggS7Bms6VYAOdp74FhywJcTNaFmfog7iwK9jIcEqK4ehRSLdBLUM4evaXuxh8uv4F \ No newline at end of file diff --git a/docs/static/images/logo.svg b/docs/static/images/logo.svg index e99f469..562631a 100644 --- a/docs/static/images/logo.svg +++ b/docs/static/images/logo.svg @@ -1,3 +1,3 @@ - \ No newline at end of file +
LwOW
LwOW \ No newline at end of file From 1f7c1e805a9dad45ce7959bb578b348b87f3f89d Mon Sep 17 00:00:00 2001 From: Tilen Majerle Date: Sat, 5 Dec 2020 01:27:47 +0100 Subject: [PATCH 05/17] Add logo on all --- docs/index.rst | 3 --- 1 file changed, 3 deletions(-) diff --git a/docs/index.rst b/docs/index.rst index 8e06dee..a28bf69 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -6,9 +6,6 @@ Welcome to the documentation for version |version|. LwOW is lightweight, platform independent library for Onewire protocol for embedded systems. Its primary focus is UART hardware for physical communication for sensors and other slaves. -.. image:: static/images/logo.svg - :align: center - .. image:: static/images/logo.svg :align: center From 039c3c914b3d981122b1ef49d9ba4ab47afdc5c7 Mon Sep 17 00:00:00 2001 From: Tilen Majerle Date: Sat, 5 Dec 2020 08:58:16 +0100 Subject: [PATCH 06/17] Add v prefix in version --- docs/conf.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/conf.py b/docs/conf.py index 0497bd5..d444f8e 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -27,7 +27,7 @@ author = 'Tilen MAJERLE' # The full version, including alpha/beta/rc tags -version = '3.0.1' +version = 'v3.0.1' # Try to get branch at which this is running # and try to determine which version to display in sphinx From e7b917611088fcde6ea246ffdb6d6639aabd6360 Mon Sep 17 00:00:00 2001 From: Tilen Majerle Date: Sat, 12 Dec 2020 10:57:24 +0100 Subject: [PATCH 07/17] Generic docs update --- docs/conf.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/conf.py b/docs/conf.py index d444f8e..bf526f3 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -112,7 +112,7 @@ 'css/custom.css', ] html_js_files = [ - 'https://kit.fontawesome.com/3102794088.js' + 'https://cdnjs.cloudflare.com/ajax/libs/font-awesome/5.15.1/css/all.min.css' ] master_doc = 'index' From 7c665f457ed59afe4d6380fe3faf208bb51f4faf Mon Sep 17 00:00:00 2001 From: Tilen Majerle Date: Thu, 7 Jan 2021 22:30:12 +0100 Subject: [PATCH 08/17] Add F401-nucleo demo --- .../STM32CubeIDE/.cproject | 193 +++++ .../STM32CubeIDE/.project | 202 +++++ .../STM32CubeIDE/STM32F401RETX_FLASH.ld | 175 ++++ ...m32f401re_nucleo_ds18b20_rtos Debug.launch | 73 ++ .../startup/startup_stm32f401xe.s | 432 ++++++++++ .../inc/FreeRTOSConfig.h | 174 ++++ .../inc/lwow_opts.h | 48 ++ .../inc/main.h | 80 ++ .../inc/stm32_assert.h | 73 ++ .../inc/stm32f4xx_hal_conf.h | 462 +++++++++++ .../inc/stm32f4xx_it.h | 65 ++ .../src/main.c | 241 ++++++ .../src/stm32f4xx_it.c | 116 +++ .../src/syscalls.c | 185 +++++ .../src/system_stm32f4xx.c | 763 ++++++++++++++++++ lwow/src/system/lwow_ll_stm32f401re_nucleo.c | 71 ++ 16 files changed, 3353 insertions(+) create mode 100644 examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/.cproject create mode 100644 examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/.project create mode 100644 examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/STM32F401RETX_FLASH.ld create mode 100644 examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/lwow_stm32f401re_nucleo_ds18b20_rtos Debug.launch create mode 100644 examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/startup/startup_stm32f401xe.s create mode 100644 examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/FreeRTOSConfig.h create mode 100644 examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/lwow_opts.h create mode 100644 examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/main.h create mode 100644 examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/stm32_assert.h create mode 100644 examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/stm32f4xx_hal_conf.h create mode 100644 examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/stm32f4xx_it.h create mode 100644 examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/main.c create mode 100644 examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/stm32f4xx_it.c create mode 100644 examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/syscalls.c create mode 100644 examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/system_stm32f4xx.c create mode 100644 lwow/src/system/lwow_ll_stm32f401re_nucleo.c diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/.cproject b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/.cproject new file mode 100644 index 0000000..3c3949a --- /dev/null +++ b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/.cproject @@ -0,0 +1,193 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/.project b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/.project new file mode 100644 index 0000000..6060362 --- /dev/null +++ b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/.project @@ -0,0 +1,202 @@ + + + lwow_stm32f401re_nucleo_ds18b20_rtos + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?children? + ?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\|| + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc:/STM32100B-EVAL/Debug} + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.st.stm32cube.ide.mcu.MCUTSConvertedProjectNature + + + + FreeRTOS/cmsis_os2.c + 1 + PARENT-4-PROJECT_LOC/third_party/embedded-libs/FreeRTOS/CMSIS_RTOS_V2/cmsis_os2.c + + + FreeRTOS/croutine.c + 1 + PARENT-4-PROJECT_LOC/third_party/embedded-libs/FreeRTOS/croutine.c + + + FreeRTOS/event_groups.c + 1 + PARENT-4-PROJECT_LOC/third_party/embedded-libs/FreeRTOS/event_groups.c + + + FreeRTOS/heap_4.c + 1 + PARENT-4-PROJECT_LOC/third_party/embedded-libs/FreeRTOS/portable/MemMang/heap_4.c + + + FreeRTOS/list.c + 1 + PARENT-4-PROJECT_LOC/third_party/embedded-libs/FreeRTOS/list.c + + + FreeRTOS/port.c + 1 + PARENT-4-PROJECT_LOC/third_party/embedded-libs/FreeRTOS/portable/GCC/ARM_CM4F/port.c + + + FreeRTOS/queue.c + 1 + PARENT-4-PROJECT_LOC/third_party/embedded-libs/FreeRTOS/queue.c + + + FreeRTOS/tasks.c + 1 + PARENT-4-PROJECT_LOC/third_party/embedded-libs/FreeRTOS/tasks.c + + + FreeRTOS/timers.c + 1 + PARENT-4-PROJECT_LOC/third_party/embedded-libs/FreeRTOS/timers.c + + + STM32F4xx_HAL_Driver/stm32f4xx_ll_dma.c + 1 + PARENT-4-PROJECT_LOC/third_party/embedded-libs/st_hal/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma.c + + + STM32F4xx_HAL_Driver/stm32f4xx_ll_exti.c + 1 + PARENT-4-PROJECT_LOC/third_party/embedded-libs/st_hal/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_exti.c + + + STM32F4xx_HAL_Driver/stm32f4xx_ll_gpio.c + 1 + PARENT-4-PROJECT_LOC/third_party/embedded-libs/st_hal/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_gpio.c + + + STM32F4xx_HAL_Driver/stm32f4xx_ll_pwr.c + 1 + PARENT-4-PROJECT_LOC/third_party/embedded-libs/st_hal/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_pwr.c + + + STM32F4xx_HAL_Driver/stm32f4xx_ll_rcc.c + 1 + PARENT-4-PROJECT_LOC/third_party/embedded-libs/st_hal/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c + + + STM32F4xx_HAL_Driver/stm32f4xx_ll_usart.c + 1 + PARENT-4-PROJECT_LOC/third_party/embedded-libs/st_hal/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c + + + STM32F4xx_HAL_Driver/stm32f4xx_ll_utils.c + 1 + PARENT-4-PROJECT_LOC/third_party/embedded-libs/st_hal/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_utils.c + + + User/main.c + 1 + PARENT-1-PROJECT_LOC/src/main.c + + + User/stm32f4xx_it.c + 1 + PARENT-1-PROJECT_LOC/src/stm32f4xx_it.c + + + User/syscalls.c + 1 + PARENT-1-PROJECT_LOC/src/syscalls.c + + + User/system_stm32f4xx.c + 1 + PARENT-1-PROJECT_LOC/src/system_stm32f4xx.c + + + lwow/lwow.c + 1 + PARENT-4-PROJECT_LOC/lwow/src/lwow/lwow.c + + + lwow/lwow_device_ds18x20.c + 1 + PARENT-4-PROJECT_LOC/lwow/src/devices/lwow_device_ds18x20.c + + + lwow/lwow_ll_stm32f401re_nucleo.c + 1 + PARENT-4-PROJECT_LOC/lwow/src/system/lwow_ll_stm32f401re_nucleo.c + + + lwow/lwow_sys_cmsis_os.c + 1 + PARENT-4-PROJECT_LOC/lwow/src/system/lwow_sys_cmsis_os.c + + + lwow/scan_devices.c + 1 + PARENT-4-PROJECT_LOC/snippets/scan_devices.c + + + diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/STM32F401RETX_FLASH.ld b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/STM32F401RETX_FLASH.ld new file mode 100644 index 0000000..b404df3 --- /dev/null +++ b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/STM32F401RETX_FLASH.ld @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file LinkerScript.ld + * @author Auto-generated by STM32CubeIDE + * @brief Linker script for STM32F401RETx Device from STM32F4 series + * 512Kbytes FLASH + * 96Kbytes RAM + * + * Set heap size, stack size and stack location according + * to application requirements. + * + * Set memory bank area and size if external memory is used + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/lwow_stm32f401re_nucleo_ds18b20_rtos Debug.launch b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/lwow_stm32f401re_nucleo_ds18b20_rtos Debug.launch new file mode 100644 index 0000000..6cfcd84 --- /dev/null +++ b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/lwow_stm32f401re_nucleo_ds18b20_rtos Debug.launch @@ -0,0 +1,73 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/startup/startup_stm32f401xe.s b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/startup/startup_stm32f401xe.s new file mode 100644 index 0000000..cc9a847 --- /dev/null +++ b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/STM32CubeIDE/startup/startup_stm32f401xe.s @@ -0,0 +1,432 @@ +/** + ****************************************************************************** + * @file startup_stm32f401xe.s + * @author MCD Application Team + * @brief STM32F401xExx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word 0 /* Reserved */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI4_IRQHandler /* SPI4 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/FreeRTOSConfig.h b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/FreeRTOSConfig.h new file mode 100644 index 0000000..a7ca454 --- /dev/null +++ b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/FreeRTOSConfig.h @@ -0,0 +1,174 @@ +/* + FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +/* Ensure stdint is only used by the compiler, and not the assembler. */ +#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__) + #include + extern uint32_t SystemCoreClock; +#endif + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES (7) +#define configMINIMAL_STACK_SIZE ((uint16_t)128) +#define configTOTAL_HEAP_SIZE ((size_t)(15 * 1024)) +#define configMAX_TASK_NAME_LEN (16) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configSUPPORT_STATIC_ALLOCATION 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer definitions. */ +#define configUSE_TIMERS 0 +#define configTIMER_TASK_PRIORITY 2 +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 + +/* Cortex-M specific definitions. */ +#ifdef __NVIC_PRIO_BITS + /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 4 /* 15 priority levels */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x0F + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 0x05 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +#define configASSERT( x ) if ((x) == 0) { taskDISABLE_INTERRUPTS(); for (;;) {} } + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS + standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler + +/* IMPORTANT: This define MUST be commented when used with STM32Cube firmware, + to prevent overwriting SysTick_Handler defined within STM32Cube HAL */ +/* #define xPortSysTickHandler SysTick_Handler */ + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/lwow_opts.h b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/lwow_opts.h new file mode 100644 index 0000000..f6459e9 --- /dev/null +++ b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/lwow_opts.h @@ -0,0 +1,48 @@ +/** + * \file lwow_opts.h + * \brief OW application options + */ + +/* + * Copyright (c) 2020 Tilen MAJERLE + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of LwOW. + * + * Author: Tilen MAJERLE + * Version: v3.0.1 + */ +#ifndef LWOW_HDR_OPTS_H +#define LWOW_HDR_OPTS_H + +/* Rename this file to "lwow_opts.h" for your application */ + +#include "cmsis_os.h" + +/* + * Open "include/lwow/lwow_opt.h" and + * copy & replace here settings you want to change values + */ +#define LWOW_CFG_OS 1 +#define LWOW_CFG_OS_MUTEX_HANDLE osMutexId_t + +#endif /* LWOW_HDR_OPTS_H */ diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/main.h b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/main.h new file mode 100644 index 0000000..dd8afe5 --- /dev/null +++ b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/main.h @@ -0,0 +1,80 @@ +/** + * \file main.h + * \brief Main file + */ + +/* + * Copyright (c) 2020 Tilen MAJERLE + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Author: Tilen MAJERLE + * Version: v3.0.1 + */ +#ifndef __MAIN_H +#define __MAIN_H + +#include "stm32f4xx.h" +#include "stm32f4xx_ll_rcc.h" +#include "stm32f4xx_ll_bus.h" +#include "stm32f4xx_ll_system.h" +#include "stm32f4xx_ll_exti.h" +#include "stm32f4xx_ll_cortex.h" +#include "stm32f4xx_ll_utils.h" +#include "stm32f4xx_ll_pwr.h" +#include "stm32f4xx_ll_dma.h" +#include "stm32f4xx_ll_usart.h" +#include "stm32f4xx_ll_gpio.h" +#include + +#ifndef NVIC_PRIORITYGROUP_0 +#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority, + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority, + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority, + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority, + 1 bit for subpriority */ +#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority, + 0 bit for subpriority */ +#endif + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +#ifdef __cplusplus + extern "C" { +#endif +void _Error_Handler(char *, int); + +#define Error_Handler() _Error_Handler(__FILE__, __LINE__) +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/stm32_assert.h b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/stm32_assert.h new file mode 100644 index 0000000..7fa31cf --- /dev/null +++ b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/stm32_assert.h @@ -0,0 +1,73 @@ +/** + ****************************************************************************** + * @file stm32_assert.h + * @brief STM32 assert file. + ****************************************************************************** + ** This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_ASSERT_H +#define __STM32_ASSERT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Includes ------------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_ASSERT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/stm32f4xx_hal_conf.h b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/stm32f4xx_hal_conf.h new file mode 100644 index 0000000..ccc3354 --- /dev/null +++ b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/stm32f4xx_hal_conf.h @@ -0,0 +1,462 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f4xx_hal_conf.h. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_CAN_MODULE_ENABLED +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +#define HAL_CRC_MODULE_ENABLED +#define HAL_CEC_MODULE_ENABLED +#define HAL_CRYP_MODULE_ENABLED +#define HAL_DAC_MODULE_ENABLED +#define HAL_DCMI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_DMA2D_MODULE_ENABLED +#define HAL_ETH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_NAND_MODULE_ENABLED +#define HAL_NOR_MODULE_ENABLED +#define HAL_PCCARD_MODULE_ENABLED +#define HAL_SRAM_MODULE_ENABLED +#define HAL_SDRAM_MODULE_ENABLED +#define HAL_HASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +#define HAL_LTDC_MODULE_ENABLED +#define HAL_DSI_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_QSPI_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_SAI_MODULE_ENABLED +#define HAL_SD_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +#define HAL_IRDA_MODULE_ENABLED +#define HAL_SMARTCARD_MODULE_ENABLED +#define HAL_WWDG_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED +#define HAL_FMPI2C_MODULE_ENABLED +#define HAL_SPDIFRX_MODULE_ENABLED +#define HAL_DFSDM_MODULE_ENABLED +#define HAL_LPTIM_MODULE_ENABLED +#define HAL_MMC_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848 PHY Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY 0x000000FFU +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY 0x00000FFFU + +#define PHY_READ_TO 0x0000FFFFU +#define PHY_WRITE_TO 0x0000FFFFU + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ + +#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ +#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ +#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ + +#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ + +#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ +#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ + +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 1U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f4xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_FMPI2C_MODULE_ENABLED + #include "stm32f4xx_hal_fmpi2c.h" +#endif /* HAL_FMPI2C_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f4xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/stm32f4xx_it.h b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/stm32f4xx_it.h new file mode 100644 index 0000000..3a2df69 --- /dev/null +++ b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/stm32f4xx_it.h @@ -0,0 +1,65 @@ +/** + ****************************************************************************** + * @file stm32f7xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_IT_H +#define __STM32F7xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/main.c b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/main.c new file mode 100644 index 0000000..5c143fc --- /dev/null +++ b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/main.c @@ -0,0 +1,241 @@ +/** + * \file main.c + * \brief Main file + */ + +/* + * Copyright (c) 2020 Tilen MAJERLE + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Author: Tilen MAJERLE + * Version: v3.0.1 + */ +#include "main.h" +#include "cmsis_os.h" +#include "lwow/lwow.h" +#include "lwow/devices/lwow_device_ds18x20.h" +#include "scan_devices.h" + +static void LL_Init(void); +void SystemClock_Config(void); +static void USART_Printf_Init(void); + +static void app_thread(void* arg); + +/* Create new 1-Wire instance */ +extern const lwow_ll_drv_t lwow_ll_drv_stm32; +lwow_t ow; +lwow_rom_t rom_ids[20]; +size_t rom_found; + +/** + * \brief Program entry point + */ +int +main(void) { + LL_Init(); /* Reset of all peripherals, initializes the Flash interface and the Systick. */ + SystemClock_Config(); /* Configure the system clock */ + USART_Printf_Init(); /* Init USART for printf */ + + printf("Application running on STM32F401RE-Nucleo!\r\n"); + + osKernelInitialize(); + const osThreadAttr_t app_thread_attr = { + .priority = osPriorityNormal, + .stack_size = 512 + }; + osThreadNew(app_thread, NULL, &app_thread_attr);/* Create application thread */ + osKernelStart(); /* Start kernel */ + + while (1) {} +} + +/** + * \brief Application thread + * \param[in] arg: Thread argument + */ +static void +app_thread(void* arg) { + float avg_temp; + size_t avg_temp_count; + + /* Initialize 1-Wire library and set user argument to NULL */ + lwow_init(&ow, &lwow_ll_drv_stm32, NULL); + + /* Get onewire devices connected on 1-wire port */ + do { + if (scan_onewire_devices(&ow, rom_ids, LWOW_ARRAYSIZE(rom_ids), &rom_found) == lwowOK) { + printf("Devices scanned, found %d devices!\r\n", (int)rom_found); + } else { + printf("Device scan error\r\n"); + } + if (rom_found == 0) { + osDelay(1000); + } + } while (rom_found == 0); + + if (rom_found > 0) { + /* Infinite loop */ + while (1) { + printf("Start temperature conversion\r\n"); + lwow_ds18x20_start(&ow, NULL); /* Start conversion on all devices, use protected API */ + osDelay(1000); /* Release thread for 1 second */ + + /* Read temperature on all devices */ + avg_temp = 0; + avg_temp_count = 0; + for (size_t i = 0; i < rom_found; i++) { + if (lwow_ds18x20_is_b(&ow, &rom_ids[i])) { + float temp; + uint8_t resolution = lwow_ds18x20_get_resolution(&ow, &rom_ids[i]); + if (lwow_ds18x20_read(&ow, &rom_ids[i], &temp)) { + printf("Sensor %02u temperature is %d.%d degrees (%u bits resolution)\r\n", + (unsigned)i, (int)temp, (int)((temp * 1000.0f) - (((int)temp) * 1000)), (unsigned)resolution); + + avg_temp += temp; + avg_temp_count++; + } else { + printf("Could not read temperature on sensor %u\r\n", (unsigned)i); + } + } + } + if (avg_temp_count > 0) { + avg_temp = avg_temp / avg_temp_count; + } + printf("Average temperature: %d.%d degrees\r\n", (int)avg_temp, (int)((avg_temp * 100.0f) - ((int)avg_temp) * 100)); + } + } + printf("Terminating application thread\r\n"); + osThreadExit(); +} + +/** + * \brief Low-Layer initialization + */ +static void +LL_Init(void) { + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG); + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); + + NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + NVIC_SetPriority(MemoryManagement_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); + NVIC_SetPriority(BusFault_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); + NVIC_SetPriority(UsageFault_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); + NVIC_SetPriority(SVCall_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); + NVIC_SetPriority(DebugMonitor_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); + NVIC_SetPriority(PendSV_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); + NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 15, 0)); +} + +/** + * \brief System clock configuration + */ +void +SystemClock_Config(void) { + /* Configure flash latency */ + LL_FLASH_SetLatency(LL_FLASH_LATENCY_2); + if (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_2) { + while (1) {} + } + + /* Set voltage scaling */ + LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1); + + /* Enable HSE */ + LL_RCC_HSE_EnableBypass(); + LL_RCC_HSE_Enable(); + while (LL_RCC_HSE_IsReady() != 1) {} + + /* Enable PLL */ + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_4, 84, LL_RCC_PLLP_DIV_2); + LL_RCC_PLL_Enable(); + while (LL_RCC_PLL_IsReady() != 1) {} + + /* Set prescalers */ + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2); + LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1); + + /* Configure system clock to PLL */ + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {} + + /* Configure systick */ + LL_Init1msTick(84000000); + LL_SYSTICK_SetClkSource(LL_SYSTICK_CLKSOURCE_HCLK); + LL_SYSTICK_EnableIT(); + LL_SetSystemCoreClock(84000000); +} + +/** + * \brief Init USART2 for printf output + */ +static void +USART_Printf_Init(void) { + LL_USART_InitTypeDef USART_InitStruct = {0}; + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2); + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA); + + /* + * USART2 GPIO Configuration + * + * PA2 ------> USART2_TX + * PA3 ------> USART2_RX + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_2 | LL_GPIO_PIN_3; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_UP; + GPIO_InitStruct.Alternate = LL_GPIO_AF_7; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + USART_InitStruct.BaudRate = 921600; + USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; + USART_InitStruct.StopBits = LL_USART_STOPBITS_1; + USART_InitStruct.Parity = LL_USART_PARITY_NONE; + USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; + USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; + USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; + LL_USART_Init(USART2, &USART_InitStruct); + LL_USART_ConfigAsyncMode(USART2); + LL_USART_Enable(USART2); +} + +/** + * \brief Printf character handler + * \param[in] ch: Character to send + * \param[in] f: File pointer + * \return Written character + */ +#ifdef __GNUC__ +int __io_putchar(int ch) { +#else +int fputc(int ch, FILE* fil) { +#endif + LL_USART_TransmitData8(USART2, (uint8_t)ch); + while (!LL_USART_IsActiveFlag_TXE(USART2)) {} + return ch; +} diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/stm32f4xx_it.c b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/stm32f4xx_it.c new file mode 100644 index 0000000..3575430 --- /dev/null +++ b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/stm32f4xx_it.c @@ -0,0 +1,116 @@ +/** + ****************************************************************************** + * @file stm32f4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" +#include "stm32f4xx_it.h" + +#include "cmsis_os.h" + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ + +/** + * \brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) { + while (1) { + + } +} + +/** + * \brief This function handles Hard fault interrupt. + */ +void +HardFault_Handler(void) { + while (1) { + + } +} + +/** + * \brief This function handles Mem manage interrupt. + */ +void +MemManage_Handler(void) { + while (1) { + + } +} + +/** + * \brief This function handles Bus fault interrupt. + */ +void +BusFault_Handler(void) { + while (1) { + + } +} + +/** + * \brief This function handles Usage fault interrupt. + */ +void +UsageFault_Handler(void) { + while (1) { + + } +} + +/** + * \brief This function handles Debug monitor interrupt. + */ +void +DebugMon_Handler(void) { + while (1) { + + } +} + +/** + * \brief This function handles Systick interrupt. + */ +void +SysTick_Handler(void) { + extern void xPortSysTickHandler(void); + xPortSysTickHandler(); +} + +/******************************************************************************/ +/* STM32F4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f4xx.s). */ +/******************************************************************************/ diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/syscalls.c b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/syscalls.c new file mode 100644 index 0000000..d4839b3 --- /dev/null +++ b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/syscalls.c @@ -0,0 +1,185 @@ +/* Support files for GNU libc. Files in the system namespace go here. + Files in the C namespace (ie those that do not start with an + underscore) go in .c. */ + +#include <_ansi.h> +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FreeRTOS +#define MAX_STACK_SIZE 0x2000 + +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + +#ifndef FreeRTOS + register char * stack_ptr asm("sp"); +#endif + +caddr_t _sbrk(int incr) +{ + extern char end asm("end"); + static char *heap_end; + char *prev_heap_end,*min_stack_ptr; + + if (heap_end == 0) + heap_end = &end; + + prev_heap_end = heap_end; + +#ifdef FreeRTOS + /* Use the NVIC offset register to locate the main stack pointer. */ + min_stack_ptr = (char*)(*(unsigned int *)*(unsigned int *)0xE000ED08); + /* Locate the STACK bottom address */ + min_stack_ptr -= MAX_STACK_SIZE; + + if (heap_end + incr > min_stack_ptr) +#else + if (heap_end + incr > stack_ptr) +#endif + { +// write(1, "Heap and stack collision\n", 25); +// abort(); + errno = ENOMEM; + return (caddr_t) -1; + } + + heap_end += incr; + + return (caddr_t) prev_heap_end; +} + +/* + * _gettimeofday primitive (Stub function) + * */ +int _gettimeofday (struct timeval * tp, struct timezone * tzp) +{ + /* Return fixed data for the timezone. */ + if (tzp) + { + tzp->tz_minuteswest = 0; + tzp->tz_dsttime = 0; + } + + return 0; +} +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} +} + +int _write(int file, char *ptr, int len) +{ + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) { + __io_putchar( *ptr++ ); + } + return len; +} + +int _close(int file) +{ + return -1; +} + +int _fstat(int file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + return 0; +} + +int _read(int file, char *ptr, int len) +{ + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +int _open(char *path, int flags, ...) +{ + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + return -1; +} + +int _stat(char *file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + errno = ENOMEM; + return -1; +} diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/system_stm32f4xx.c b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/system_stm32f4xx.c new file mode 100644 index 0000000..315aad3 --- /dev/null +++ b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/system_stm32f4xx.c @@ -0,0 +1,763 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @version V2.6.1 + * @date 14-February-2017 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ + STM32F412Zx || STM32F412Vx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; + + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + FMC_Bank5_6->SDCR[0] = 0x000019E4; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ + + (void)(tmp); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + +#if defined(STM32F446xx) + /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface + clock */ + RCC->AHB1ENR |= 0x0000007D; +#else + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; +#endif /* STM32F446xx */ + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + +#if defined(STM32F446xx) + /* Connect PAx pins to FMC Alternate function */ + GPIOA->AFR[0] |= 0xC0000000; + GPIOA->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOA->MODER |= 0x00008000; + /* Configure PDx pins speed to 50 MHz */ + GPIOA->OSPEEDR |= 0x00008000; + /* Configure PDx pins Output type to push-pull */ + GPIOA->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOA->PUPDR |= 0x00000000; + + /* Connect PCx pins to FMC Alternate function */ + GPIOC->AFR[0] |= 0x00CC0000; + GPIOC->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOC->MODER |= 0x00000A00; + /* Configure PDx pins speed to 50 MHz */ + GPIOC->OSPEEDR |= 0x00000A00; + /* Configure PDx pins Output type to push-pull */ + GPIOC->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOC->PUPDR |= 0x00000000; +#endif /* STM32F446xx */ + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable SDRAM bank1 */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCR[0] = 0x00001954; +#else + FMC_Bank5_6->SDCR[0] = 0x000019E4; +#endif /* STM32F446xx */ + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x000000F3; +#else + FMC_Bank5_6->SDCMR = 0x00000073; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x00044014; +#else + FMC_Bank5_6->SDCMR = 0x00046014; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; +#if defined(STM32F446xx) + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); +#else + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); +#endif /* STM32F446xx */ + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) + +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ + || defined(STM32F412Zx) || defined(STM32F412Vx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ + (void)(tmp); +} +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/lwow/src/system/lwow_ll_stm32f401re_nucleo.c b/lwow/src/system/lwow_ll_stm32f401re_nucleo.c new file mode 100644 index 0000000..4514009 --- /dev/null +++ b/lwow/src/system/lwow_ll_stm32f401re_nucleo.c @@ -0,0 +1,71 @@ +/** + * \file lwow_ll_stm32f401re_nucleo.c + * \brief UART implementation for STM32F401RE-Nucleo + */ + +/* + * Copyright (c) 2020 Tilen MAJERLE + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of LwOW - Lightweight onewire library. + * + * Author: Tilen MAJERLE + * Version: v3.0.1 + */ + +/* + * Default UART configuration is: + * + * UART: USART1 + * STM32 TX: GPIOA, GPIO_PIN_9 + * STM32 RX: GPIOA, GPIO_PIN_10 + */ + +#if !__DOXYGEN__ + +#include "stm32f4xx_ll_usart.h" +#include "stm32f4xx_ll_bus.h" +#include "stm32f4xx_ll_rcc.h" +#include "stm32f4xx_ll_dma.h" +#include "stm32f4xx_ll_gpio.h" +#include "stm32f4xx_ll_pwr.h" + +/* USART */ +#define ONEWIRE_USART USART1 +#define ONEWIRE_USART_CLK_EN LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1) + +/* USART TX PIN */ +#define ONEWIRE_TX_PORT GPIOA +#define ONEWIRE_TX_PORT_CLK_EN LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA) +#define ONEWIRE_TX_PIN LL_GPIO_PIN_9 +#define ONEWIRE_TX_PIN_AF LL_GPIO_AF_7 + +/* USART RX PIN */ +#define ONEWIRE_RX_PORT GPIOA +#define ONEWIRE_RX_PORT_CLK_EN LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA) +#define ONEWIRE_RX_PIN LL_GPIO_PIN_10 +#define ONEWIRE_RX_PIN_AF LL_GPIO_AF_7 + +/* Include generic STM32 driver */ +#include "../system/lwow_ll_stm32.c" + +#endif /* !__DOXYGEN__ */ From d5e108666a191b170e3081862be9f0bc0255c888 Mon Sep 17 00:00:00 2001 From: Tilen Majerle Date: Fri, 12 Feb 2021 16:27:28 +0100 Subject: [PATCH 09/17] Optimize code --- .../Core/Src/main.c | 15 ++++++--------- lwow/src/devices/lwow_device_ds18x20.c | 4 ++-- 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/examples/stm32/ow_ds18b20_multi_rtos_stm32f429zi_nucleo/Core/Src/main.c b/examples/stm32/ow_ds18b20_multi_rtos_stm32f429zi_nucleo/Core/Src/main.c index 7db5bb7..ec9fe18 100644 --- a/examples/stm32/ow_ds18b20_multi_rtos_stm32f429zi_nucleo/Core/Src/main.c +++ b/examples/stm32/ow_ds18b20_multi_rtos_stm32f429zi_nucleo/Core/Src/main.c @@ -67,18 +67,15 @@ const osThreadAttr_t lwow_task_attributes = { /* Custom structure for link between onewire and uarts */ typedef struct { + lwow_t ow; uint8_t id; - lwow_t* ow; UART_HandleTypeDef* uart; } ow_uart_link_t; -/* OneWire instances */ -lwow_t ow1, ow2, ow3; - /* Make links between ow and uart */ -static ow_uart_link_t ow_uart_link_1 = { .id = 1, .ow = &ow1, .uart = &huart1 }; -static ow_uart_link_t ow_uart_link_2 = { .id = 2, .ow = &ow2, .uart = &huart2 }; -static ow_uart_link_t ow_uart_link_3 = { .id = 3, .ow = &ow3, .uart = &huart6 }; +static ow_uart_link_t ow_uart_link_1 = { .id = 1, .uart = &huart1 }; +static ow_uart_link_t ow_uart_link_2 = { .id = 2, .uart = &huart2 }; +static ow_uart_link_t ow_uart_link_3 = { .id = 3, .uart = &huart6 }; /* Use extern low-level for OW using HAL */ extern const lwow_ll_drv_t lwow_ll_drv_stm32_hal; @@ -474,14 +471,14 @@ void start_lwow_task(void *argument) } /* Initialize OW instance */ - res = lwow_init(link->ow, &lwow_ll_drv_stm32_hal, link->uart); + res = lwow_init(&link->ow, &lwow_ll_drv_stm32_hal, link->uart); /* Initialize OW with UART instance as custom parameter */ safeprintf("[OW %d] Init OW: %d\r\n", (int)link->id, (int)res); /* Scan device procedure */ do { - if (scan_onewire_devices(link->ow, rom_ids, ROM_IDS_SIZE, &rom_found) == lwowOK) { + if (scan_onewire_devices(&link->ow, rom_ids, ROM_IDS_SIZE, &rom_found) == lwowOK) { safeprintf("[OW %d] Devices scanned, found %d devices!\r\n", (int)link->id, (int)rom_found); } else { safeprintf("[OW %d] Device scan error\r\n", (int)link->id); diff --git a/lwow/src/devices/lwow_device_ds18x20.c b/lwow/src/devices/lwow_device_ds18x20.c index 7acc4bc..6ce2665 100644 --- a/lwow/src/devices/lwow_device_ds18x20.c +++ b/lwow/src/devices/lwow_device_ds18x20.c @@ -106,10 +106,10 @@ lwow_ds18x20_read_raw(lwow_t* const ow, const lwow_rom_t* const rom_id, float* c lwow_write_byte_ex_raw(ow, LWOW_CMD_RSCRATCHPAD, NULL); /* Read plain data from device */ - for (uint8_t i = 0; i < 9; ++i) { + for (uint8_t i = 0; i < LWOW_ARRAYSIZE(data); ++i) { lwow_read_byte_ex_raw(ow, &data[i]); } - crc = lwow_crc(data, 0x09); /* Calculate CRC */ + crc = lwow_crc(data, LWOW_ARRAYSIZE(data)); /* Calculate CRC */ if (crc == 0) { /* Result must be 0 to match the CRC */ temp = (data[1] << 0x08) | data[0]; /* Format data in integer format */ resolution = ((data[4] & 0x60) >> 0x05) + 0x09; /* Set resolution in units of bits */ From e2e420424cf8ef040ec93d387307e3f64654762b Mon Sep 17 00:00:00 2001 From: Tilen Majerle Date: Mon, 29 Mar 2021 14:10:16 +0200 Subject: [PATCH 10/17] Add Changelog --- CHANGELOG.md | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 CHANGELOG.md diff --git a/CHANGELOG.md b/CHANGELOG.md new file mode 100644 index 0000000..ade7313 --- /dev/null +++ b/CHANGELOG.md @@ -0,0 +1,52 @@ +# Changelog + +## v3.0.1 + +- Change configuration options from _CONFIG_ to _OPT +- Apply code style settings with Artistic style options +- Update docs + +## v3.0.0 + +- Break compatibility vs `2.0.0` +- New name of library is now LwOW - Lightweight onewire +- Added `_ex` functions to read/write bytes or bits +- Added drivers features as set of callback functions with drv pointer +- Rename private functions to `prv_` prefix + +## v2.0.0 + +- LL drivers are now passed as custom structure to allow multiple blocks as separate drivers +- Added first sphinx documentation +- Updated examples + +## v1.2.0 + +- Automatically set result to OK when search function finds at least 1 connected device +- Upgrade examples to CMSIS OS V2 +- Use pre-increment/decrement +- Other C code style fixes + +## v1.1.0 + +- Added assert for all API functions +- Added new owPARERR enumerator for wrong parameters +- Added `ow_deinit` function implementation + +## v1.0.0 + +- Use separate ROM structure instead of byte array +- Add option to search devices with command and save result directly to input array +- Make all variables as local instead of using user pointers + +## v0.2.0 + +- Removed `protect` parameter in API functions +- Added `_raw` functions to provide non-thread-safe implementation for operating systems +- Separate API functions with operating system protection + +## v0.1.0 + +- Support for UART interface instead of software emulation on microcontroller or PC application +- Support for operating systems (including non-real-time) +- Added API driver for *DS18x20* temperature sensor \ No newline at end of file From b1ffbdbc55abf76fb3d01c8c050dc3bcf6622d11 Mon Sep 17 00:00:00 2001 From: Tilen Majerle Date: Fri, 9 Apr 2021 18:14:25 +0200 Subject: [PATCH 11/17] Add new conf --- docs/conf.py | 26 ++++++++++++-------------- lwow/src/include/lwow/lwow.h | 2 +- 2 files changed, 13 insertions(+), 15 deletions(-) diff --git a/docs/conf.py b/docs/conf.py index bf526f3..c544e67 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -26,27 +26,25 @@ copyright = '2020, Tilen MAJERLE' author = 'Tilen MAJERLE' -# The full version, including alpha/beta/rc tags -version = 'v3.0.1' - -# Try to get branch at which this is running -# and try to determine which version to display in sphinx -git_branch = '' +# Get current branch res = os.popen('git branch').read().strip() for line in res.split("\n"): if line[0] == '*': git_branch = line[1:].strip() # Decision for display version -try: - if git_branch.index('develop') >= 0: - version = "latest-develop" -except Exception: - print("Exception for index check") - -# For debugging purpose +if git_branch == 'master' or git_branch == 'main': + version = os.popen('git describe --tags --abbrev=0').read().strip() + if version == '': + version = 'v0.0.0' +elif git_branch == 'develop': + version = 'latest-develop' +else: + version = 'branch-' + git_branch + +# For debugging purpose only print("GIT BRANCH: " + git_branch) -print("VERSION: " + version) +print("GIT VERSION: " + version) # -- General configuration --------------------------------------------------- diff --git a/lwow/src/include/lwow/lwow.h b/lwow/src/include/lwow/lwow.h index 8c921e1..b949a48 100644 --- a/lwow/src/include/lwow/lwow.h +++ b/lwow/src/include/lwow/lwow.h @@ -1,5 +1,5 @@ /** - * \file ow.h + * \file lwow.h * \brief LwOW library */ From 61a3228f67b6c5cb76138e5d494ede9a366b0250 Mon Sep 17 00:00:00 2001 From: Tilen Majerle Date: Fri, 9 Apr 2021 20:45:17 +0200 Subject: [PATCH 12/17] conf.py update --- docs/conf.py | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/docs/conf.py b/docs/conf.py index c544e67..988b861 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -26,6 +26,12 @@ copyright = '2020, Tilen MAJERLE' author = 'Tilen MAJERLE' +# Try to get branch at which this is running +# and try to determine which version to display in sphinx +# Version is using git tag if on master or "latest-develop" if on develop branch +version = '' +git_branch = '' + # Get current branch res = os.popen('git branch').read().strip() for line in res.split("\n"): @@ -33,11 +39,12 @@ git_branch = line[1:].strip() # Decision for display version -if git_branch == 'master' or git_branch == 'main': +git_branch = git_branch.replace('(HEAD detached at ', '').replace(')', '') +if git_branch.find('master') >= 0 or git_branch.find('main') >= 0: version = os.popen('git describe --tags --abbrev=0').read().strip() if version == '': version = 'v0.0.0' -elif git_branch == 'develop': +elif git_branch.find('develop') != -1 and not (git_branch.find('develop-') >= 0 or git_branch.find('develop/') >= 0): version = 'latest-develop' else: version = 'branch-' + git_branch From cbe7373a509145e0a75e0d9d2dfe7429604eb6e5 Mon Sep 17 00:00:00 2001 From: Tilen Majerle Date: Sat, 10 Apr 2021 11:33:09 +0200 Subject: [PATCH 13/17] Fix requirements for all repositories --- docs/requirements.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/requirements.txt b/docs/requirements.txt index c0ffd67..eb5e0fd 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -1,7 +1,7 @@ breathe>=4.9.1 colorama -docutils>=0.14 -sphinx>=2.0.1 +docutils==0.16 +sphinx>=3.5.1 sphinx_rtd_theme sphinx-tabs sphinxcontrib-svg2pdfconverter From 94dc161e54de546993c0a1610f19c8680e5c7ce4 Mon Sep 17 00:00:00 2001 From: Tilen Majerle Date: Sun, 11 Apr 2021 12:10:20 +0200 Subject: [PATCH 14/17] Add release workflow --- .github/workflows/release.yml | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 .github/workflows/release.yml diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml new file mode 100644 index 0000000..c4e4ac0 --- /dev/null +++ b/.github/workflows/release.yml @@ -0,0 +1,27 @@ +on: + push: + # Sequence of patterns matched against refs/tags + tags: + - 'v*' # Push events to matching v*, i.e. v1.0, v20.15.10 + +name: Create Release + +jobs: + build: + name: Create Release + runs-on: ubuntu-latest + steps: + - name: Checkout code + uses: actions/checkout@v2 + - name: Create Release + id: create_release + uses: actions/create-release@v1 + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} # This token is provided by Actions, you do not need to create your own token + with: + tag_name: ${{ github.ref }} + release_name: Release ${{ github.ref }} + body: | + See the CHANGELOG.md + draft: false + prerelease: false \ No newline at end of file From 8cbc2ca59f16dca530bedc4f422863eeb5d7d8e5 Mon Sep 17 00:00:00 2001 From: Tilen Majerle Date: Tue, 13 Apr 2021 21:56:17 +0200 Subject: [PATCH 15/17] Update getting started --- docs/get-started/index.rst | 45 +++++++++++++++++++++++++------------- 1 file changed, 30 insertions(+), 15 deletions(-) diff --git a/docs/get-started/index.rst b/docs/get-started/index.rst index b546ce2..b472247 100644 --- a/docs/get-started/index.rst +++ b/docs/get-started/index.rst @@ -3,6 +3,9 @@ Getting started =============== +Getting started may be the most challenging part of every new library. +This guide is describing how to start with the library quickly and effectively + .. _download_library: Download library @@ -10,8 +13,11 @@ Download library Library is primarly hosted on `Github `_. -* Download latest release from `releases area `_ on Github -* Clone `develop` branch for latest development +You can get it with: + +* Downloading latest release from `releases area `_ on Github +* Cloning ``master`` branch for latest stable version +* Cloning ``develop`` branch for latest development Download from releases ********************** @@ -24,7 +30,9 @@ Clone from Github First-time clone """""""""""""""" -* Download and install ``git`` if not already +This is used when you do not have yet local copy on your machine. + +* Make sure ``git`` is installed. * Open console and navigate to path in the system to clone repository to. Use command ``cd your_path`` * Clone repository with one of available ``3`` options @@ -38,40 +46,47 @@ Update cloned to latest version """"""""""""""""""""""""""""""" * Open console and navigate to path in the system where your resources repository is. Use command ``cd your_path`` -* Run ``git pull origin master --recurse-submodules`` command to pull latest changes and to fetch latest changes from submodules +* Run ``git pull origin master --recurse-submodules`` command to pull latest changes and to fetch latest changes from submodules on ``master`` branch +* Run ``git pull origin develop --recurse-submodules`` command to pull latest changes and to fetch latest changes from submodules on ``develop`` branch * Run ``git submodule foreach git pull origin master`` to update & merge all submodules .. note:: - This is preferred option to use when you want to evaluate library and run prepared examples. - Repository consists of multiple submodules which can be automatically downloaded when cloning and pulling changes from root repository. + This is preferred option to use when you want to evaluate library and run prepared examples. + Repository consists of multiple submodules which can be automatically downloaded when cloning and pulling changes from root repository. Add library to project ^^^^^^^^^^^^^^^^^^^^^^ At this point it is assumed that you have successfully download library, either cloned it or from releases page. +Next step is to add the library to the project, by means of source files to compiler inputs and header files in search path -* Copy ``lwow`` folder to your project -* Add ``lwow/src/include`` folder to `include path` of your toolchain -* Add source files from ``lwow/src/`` folder to toolchain build +* Copy ``lwow`` folder to your project, it contains library files +* Add ``lwow/src/include`` folder to `include path` of your toolchain. This is where `C/C++` compiler can find the files during compilation process. Usually using ``-I`` flag +* Add source files from ``lwow/src/`` folder to toolchain build. These files are built by `C/C++` compiler * Copy ``lwow/src/include/lwow/lwow_opts_template.h`` to project folder and rename it to ``lwow_opts.h`` -* Implement device drivers for UART hardware * Build the project Configuration file ^^^^^^^^^^^^^^^^^^ +Configuration file is used to overwrite default settings defined for the essential use case. Library comes with template config file, which can be modified according to needs. -This file shall be named ``lwow_opts.h`` and its default template looks like the one below. +and it should be copied (or simply renamed in-place) and named ``lwow_opts.h`` .. note:: Default configuration template file location: ``lwow/src/include/lwow/lwow_opts_template.h``. - File must be renamed to ``lwow_opts.h`` first and then copied to the project directory (or simply renamed in-place) where compiler + File must be renamed to ``lwow_opts.h`` first and then copied to the project directory where compiler include paths have access to it by using ``#include "lwow_opts.h"``. -.. tip:: - Check :ref:`api_lwow_opt` section for possible configuration settings +List of configuration options are available in the :ref:`api_lwow_opt` section. +If any option is about to be modified, it should be done in configuration file .. literalinclude:: ../../lwow/src/include/lwow/lwow_opts_template.h :language: c :linenos: - :caption: Config template file + :caption: Template configuration file + +.. note:: + If you prefer to avoid using configuration file, application must define + a global symbol ``LWOW_IGNORE_USER_OPTS``, visible across entire application. + This can be achieved with ``-D`` compiler option. From a45af8a044755d67361980245159e1503e3c91ee Mon Sep 17 00:00:00 2001 From: Tilen Majerle Date: Tue, 1 Jun 2021 20:20:59 +0200 Subject: [PATCH 16/17] Update cmsis-os driver to support kernel aware debuggers --- lwow/src/system/lwow_sys_cmsis_os.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/lwow/src/system/lwow_sys_cmsis_os.c b/lwow/src/system/lwow_sys_cmsis_os.c index c962e31..9fba7a0 100644 --- a/lwow/src/system/lwow_sys_cmsis_os.c +++ b/lwow/src/system/lwow_sys_cmsis_os.c @@ -41,11 +41,10 @@ uint8_t lwow_sys_mutex_create(LWOW_CFG_OS_MUTEX_HANDLE* m, void* arg) { LWOW_UNUSED(arg); const osMutexAttr_t attr = { - .attr_bits = osMutexRecursive + .attr_bits = osMutexRecursive, + .name = "lwow_mutex", }; - - *m = osMutexNew(&attr); - return *m != NULL; + return (*m = osMutexNew(&attr)) != NULL; } uint8_t From 525dfc91312b466883efb28aee6dd6cedc89e953 Mon Sep 17 00:00:00 2001 From: Tilen Majerle Date: Tue, 1 Jun 2021 20:41:53 +0200 Subject: [PATCH 17/17] CMSIS-OS driver improvements --- CHANGELOG.md | 4 ++++ dev/VisualStudio/lwow_opts.h | 2 +- .../Core/Inc/lwow_opts.h | 2 +- .../stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/lwow_opts.h | 2 +- examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/main.h | 2 +- examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/main.c | 2 +- .../stm32/ow_ds18b20_rtos_stm32f429zi_nucleo/inc/lwow_opts.h | 2 +- examples/stm32/ow_ds18b20_rtos_stm32f429zi_nucleo/inc/main.h | 2 +- examples/stm32/ow_ds18b20_rtos_stm32f429zi_nucleo/src/main.c | 2 +- .../ow_ds18b20_rtos_stm32l496g_discovery/inc/lwow_opts.h | 2 +- .../stm32/ow_ds18b20_rtos_stm32l496g_discovery/inc/main.h | 2 +- .../stm32/ow_ds18b20_rtos_stm32l496g_discovery/src/main.c | 2 +- .../stm32/ow_ds18b20_stm32l496g_discovery/inc/lwow_opts.h | 2 +- examples/stm32/ow_ds18b20_stm32l496g_discovery/inc/main.h | 2 +- examples/stm32/ow_ds18b20_stm32l496g_discovery/src/main.c | 2 +- lwow/src/devices/lwow_device_ds18x20.c | 2 +- lwow/src/include/lwow/devices/lwow_device_ds18x20.h | 2 +- lwow/src/include/lwow/lwow.h | 2 +- lwow/src/include/lwow/lwow_opt.h | 2 +- lwow/src/include/lwow/lwow_opts_template.h | 2 +- lwow/src/lwow/lwow.c | 2 +- lwow/src/system/lwow_ll_stm32.c | 2 +- lwow/src/system/lwow_ll_stm32_hal.c | 2 +- lwow/src/system/lwow_ll_stm32f401re_nucleo.c | 2 +- lwow/src/system/lwow_ll_stm32f429zi_nucleo.c | 2 +- lwow/src/system/lwow_ll_stm32l0xx.c | 2 +- lwow/src/system/lwow_ll_stm32l496g_discovery.c | 2 +- lwow/src/system/lwow_ll_template.c | 2 +- lwow/src/system/lwow_ll_win32.c | 2 +- lwow/src/system/lwow_sys_cmsis_os.c | 2 +- lwow/src/system/lwow_sys_template.c | 2 +- lwow/src/system/lwow_sys_win32.c | 2 +- lwow/src/system/ow_ll_stm32.c | 2 +- lwow/src/system/ow_ll_stm32_hal.c | 2 +- 34 files changed, 37 insertions(+), 33 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index ade7313..b37d073 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,9 @@ # Changelog +## v3.0.2 + +- Update CMSIS OS driver to support FreeRTOS aware kernel + ## v3.0.1 - Change configuration options from _CONFIG_ to _OPT diff --git a/dev/VisualStudio/lwow_opts.h b/dev/VisualStudio/lwow_opts.h index 3c901fe..679a11b 100644 --- a/dev/VisualStudio/lwow_opts.h +++ b/dev/VisualStudio/lwow_opts.h @@ -29,7 +29,7 @@ * This file is part of OneWire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #ifndef LWOW_HDR_OPTS_H #define LWOW_HDR_OPTS_H diff --git a/examples/stm32/ow_ds18b20_multi_rtos_stm32f429zi_nucleo/Core/Inc/lwow_opts.h b/examples/stm32/ow_ds18b20_multi_rtos_stm32f429zi_nucleo/Core/Inc/lwow_opts.h index f6459e9..2056d32 100644 --- a/examples/stm32/ow_ds18b20_multi_rtos_stm32f429zi_nucleo/Core/Inc/lwow_opts.h +++ b/examples/stm32/ow_ds18b20_multi_rtos_stm32f429zi_nucleo/Core/Inc/lwow_opts.h @@ -29,7 +29,7 @@ * This file is part of LwOW. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #ifndef LWOW_HDR_OPTS_H #define LWOW_HDR_OPTS_H diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/lwow_opts.h b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/lwow_opts.h index f6459e9..2056d32 100644 --- a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/lwow_opts.h +++ b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/lwow_opts.h @@ -29,7 +29,7 @@ * This file is part of LwOW. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #ifndef LWOW_HDR_OPTS_H #define LWOW_HDR_OPTS_H diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/main.h b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/main.h index dd8afe5..b168bfb 100644 --- a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/main.h +++ b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/inc/main.h @@ -27,7 +27,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #ifndef __MAIN_H #define __MAIN_H diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/main.c b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/main.c index 5c143fc..6d612cf 100644 --- a/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/main.c +++ b/examples/stm32/ow_ds18b20_rtos_stm32f401re_nucleo/src/main.c @@ -27,7 +27,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #include "main.h" #include "cmsis_os.h" diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f429zi_nucleo/inc/lwow_opts.h b/examples/stm32/ow_ds18b20_rtos_stm32f429zi_nucleo/inc/lwow_opts.h index f6459e9..2056d32 100644 --- a/examples/stm32/ow_ds18b20_rtos_stm32f429zi_nucleo/inc/lwow_opts.h +++ b/examples/stm32/ow_ds18b20_rtos_stm32f429zi_nucleo/inc/lwow_opts.h @@ -29,7 +29,7 @@ * This file is part of LwOW. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #ifndef LWOW_HDR_OPTS_H #define LWOW_HDR_OPTS_H diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f429zi_nucleo/inc/main.h b/examples/stm32/ow_ds18b20_rtos_stm32f429zi_nucleo/inc/main.h index dd8afe5..b168bfb 100644 --- a/examples/stm32/ow_ds18b20_rtos_stm32f429zi_nucleo/inc/main.h +++ b/examples/stm32/ow_ds18b20_rtos_stm32f429zi_nucleo/inc/main.h @@ -27,7 +27,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #ifndef __MAIN_H #define __MAIN_H diff --git a/examples/stm32/ow_ds18b20_rtos_stm32f429zi_nucleo/src/main.c b/examples/stm32/ow_ds18b20_rtos_stm32f429zi_nucleo/src/main.c index 801b6d8..f525594 100644 --- a/examples/stm32/ow_ds18b20_rtos_stm32f429zi_nucleo/src/main.c +++ b/examples/stm32/ow_ds18b20_rtos_stm32f429zi_nucleo/src/main.c @@ -27,7 +27,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #include "main.h" #include "cmsis_os.h" diff --git a/examples/stm32/ow_ds18b20_rtos_stm32l496g_discovery/inc/lwow_opts.h b/examples/stm32/ow_ds18b20_rtos_stm32l496g_discovery/inc/lwow_opts.h index f6459e9..2056d32 100644 --- a/examples/stm32/ow_ds18b20_rtos_stm32l496g_discovery/inc/lwow_opts.h +++ b/examples/stm32/ow_ds18b20_rtos_stm32l496g_discovery/inc/lwow_opts.h @@ -29,7 +29,7 @@ * This file is part of LwOW. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #ifndef LWOW_HDR_OPTS_H #define LWOW_HDR_OPTS_H diff --git a/examples/stm32/ow_ds18b20_rtos_stm32l496g_discovery/inc/main.h b/examples/stm32/ow_ds18b20_rtos_stm32l496g_discovery/inc/main.h index 3f55fd2..f1d57a4 100644 --- a/examples/stm32/ow_ds18b20_rtos_stm32l496g_discovery/inc/main.h +++ b/examples/stm32/ow_ds18b20_rtos_stm32l496g_discovery/inc/main.h @@ -27,7 +27,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #ifndef __MAIN_H #define __MAIN_H diff --git a/examples/stm32/ow_ds18b20_rtos_stm32l496g_discovery/src/main.c b/examples/stm32/ow_ds18b20_rtos_stm32l496g_discovery/src/main.c index 2c94ef4..e7d418d 100644 --- a/examples/stm32/ow_ds18b20_rtos_stm32l496g_discovery/src/main.c +++ b/examples/stm32/ow_ds18b20_rtos_stm32l496g_discovery/src/main.c @@ -27,7 +27,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #include "main.h" #include "cmsis_os.h" diff --git a/examples/stm32/ow_ds18b20_stm32l496g_discovery/inc/lwow_opts.h b/examples/stm32/ow_ds18b20_stm32l496g_discovery/inc/lwow_opts.h index 60e767d..a436de6 100644 --- a/examples/stm32/ow_ds18b20_stm32l496g_discovery/inc/lwow_opts.h +++ b/examples/stm32/ow_ds18b20_stm32l496g_discovery/inc/lwow_opts.h @@ -29,7 +29,7 @@ * This file is part of LwOW. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #ifndef LWOW_HDR_OPTS_H #define LWOW_HDR_OPTS_H diff --git a/examples/stm32/ow_ds18b20_stm32l496g_discovery/inc/main.h b/examples/stm32/ow_ds18b20_stm32l496g_discovery/inc/main.h index 3f55fd2..f1d57a4 100644 --- a/examples/stm32/ow_ds18b20_stm32l496g_discovery/inc/main.h +++ b/examples/stm32/ow_ds18b20_stm32l496g_discovery/inc/main.h @@ -27,7 +27,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #ifndef __MAIN_H #define __MAIN_H diff --git a/examples/stm32/ow_ds18b20_stm32l496g_discovery/src/main.c b/examples/stm32/ow_ds18b20_stm32l496g_discovery/src/main.c index 856d760..7639028 100644 --- a/examples/stm32/ow_ds18b20_stm32l496g_discovery/src/main.c +++ b/examples/stm32/ow_ds18b20_stm32l496g_discovery/src/main.c @@ -27,7 +27,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #include "main.h" #include "lwow/lwow.h" diff --git a/lwow/src/devices/lwow_device_ds18x20.c b/lwow/src/devices/lwow_device_ds18x20.c index 6ce2665..afd79a0 100644 --- a/lwow/src/devices/lwow_device_ds18x20.c +++ b/lwow/src/devices/lwow_device_ds18x20.c @@ -29,7 +29,7 @@ * This file is part of LwOW - Lightweight onewire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #include "lwow/lwow.h" #include "lwow/devices/lwow_device_ds18x20.h" diff --git a/lwow/src/include/lwow/devices/lwow_device_ds18x20.h b/lwow/src/include/lwow/devices/lwow_device_ds18x20.h index d87e6eb..5e2d405 100644 --- a/lwow/src/include/lwow/devices/lwow_device_ds18x20.h +++ b/lwow/src/include/lwow/devices/lwow_device_ds18x20.h @@ -29,7 +29,7 @@ * This file is part of LwOW - Lightweight onewire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #ifndef LWOW_HDR_DEVICE_DS18x20_H #define LWOW_HDR_DEVICE_DS18x20_H diff --git a/lwow/src/include/lwow/lwow.h b/lwow/src/include/lwow/lwow.h index b949a48..9c77282 100644 --- a/lwow/src/include/lwow/lwow.h +++ b/lwow/src/include/lwow/lwow.h @@ -29,7 +29,7 @@ * This file is part of LwOW - Lightweight onewire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #ifndef LWOW_HDR_H #define LWOW_HDR_H diff --git a/lwow/src/include/lwow/lwow_opt.h b/lwow/src/include/lwow/lwow_opt.h index 548a20d..cf09c74 100644 --- a/lwow/src/include/lwow/lwow_opt.h +++ b/lwow/src/include/lwow/lwow_opt.h @@ -29,7 +29,7 @@ * This file is part of LwOW - Lightweight onewire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #ifndef LWOW_HDR_OPT_H #define LWOW_HDR_OPT_H diff --git a/lwow/src/include/lwow/lwow_opts_template.h b/lwow/src/include/lwow/lwow_opts_template.h index ff87f96..dfbda9c 100644 --- a/lwow/src/include/lwow/lwow_opts_template.h +++ b/lwow/src/include/lwow/lwow_opts_template.h @@ -29,7 +29,7 @@ * This file is part of LwOW - Lightweight onewire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #ifndef LWOW_HDR_OPTS_H #define LWOW_HDR_OPTS_H diff --git a/lwow/src/lwow/lwow.c b/lwow/src/lwow/lwow.c index bdc6f83..d314e9b 100644 --- a/lwow/src/lwow/lwow.c +++ b/lwow/src/lwow/lwow.c @@ -29,7 +29,7 @@ * This file is part of LwOW - Lightweight onewire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #include #include "lwow/lwow.h" diff --git a/lwow/src/system/lwow_ll_stm32.c b/lwow/src/system/lwow_ll_stm32.c index 641f782..519a805 100644 --- a/lwow/src/system/lwow_ll_stm32.c +++ b/lwow/src/system/lwow_ll_stm32.c @@ -29,7 +29,7 @@ * This file is part of LwOW - Lightweight onewire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ /* diff --git a/lwow/src/system/lwow_ll_stm32_hal.c b/lwow/src/system/lwow_ll_stm32_hal.c index efccf01..f25fe62 100644 --- a/lwow/src/system/lwow_ll_stm32_hal.c +++ b/lwow/src/system/lwow_ll_stm32_hal.c @@ -29,7 +29,7 @@ * This file is part of LwOW - Lightweight onewire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ /* diff --git a/lwow/src/system/lwow_ll_stm32f401re_nucleo.c b/lwow/src/system/lwow_ll_stm32f401re_nucleo.c index 4514009..6036395 100644 --- a/lwow/src/system/lwow_ll_stm32f401re_nucleo.c +++ b/lwow/src/system/lwow_ll_stm32f401re_nucleo.c @@ -29,7 +29,7 @@ * This file is part of LwOW - Lightweight onewire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ /* diff --git a/lwow/src/system/lwow_ll_stm32f429zi_nucleo.c b/lwow/src/system/lwow_ll_stm32f429zi_nucleo.c index 80a8401..cf3268b 100644 --- a/lwow/src/system/lwow_ll_stm32f429zi_nucleo.c +++ b/lwow/src/system/lwow_ll_stm32f429zi_nucleo.c @@ -29,7 +29,7 @@ * This file is part of LwOW - Lightweight onewire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ /* diff --git a/lwow/src/system/lwow_ll_stm32l0xx.c b/lwow/src/system/lwow_ll_stm32l0xx.c index 24e4adf..d165eb8 100644 --- a/lwow/src/system/lwow_ll_stm32l0xx.c +++ b/lwow/src/system/lwow_ll_stm32l0xx.c @@ -29,7 +29,7 @@ * This file is part of LwOW - Lightweight onewire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ /* diff --git a/lwow/src/system/lwow_ll_stm32l496g_discovery.c b/lwow/src/system/lwow_ll_stm32l496g_discovery.c index bb2c406..f90ead7 100644 --- a/lwow/src/system/lwow_ll_stm32l496g_discovery.c +++ b/lwow/src/system/lwow_ll_stm32l496g_discovery.c @@ -29,7 +29,7 @@ * This file is part of LwOW - Lightweight onewire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ /* diff --git a/lwow/src/system/lwow_ll_template.c b/lwow/src/system/lwow_ll_template.c index 9d0af58..81cabac 100644 --- a/lwow/src/system/lwow_ll_template.c +++ b/lwow/src/system/lwow_ll_template.c @@ -29,7 +29,7 @@ * This file is part of LwOW - Lightweight onewire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #include "system/lwow_ll.h" diff --git a/lwow/src/system/lwow_ll_win32.c b/lwow/src/system/lwow_ll_win32.c index eb87a43..c6a5923 100644 --- a/lwow/src/system/lwow_ll_win32.c +++ b/lwow/src/system/lwow_ll_win32.c @@ -29,7 +29,7 @@ * This file is part of LwOW - Lightweight onewire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #include #include "lwow/lwow.h" diff --git a/lwow/src/system/lwow_sys_cmsis_os.c b/lwow/src/system/lwow_sys_cmsis_os.c index 9fba7a0..dc5e1e1 100644 --- a/lwow/src/system/lwow_sys_cmsis_os.c +++ b/lwow/src/system/lwow_sys_cmsis_os.c @@ -29,7 +29,7 @@ * This file is part of LwOW - Lightweight onewire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #include "lwow/lwow.h" diff --git a/lwow/src/system/lwow_sys_template.c b/lwow/src/system/lwow_sys_template.c index b401333..90b2b1d 100644 --- a/lwow/src/system/lwow_sys_template.c +++ b/lwow/src/system/lwow_sys_template.c @@ -29,7 +29,7 @@ * This file is part of LwOW - Lightweight onewire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #include "lwow/lwow.h" diff --git a/lwow/src/system/lwow_sys_win32.c b/lwow/src/system/lwow_sys_win32.c index dd2d8cb..d0f228e 100644 --- a/lwow/src/system/lwow_sys_win32.c +++ b/lwow/src/system/lwow_sys_win32.c @@ -29,7 +29,7 @@ * This file is part of LwOW - Lightweight onewire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ #include "lwow/lwow.h" #include "windows.h" diff --git a/lwow/src/system/ow_ll_stm32.c b/lwow/src/system/ow_ll_stm32.c index a243254..c57ad6d 100644 --- a/lwow/src/system/ow_ll_stm32.c +++ b/lwow/src/system/ow_ll_stm32.c @@ -29,7 +29,7 @@ * This file is part of LwOW - Lightweight onewire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ /* diff --git a/lwow/src/system/ow_ll_stm32_hal.c b/lwow/src/system/ow_ll_stm32_hal.c index e1bbd17..1bf11e2 100644 --- a/lwow/src/system/ow_ll_stm32_hal.c +++ b/lwow/src/system/ow_ll_stm32_hal.c @@ -29,7 +29,7 @@ * This file is part of LwOW - Lightweight onewire library. * * Author: Tilen MAJERLE - * Version: v3.0.1 + * Version: v3.0.2 */ /*