forked from labtroll/KiCad-DesignRules
-
Notifications
You must be signed in to change notification settings - Fork 2
/
JLCPCB.kicad_dru
219 lines (181 loc) · 7.34 KB
/
JLCPCB.kicad_dru
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
(version 1)
# Custom Design Rules (DRC) for KiCAD 7.0 (Stored in '<project>.kicad_dru' file).
#
# Matching JLCPCB capabilities: https://jlcpcb.com/capabilities/pcb-capabilities
#
# KiCad documentation: https://docs.kicad.org/master/id/pcbnew/pcbnew_advanced.html#custom_design_rules
#
# Inspiration
# - https://gist.github.com/darkxst/f713268e5469645425eed40115fb8b49 (with comments)
# - https://gist.github.com/denniskupec/e163d13b0a64c2044bd259f64659485e (with comments)
# TODO new rule: NPTH pads.
# Inner diameter of pad should be 0.4-0.5 mm larger than NPTH drill diameter.
# JLCPCB: "We make NPTH via dry sealing film process, if customer would like a NPTH but around with pad/copper, our engineer will dig out around pad/copper about 0.2mm-0.25mm, otherwise the metal potion will be flowed into the hole and it becomes a PTH. (there will be no copper dig out optimization for single board)."
# TODO: new rule for plated slots: min diameter/width 0.5mm
# JLCPCB: "The minimum plated slot width is 0.5mm, which is drawn with a pad."
# TODO new rule: non-plated slots: min diameter/width 1.0mm
# JLCPCB: "The minimum Non-Plated Slot Width is 1.0mm, please draw the slot outline in the mechanical layer(GML or GKO)""
# --- Drill/Hole Size ---
(rule "JLCPCB: Drill Hole Size"
# Choose between:
# 1-2 Layers
# (constraint hole_size (min 0.3mm) (max 6.3mm))
# 4-6 Layers (more costly)
# (constraint hole_size (min 0.15mm) (max 6.3mm))
# 4-6 Layers (preferred)
(constraint hole_size (min 0.2mm) (max 6.3mm))
)
(rule "JLCPCB: Via Hole Size"
(condition "A.Type == 'Via'")
# Choose between:
# 1-2 Layers
# (constraint hole_size (min 0.3mm))
# 4-6 Layers (more costly)
# (constraint hole_size (min 0.15mm))
# 4-6 Layers (preferred)
(constraint hole_size (min 0.2mm))
)
(rule "JLCPCB: Via Annular Ring"
(condition "A.Type == 'Via'")
# Choose between:
# 1-6 Layers
# (constraint annular_width (min 0.05mm))
# 1-6 Layers (preferred)
(constraint annular_width (min 0.075mm))
)
(rule "JLCPCB: PTH Hole Size"
(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && A.isPlated()")
(constraint hole_size (min 0.2mm) (max 6.3mm))
)
(rule "JLCPCB: NPTH Hole Size"
(condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical' && !A.isPlated()")
(constraint hole_size (min 0.5mm))
)
# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm.
(rule "JLCPCB: Castellated Hole Size"
(layer outer)
(condition "A.Type == 'Pad' && A.Fabrication_Property == 'Castellated pad'")
(constraint hole_size (min 0.6mm))
)
(rule "JLCPCB: PTH Annular Ring"
(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && A.isPlated()")
(constraint annular_width (min 0.075mm))
)
(rule "JLCPCB: NPTH Annular Ring"
(condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical' && !A.isPlated()")
(constraint annular_width (min 0.25mm))
)
# An expensive 4-Wire Kelvin Test is automatically added for holes that are < 0.3mm with a diameter ≤ 0.4mm.
(rule "JLCPCB: Avoid 4-Wire Kelvin Test"
(condition "(A.Type == 'Via' && A.Hole < 0.3mm && A.Diameter <= 0.4mm) || (A.Type == 'Pad' && ((A.Hole_Size_X < 0.3mm && A.Size_X <= 0.4mm) || (A.Hole_Size_Y < 0.3mm && A.Size_Y <= 0.4mm)))")
# 4-6 Layers
(constraint annular_width (min 0.125mm))
)
# --- Minimum Clearance ---
(rule "JLCPCB: Hole to Hole Clearance (Different Nets)"
(condition "A.Net != B.Net")
(constraint hole_to_hole (min 0.5mm))
)
(rule "JLCPCB: Via Hole to Via Hole Clearance (Same Net)"
(condition "A.Type == 'Via' && B.Type == 'Via' && A.Net == B.Net")
(constraint hole_to_hole (min 0.254mm))
)
(rule "JLCPCB: Pad to Pad Clearance (Pad without Hole, Different Nets)"
(condition "A.Type == 'Pad' && (A.Pad_Type != 'Through-hole' && A.Pad_Type != 'NPTH, mechanical') && B.Type == 'Pad' && (B.Pad_Type != 'Through-hole' && B.Pad_Type != 'NPTH, mechanical') && A.Net != B.Net")
(constraint clearance (min 0.127mm))
)
(rule "JLCPCB: Pad Hole to Pad Hole Clearance (Pad with Hole, Different Nets)"
(condition "A.Type == 'Pad' && (A.Pad_Type == 'Through-hole' || A.Pad_Type == 'NPTH, mechanical') && B.Type == 'Pad' && (B.Pad_Type == 'Through-hole' || B.Pad_Type == 'NPTH, mechanical') && A.Net != B.Net")
(constraint hole_to_hole (min 0.5mm))
)
# NOTE: This is not stated specifically, but is implied by other rules.
(rule "JLCPCB: Via/Pad to Via/Pad Clearance (Different Nets)"
(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
(constraint clearance (min 0.127mm))
)
# NOTE: This is not stated specifically, but is implied by other rules.
(rule "JLCPCB: Via/Pad Hole to Via/Pad Hole Clearance (Same Net)"
(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net == B.Net")
(constraint hole_to_hole (min 0.254mm))
)
(rule "JLCPCB: Via to Trace"
(condition "A.Type == 'Via' && B.Type == 'Track'")
(constraint hole_clearance (min 0.254mm))
)
(rule "JLCPCB: PTH to Trace"
(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && A.isPlated() && B.Type == 'Track'")
(constraint hole_clearance (min 0.33mm))
)
(rule "JLCPCB: NPTH to Trace"
(condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical' && !A.isPlated() && B.Type == 'Track'")
(constraint hole_clearance (min 0.254mm))
)
(rule "JLCPCB: Pad to Trace"
(condition "A.Type == 'Pad' && (A.Pad_Type == 'Through-hole' || A.Pad_Type == 'NPTH, mechanical') && B.Type == 'Track' && A.Net != B.Net")
(constraint clearance (min 0.2mm))
)
# --- Minimum Trace Width and Spacing ---
(rule "JLCPCB: Trace Width (Outer Layer)"
(layer outer)
(condition "A.Type == 'Track'")
# Choose between:
# 1-2 Layers (1oz)
# (constraint track_width (min 0.127mm))
# 4-6 Layers (1oz and 0.5oz)
(constraint track_width (min 0.09mm))
# 1-6 Layers (2oz)
# (constraint track_width (min 0.2mm))
)
(rule "JLCPCB: Trace Spacing (Outer Layer)"
(layer outer)
(condition "A.Type == 'Track' && B.Type == 'Track'")
# Choose between:
# 1-2 Layers (1oz)
# (constraint clearance (min 0.127mm))
# 4-6 Layers (1oz and 0.5oz)
(constraint clearance (min 0.09mm))
# 1-6 Layers (2oz)
# (constraint clearance (min 0.2mm))
)
(rule "JLCPCB: Trace Width (Inner Layer)"
(layer inner)
(condition "A.Type == 'Track'")
# Choose between:
# 4-6 Layers (1oz and 0.5oz)
(constraint track_width (min 0.09mm))
# 4-6 Layers (2oz)
# (constraint track_width (min 0.2mm))
)
(rule "JLCPCB: Trace Spacing (Inner Layer)"
(layer inner)
(condition "A.Type == 'Track' && B.Type == 'Track'")
# Choose between:
# 4-6 Layers (1oz and 0.5oz)
(constraint clearance (min 0.09mm))
# 4-6 Layers (2oz)
# (constraint clearance (min 0.2mm))
)
# --- Legend ---
(rule "JLCPCB: Minimum Line Width"
(layer "?.Silkscreen")
(condition "A.Type == 'Text' || A.Type == 'Text Box'")
(constraint text_thickness (min 0.15mm))
)
(rule "JLCPCB: Minimum Text Height"
(layer "?.Silkscreen")
(condition "A.Type == 'Text' || A.Type == 'Text Box'")
(constraint text_height (min 1mm))
)
(rule "JLCPCB: Pad to Silkscreen"
(condition "A.Type == 'Pad' && ((A.existsOnLayer('F.Mask') && B.Layer == 'F.Silkscreen') || (A.existsOnLayer('B.Mask') && B.Layer == 'B.Silkscreen')) ")
(constraint silk_clearance (min 0.15mm))
)
# --- Board Outlines ---
(rule "JLCPCB: Trace to Board Edge"
(condition "A.Type == 'Track'")
# Choose between:
# Routed
(constraint edge_clearance (min 0.3mm))
# V-Cut Panel
# (constraint edge_clearance (min 0.4mm))
)